[PATCH v3 1/6] drm/bridge: tc358767: Split tc_pxl_pll_en() into parameter calculation and enablement

[PATCH v3 1/6] drm/bridge: tc358767: Split tc_pxl_pll_en() into parameter calculation and enablement

[Marek Vasut]

Split tc_pxl_pll_en() into tc_pxl_pll_calc() which does only Pixel PLL
parameter calculation and tc_pxl_pll_en() which calls tc_pxl_pll_calc()
and then configures the Pixel PLL register.

This is a preparatory patch for further rework, where tc_pxl_pll_calc()
will also be used to find out the exact clock frequency generated by the
Pixel PLL. This frequency will be used as adjusted_mode clock frequency
and passed down the display pipeline to obtain exactly this frequency
on input into this bridge.

The precise input frequency that matches the Pixel PLL frequency is
important for this bridge, as if the frequencies do not match, the
bridge does suffer VFIFO overruns or underruns.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: David Airlie <airlied@gmail.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: dri-devel@lists.freedesktop.org
Cc: kernel@dh-electronics.com
---
V2: No change
V3: No change
---
 drivers/gpu/drm/bridge/tc358767.c | 37 +++++++++++++++++++++----------
 1 file changed, 25 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index b0435c8b754b4..cbb342d811ac3 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -580,14 +580,9 @@ static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
 	return 0;
 }
 
-static u32 div64_round_up(u64 v, u32 d)
+static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock,
+			   int *out_best_pixelclock, u32 *out_pxl_pllparam)
 {
-	return div_u64(v + d - 1, d);
-}
-
-static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
-{
-	int ret;
 	int i_pre, best_pre = 1;
 	int i_post, best_post = 1;
 	int div, best_div = 1;
@@ -683,11 +678,6 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
 	if (best_mul == 128)
 		best_mul = 0;
 
-	/* Power up PLL and switch to bypass */
-	ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
-	if (ret)
-		return ret;
-
 	pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
 	pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
 	pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
@@ -695,6 +685,29 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
 	pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
 	pxl_pllparam |= best_mul; /* Multiplier for PLL */
 
+	if (out_best_pixelclock)
+		*out_best_pixelclock = best_pixelclock;
+
+	if (out_pxl_pllparam)
+		*out_pxl_pllparam = pxl_pllparam;
+
+	return 0;
+}
+
+static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
+{
+	u32 pxl_pllparam = 0;
+	int ret;
+
+	ret = tc_pxl_pll_calc(tc, refclk, pixelclock, NULL, &pxl_pllparam);
+	if (ret)
+		return ret;
+
+	/* Power up PLL and switch to bypass */
+	ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
+	if (ret)
+		return ret;
+
 	ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
 	if (ret)
 		return ret;
-- 
2.43.0

[PATCH v3 2/6] drm/bridge: tc358767: Use tc_pxl_pll_calc() to correct adjusted_mode clock

[Marek Vasut]

Use tc_pxl_pll_calc() to find out the exact clock frequency generated by the
Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency and
pass it down the display pipeline to obtain exactly this frequency on input
into this bridge.

The precise input frequency that matches the Pixel PLL frequency is
important for this bridge, as if the frequencies do not match, the
bridge does suffer VFIFO overruns or underruns.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: David Airlie <airlied@gmail.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: dri-devel@lists.freedesktop.org
Cc: kernel@dh-electronics.com
---
V2: - Use mode clock as input into tc_pxl_pll_calc() to avoid
      accumulating rounding error
V3: No change
---
 drivers/gpu/drm/bridge/tc358767.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index cbb342d811ac3..20be21660ba76 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -1619,6 +1619,18 @@ static int tc_dpi_atomic_check(struct drm_bridge *bridge,
 			       struct drm_crtc_state *crtc_state,
 			       struct drm_connector_state *conn_state)
 {
+	struct tc_data *tc = bridge_to_tc(bridge);
+	int adjusted_clock = 0;
+	int ret;
+
+	ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
+			      crtc_state->mode.clock * 1000,
+			      &adjusted_clock, NULL);
+	if (ret)
+		return ret;
+
+	crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
+
 	/* DSI->DPI interface clock limitation: upto 100 MHz */
 	if (crtc_state->adjusted_mode.clock > 100000)
 		return -EINVAL;
@@ -1631,6 +1643,18 @@ static int tc_edp_atomic_check(struct drm_bridge *bridge,
 			       struct drm_crtc_state *crtc_state,
 			       struct drm_connector_state *conn_state)
 {
+	struct tc_data *tc = bridge_to_tc(bridge);
+	int adjusted_clock = 0;
+	int ret;
+
+	ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
+			      crtc_state->mode.clock * 1000,
+			      &adjusted_clock, NULL);
+	if (ret)
+		return ret;
+
+	crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
+
 	/* DPI->(e)DP interface clock limitation: upto 154 MHz */
 	if (crtc_state->adjusted_mode.clock > 154000)
 		return -EINVAL;
-- 
2.43.0

[PATCH v3 3/6] drm/bridge: tc358767: Drop line_pixel_subtract

[Marek Vasut]

This line_pixel_subtract is no longer needed now that the bridge can
request and obtain specific pixel clock on input to the bridge, with
clock frequency that matches the Pixel PLL frequency.

The line_pixel_subtract is now always 0, so drop it entirely.

The line_pixel_subtract was not reliable as it never worked when the
Pixel PLL and input clock were off just so that the required amount
of pixels to subtract would not be whole integer.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: David Airlie <airlied@gmail.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: dri-devel@lists.freedesktop.org
Cc: kernel@dh-electronics.com
---
V2: No change
V3: Fix up rebase artifact
---
 drivers/gpu/drm/bridge/tc358767.c | 16 +---------------
 1 file changed, 1 insertion(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 20be21660ba76..c4e2455ad95e4 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -382,9 +382,6 @@ struct tc_data {
 
 	/* HPD pin number (0 or 1) or -ENODEV */
 	int			hpd_pin;
-
-	/* Number of pixels to subtract from a line due to pixel clock delta */
-	u32			line_pixel_subtract;
 };
 
 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
@@ -661,11 +658,7 @@ static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock,
 		return -EINVAL;
 	}
 
-	tc->line_pixel_subtract = tc->mode.htotal -
-		div64_round_up(tc->mode.htotal * (u64)best_pixelclock, pixelclock);
-
-	dev_dbg(tc->dev, "PLL: got %d, delta %d (subtract %d px)\n", best_pixelclock,
-		best_delta, tc->line_pixel_subtract);
+	dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, best_delta);
 	dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
 		ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
 
@@ -909,13 +902,6 @@ static int tc_set_common_video_mode(struct tc_data *tc,
 		upper_margin, lower_margin, vsync_len);
 	dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
 
-	if (right_margin > tc->line_pixel_subtract) {
-		right_margin -= tc->line_pixel_subtract;
-	} else {
-		dev_err(tc->dev, "Bridge pixel clock too slow for mode\n");
-		right_margin = 0;
-	}
-
 	/*
 	 * LCD Ctl Frame Size
 	 * datasheet is not clear of vsdelay in case of DPI
-- 
2.43.0

[PATCH v3 4/6] drm/bridge: tc358767: Disable MIPI_DSI_CLOCK_NON_CONTINUOUS

[Marek Vasut]

The MIPI_DSI_CLOCK_NON_CONTINUOUS causes visible artifacts in high
resolution modes, disable it. Namely, in DSI->DP mode 1920x1200 24
bpp 59.95 Hz, with DSI bus at maximum 1 Gbps per lane setting, the
image contains jittering empty lines.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: David Airlie <airlied@gmail.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: dri-devel@lists.freedesktop.org
Cc: kernel@dh-electronics.com
---
V2: No change
V3: No change
---
 drivers/gpu/drm/bridge/tc358767.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index c4e2455ad95e4..a48454fe2f634 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -2303,7 +2303,7 @@ static int tc_mipi_dsi_host_attach(struct tc_data *tc)
 	dsi->lanes = dsi_lanes;
 	dsi->format = MIPI_DSI_FMT_RGB888;
 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
-			  MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
+			  MIPI_DSI_MODE_LPM;
 
 	ret = devm_mipi_dsi_attach(dev, dsi);
 	if (ret < 0) {
-- 
2.43.0

[PATCH v3 5/6] drm/bridge: tc358767: Set LSCLK divider for SYSCLK to 1

[Marek Vasut]

The only information in the datasheet regarding this divider is a note
in SYS_PLLPARAM register documentation which states that when LSCLK is
270 MHz, LSCLK_DIV should be 1. What should LSCLK_DIV be set to when
LSCLK is 162 MHz (for DP 1.62G mode) is unclear, but empirical test
confirms using LSCLK_DIV 1 has no adverse effects either. In the worst
case, the internal TC358767 clock would run faster.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: David Airlie <airlied@gmail.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: dri-devel@lists.freedesktop.org
Cc: kernel@dh-electronics.com
---
V2: No change
V3: No change
---
 drivers/gpu/drm/bridge/tc358767.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index a48454fe2f634..743bf1334923d 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -738,7 +738,7 @@ static int tc_stream_clock_calc(struct tc_data *tc)
 static int tc_set_syspllparam(struct tc_data *tc)
 {
 	unsigned long rate;
-	u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
+	u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_1;
 
 	rate = clk_get_rate(tc->refclk);
 	switch (rate) {
-- 
2.43.0

[PATCH v3 6/6] Revert "drm/bridge: tc358767: Set default CLRSIPO count"

[Marek Vasut]

This reverts commit 01338bb82fed40a6a234c2b36a92367c8671adf0.

With clock improvements in place, this seems to be no longer
necessary. Set the CLRSIPO to default setting recommended by
manufacturer.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: David Airlie <airlied@gmail.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: dri-devel@lists.freedesktop.org
Cc: kernel@dh-electronics.com
---
V2: No change
V3: No change
---
 drivers/gpu/drm/bridge/tc358767.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 743bf1334923d..2b035a136a6e5 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -1356,10 +1356,10 @@ static int tc_dsi_rx_enable(struct tc_data *tc)
 	u32 value;
 	int ret;
 
-	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
-	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
-	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
-	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
+	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);
+	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);
+	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);
+	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);
 	regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
 	regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
 	regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
-- 
2.43.0

Re: [PATCH v3 4/6] drm/bridge: tc358767: Disable MIPI_DSI_CLOCK_NON_CONTINUOUS

[Alexander Stein]

Hi,

Am Sonntag, 23. Juni 2024, 16:38:36 CEST schrieb Marek Vasut:
> The MIPI_DSI_CLOCK_NON_CONTINUOUS causes visible artifacts in high
> resolution modes, disable it. Namely, in DSI->DP mode 1920x1200 24
> bpp 59.95 Hz, with DSI bus at maximum 1 Gbps per lane setting, the
> image contains jittering empty lines.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>

I can't see these artifacts in 1920x1200 24bpp, but still looks good to me
Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>

> ---
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
> Cc: Jonas Karlman <jonas@kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Robert Foss <rfoss@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: kernel@dh-electronics.com
> ---
> V2: No change
> V3: No change
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index c4e2455ad95e4..a48454fe2f634 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -2303,7 +2303,7 @@ static int tc_mipi_dsi_host_attach(struct tc_data *tc)
>  	dsi->lanes = dsi_lanes;
>  	dsi->format = MIPI_DSI_FMT_RGB888;
>  	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
> -			  MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
> +			  MIPI_DSI_MODE_LPM;
>  
>  	ret = devm_mipi_dsi_attach(dev, dsi);
>  	if (ret < 0) {
> 


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH v3 6/6] Revert "drm/bridge: tc358767: Set default CLRSIPO count"

[Alexander Stein]

Am Sonntag, 23. Juni 2024, 16:38:38 CEST schrieb Marek Vasut:
> This reverts commit 01338bb82fed40a6a234c2b36a92367c8671adf0.
> 
> With clock improvements in place, this seems to be no longer
> necessary. Set the CLRSIPO to default setting recommended by
> manufacturer.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>

Although calculation sheet indicates this depends on DSI-Timings, this
works as well.
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

> ---
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
> Cc: Jonas Karlman <jonas@kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Robert Foss <rfoss@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: kernel@dh-electronics.com
> ---
> V2: No change
> V3: No change
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 743bf1334923d..2b035a136a6e5 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -1356,10 +1356,10 @@ static int tc_dsi_rx_enable(struct tc_data *tc)
>  	u32 value;
>  	int ret;
>  
> -	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
> -	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
> -	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
> -	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
> +	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);
> +	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);
> +	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);
> +	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);
>  	regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
>  	regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
>  	regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
> 


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Re: [PATCH v3 5/6] drm/bridge: tc358767: Set LSCLK divider for SYSCLK to 1

[Alexander Stein]

Am Sonntag, 23. Juni 2024, 16:38:37 CEST schrieb Marek Vasut:
> The only information in the datasheet regarding this divider is a note
> in SYS_PLLPARAM register documentation which states that when LSCLK is
> 270 MHz, LSCLK_DIV should be 1. What should LSCLK_DIV be set to when
> LSCLK is 162 MHz (for DP 1.62G mode) is unclear, but empirical test
> confirms using LSCLK_DIV 1 has no adverse effects either. In the worst
> case, the internal TC358767 clock would run faster.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>

Works also on a 2.7Gbps link.
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

> ---
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
> Cc: Jonas Karlman <jonas@kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Robert Foss <rfoss@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: kernel@dh-electronics.com
> ---
> V2: No change
> V3: No change
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index a48454fe2f634..743bf1334923d 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -738,7 +738,7 @@ static int tc_stream_clock_calc(struct tc_data *tc)
>  static int tc_set_syspllparam(struct tc_data *tc)
>  {
>  	unsigned long rate;
> -	u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
> +	u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_1;
>  
>  	rate = clk_get_rate(tc->refclk);
>  	switch (rate) {
> 


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Re: [PATCH v3 3/6] drm/bridge: tc358767: Drop line_pixel_subtract

[Alexander Stein]

Am Sonntag, 23. Juni 2024, 16:38:35 CEST schrieb Marek Vasut:
> This line_pixel_subtract is no longer needed now that the bridge can
> request and obtain specific pixel clock on input to the bridge, with
> clock frequency that matches the Pixel PLL frequency.
> 
> The line_pixel_subtract is now always 0, so drop it entirely.
> 
> The line_pixel_subtract was not reliable as it never worked when the
> Pixel PLL and input clock were off just so that the required amount
> of pixels to subtract would not be whole integer.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>

For me is even necessary to get the DP test mode running, using DSI as input.
With the removal of div64_round_up() from patch 1 addeded here:
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

> ---
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
> Cc: Jonas Karlman <jonas@kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Robert Foss <rfoss@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: kernel@dh-electronics.com
> ---
> V2: No change
> V3: Fix up rebase artifact
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 16 +---------------
>  1 file changed, 1 insertion(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 20be21660ba76..c4e2455ad95e4 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -382,9 +382,6 @@ struct tc_data {
>  
>  	/* HPD pin number (0 or 1) or -ENODEV */
>  	int			hpd_pin;
> -
> -	/* Number of pixels to subtract from a line due to pixel clock delta */
> -	u32			line_pixel_subtract;
>  };
>  
>  static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
> @@ -661,11 +658,7 @@ static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock,
>  		return -EINVAL;
>  	}
>  
> -	tc->line_pixel_subtract = tc->mode.htotal -
> -		div64_round_up(tc->mode.htotal * (u64)best_pixelclock, pixelclock);
> -
> -	dev_dbg(tc->dev, "PLL: got %d, delta %d (subtract %d px)\n", best_pixelclock,
> -		best_delta, tc->line_pixel_subtract);
> +	dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, best_delta);
>  	dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
>  		ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
>  
> @@ -909,13 +902,6 @@ static int tc_set_common_video_mode(struct tc_data *tc,
>  		upper_margin, lower_margin, vsync_len);
>  	dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
>  
> -	if (right_margin > tc->line_pixel_subtract) {
> -		right_margin -= tc->line_pixel_subtract;
> -	} else {
> -		dev_err(tc->dev, "Bridge pixel clock too slow for mode\n");
> -		right_margin = 0;
> -	}
> -
>  	/*
>  	 * LCD Ctl Frame Size
>  	 * datasheet is not clear of vsdelay in case of DPI
> 


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Re: [PATCH v3 2/6] drm/bridge: tc358767: Use tc_pxl_pll_calc() to correct adjusted_mode clock

[Alexander Stein]

Am Sonntag, 23. Juni 2024, 16:38:34 CEST schrieb Marek Vasut:
> Use tc_pxl_pll_calc() to find out the exact clock frequency generated by the
> Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency and
> pass it down the display pipeline to obtain exactly this frequency on input
> into this bridge.
> 
> The precise input frequency that matches the Pixel PLL frequency is
> important for this bridge, as if the frequencies do not match, the
> bridge does suffer VFIFO overruns or underruns.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>

This changes actually changes the media_disp1_pix clock to match the
configured PLL rate in the bridge. 147333000 instead of 148500000.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
> Cc: Jonas Karlman <jonas@kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Robert Foss <rfoss@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: kernel@dh-electronics.com
> ---
> V2: - Use mode clock as input into tc_pxl_pll_calc() to avoid
>       accumulating rounding error
> V3: No change
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index cbb342d811ac3..20be21660ba76 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -1619,6 +1619,18 @@ static int tc_dpi_atomic_check(struct drm_bridge *bridge,
>  			       struct drm_crtc_state *crtc_state,
>  			       struct drm_connector_state *conn_state)
>  {
> +	struct tc_data *tc = bridge_to_tc(bridge);
> +	int adjusted_clock = 0;
> +	int ret;
> +
> +	ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
> +			      crtc_state->mode.clock * 1000,
> +			      &adjusted_clock, NULL);
> +	if (ret)
> +		return ret;
> +
> +	crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
> +
>  	/* DSI->DPI interface clock limitation: upto 100 MHz */
>  	if (crtc_state->adjusted_mode.clock > 100000)
>  		return -EINVAL;
> @@ -1631,6 +1643,18 @@ static int tc_edp_atomic_check(struct drm_bridge *bridge,
>  			       struct drm_crtc_state *crtc_state,
>  			       struct drm_connector_state *conn_state)
>  {
> +	struct tc_data *tc = bridge_to_tc(bridge);
> +	int adjusted_clock = 0;
> +	int ret;
> +
> +	ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
> +			      crtc_state->mode.clock * 1000,
> +			      &adjusted_clock, NULL);
> +	if (ret)
> +		return ret;
> +
> +	crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
> +
>  	/* DPI->(e)DP interface clock limitation: upto 154 MHz */
>  	if (crtc_state->adjusted_mode.clock > 154000)
>  		return -EINVAL;
> 


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Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
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Re: [PATCH v3 1/6] drm/bridge: tc358767: Split tc_pxl_pll_en() into parameter calculation and enablement

[Alexander Stein]

Am Sonntag, 23. Juni 2024, 16:38:33 CEST schrieb Marek Vasut:
> Split tc_pxl_pll_en() into tc_pxl_pll_calc() which does only Pixel PLL
> parameter calculation and tc_pxl_pll_en() which calls tc_pxl_pll_calc()
> and then configures the Pixel PLL register.
> 
> This is a preparatory patch for further rework, where tc_pxl_pll_calc()
> will also be used to find out the exact clock frequency generated by the
> Pixel PLL. This frequency will be used as adjusted_mode clock frequency
> and passed down the display pipeline to obtain exactly this frequency
> on input into this bridge.
> 
> The precise input frequency that matches the Pixel PLL frequency is
> important for this bridge, as if the frequencies do not match, the
> bridge does suffer VFIFO overruns or underruns.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
> Cc: Jonas Karlman <jonas@kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Robert Foss <rfoss@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: kernel@dh-electronics.com
> ---
> V2: No change
> V3: No change
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 37 +++++++++++++++++++++----------
>  1 file changed, 25 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index b0435c8b754b4..cbb342d811ac3 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -580,14 +580,9 @@ static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
>  	return 0;
>  }
>  
> -static u32 div64_round_up(u64 v, u32 d)
> +static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock,
> +			   int *out_best_pixelclock, u32 *out_pxl_pllparam)
>  {
> -	return div_u64(v + d - 1, d);
> -}

There seems to be a rebase mishap. The removal of div64_round_up should be
put into patch 3. With that fixed:
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Best regards,
Alexander
> -
> -static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
> -{
> -	int ret;
>  	int i_pre, best_pre = 1;
>  	int i_post, best_post = 1;
>  	int div, best_div = 1;
> @@ -683,11 +678,6 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
>  	if (best_mul == 128)
>  		best_mul = 0;
>  
> -	/* Power up PLL and switch to bypass */
> -	ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
> -	if (ret)
> -		return ret;
> -
>  	pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
>  	pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
>  	pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
> @@ -695,6 +685,29 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
>  	pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
>  	pxl_pllparam |= best_mul; /* Multiplier for PLL */
>  
> +	if (out_best_pixelclock)
> +		*out_best_pixelclock = best_pixelclock;
> +
> +	if (out_pxl_pllparam)
> +		*out_pxl_pllparam = pxl_pllparam;
> +
> +	return 0;
> +}
> +
> +static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
> +{
> +	u32 pxl_pllparam = 0;
> +	int ret;
> +
> +	ret = tc_pxl_pll_calc(tc, refclk, pixelclock, NULL, &pxl_pllparam);
> +	if (ret)
> +		return ret;
> +
> +	/* Power up PLL and switch to bypass */
> +	ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
> +	if (ret)
> +		return ret;
> +
>  	ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
>  	if (ret)
>  		return ret;
> 


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Re: [PATCH v3 4/6] drm/bridge: tc358767: Disable MIPI_DSI_CLOCK_NON_CONTINUOUS

[Alexander Stein]

Am Montag, 24. Juni 2024, 09:45:13 CEST schrieb Alexander Stein:
> Hi,
> 
> Am Sonntag, 23. Juni 2024, 16:38:36 CEST schrieb Marek Vasut:
> > The MIPI_DSI_CLOCK_NON_CONTINUOUS causes visible artifacts in high
> > resolution modes, disable it. Namely, in DSI->DP mode 1920x1200 24
> > bpp 59.95 Hz, with DSI bus at maximum 1 Gbps per lane setting, the
> > image contains jittering empty lines.
> > 
> > Signed-off-by: Marek Vasut <marex@denx.de>
> 
> I can't see these artifacts in 1920x1200 24bpp, but still looks good to me
> Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>

I have to retract that. After checking for those mentioned artifacts
I noticed that the DP output was running without any issues.
There is something more going on here. Reverting this patch there wasn't
a single output problem.
This changes actually breaks my DSI connection randomly.
Sometimes it works, sometimes not. I also noticed that there wasn't even
a single DP link training failure, so I assume the DSI clock somehow
affected the internal state machine which even affected DP link training.
Until we know what's going on, NAK form me.

Best regards,
Alexander
> > ---
> > Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> > Cc: David Airlie <airlied@gmail.com>
> > Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
> > Cc: Jonas Karlman <jonas@kwiboo.se>
> > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> > Cc: Lucas Stach <l.stach@pengutronix.de>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Cc: Maxime Ripard <mripard@kernel.org>
> > Cc: Neil Armstrong <neil.armstrong@linaro.org>
> > Cc: Robert Foss <rfoss@kernel.org>
> > Cc: Thomas Zimmermann <tzimmermann@suse.de>
> > Cc: dri-devel@lists.freedesktop.org
> > Cc: kernel@dh-electronics.com
> > ---
> > V2: No change
> > V3: No change
> > ---
> >  drivers/gpu/drm/bridge/tc358767.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> > index c4e2455ad95e4..a48454fe2f634 100644
> > --- a/drivers/gpu/drm/bridge/tc358767.c
> > +++ b/drivers/gpu/drm/bridge/tc358767.c
> > @@ -2303,7 +2303,7 @@ static int tc_mipi_dsi_host_attach(struct tc_data *tc)
> >  	dsi->lanes = dsi_lanes;
> >  	dsi->format = MIPI_DSI_FMT_RGB888;
> >  	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
> > -			  MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
> > +			  MIPI_DSI_MODE_LPM;
> >  
> >  	ret = devm_mipi_dsi_attach(dev, dsi);
> >  	if (ret < 0) {
> > 
> 
> 
> 


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Re: [PATCH v3 4/6] drm/bridge: tc358767: Disable MIPI_DSI_CLOCK_NON_CONTINUOUS

[Marek Vasut]

On 6/24/24 11:06 AM, Alexander Stein wrote:
> Am Montag, 24. Juni 2024, 09:45:13 CEST schrieb Alexander Stein:
>> Hi,
>>
>> Am Sonntag, 23. Juni 2024, 16:38:36 CEST schrieb Marek Vasut:
>>> The MIPI_DSI_CLOCK_NON_CONTINUOUS causes visible artifacts in high
>>> resolution modes, disable it. Namely, in DSI->DP mode 1920x1200 24
>>> bpp 59.95 Hz, with DSI bus at maximum 1 Gbps per lane setting, the
>>> image contains jittering empty lines.
>>>
>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>
>> I can't see these artifacts in 1920x1200 24bpp, but still looks good to me
>> Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> 
> I have to retract that. After checking for those mentioned artifacts
> I noticed that the DP output was running without any issues.
> There is something more going on here. Reverting this patch there wasn't
> a single output problem.
> This changes actually breaks my DSI connection randomly.
> Sometimes it works, sometimes not. I also noticed that there wasn't even
> a single DP link training failure, so I assume the DSI clock somehow
> affected the internal state machine which even affected DP link training.
> Until we know what's going on, NAK form me.

I can temporarily drop this patch and keep the remaining five if that's 
OK with you ?