[PATCH 1/4] drm/amdgpu/gfx11: properly reference EOP interrupts for userqs

[PATCH 1/4] drm/amdgpu/gfx11: properly reference EOP interrupts for userqs

[Alex Deucher]

Regardless of whether we disable kernel queues, we need
to take an extra reference to the pipe interrupts for
user queues to make sure they stay enabled in case we
disable them for kernel queues.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 7274334ecd6fa..40d3c05326c02 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4836,10 +4836,10 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
 static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
 					      bool enable)
 {
-	if (adev->gfx.disable_kq) {
-		unsigned int irq_type;
-		int m, p, r;
+	unsigned int irq_type;
+	int m, p, r;
 
+	if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
 		for (m = 0; m < adev->gfx.me.num_me; m++) {
 			for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
 				irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
@@ -4853,7 +4853,9 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
 					return r;
 			}
 		}
+	}
 
+	if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
 		for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
 			for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
 				irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
@@ -4870,6 +4872,7 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
 			}
 		}
 	}
+
 	return 0;
 }
 
-- 
2.49.0

[PATCH 2/4] drm/amdgpu/gfx12: properly reference EOP interrupts for userqs

[Alex Deucher]

Regardless of whether we disable kernel queues, we need
to take an extra reference to the pipe interrupts for
user queues to make sure they stay enabled in case we
disable them for kernel queues.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index acfbf48482ef0..ff56368df66ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3684,10 +3684,10 @@ static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
 					      bool enable)
 {
-	if (adev->gfx.disable_kq) {
-		unsigned int irq_type;
-		int m, p, r;
+	unsigned int irq_type;
+	int m, p, r;
 
+	if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
 		for (m = 0; m < adev->gfx.me.num_me; m++) {
 			for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
 				irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
@@ -3701,7 +3701,9 @@ static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
 					return r;
 			}
 		}
+	}
 
+	if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
 		for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
 			for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
 				irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
@@ -3718,6 +3720,7 @@ static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
 			}
 		}
 	}
+
 	return 0;
 }
 
-- 
2.49.0

[PATCH 3/4] drm/sdma6: properly reference trap interrupts for userqs

[Alex Deucher]

We need to take a reference to the interrupts to make
sure they stay enabled even if the kernel queues have
disabled them.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 31 +++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 2249a1ef057bf..c3d53974e7f53 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1377,11 +1377,39 @@ static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)
 	return 0;
 }
 
+static int sdma_v6_0_set_userq_trap_interrupts(struct amdgpu_device *adev,
+					       bool enable)
+{
+	unsigned int irq_type;
+	int i, r;
+
+	if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) {
+		for (i = 0; i < adev->sdma.num_instances; i++) {
+			irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i;
+			if (enable)
+				r = amdgpu_irq_get(adev, &adev->sdma.trap_irq,
+						   irq_type);
+			else
+				r = amdgpu_irq_put(adev, &adev->sdma.trap_irq,
+						   irq_type);
+			if (r)
+				return r;
+		}
+	}
+
+	return 0;
+}
+
 static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
+	int r;
 
-	return sdma_v6_0_start(adev);
+	r = sdma_v6_0_start(adev);
+	if (r)
+		return r;
+
+	return sdma_v6_0_set_userq_trap_interrupts(adev, true);
 }
 
 static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -1393,6 +1421,7 @@ static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
 
 	sdma_v6_0_ctxempty_int_enable(adev, false);
 	sdma_v6_0_enable(adev, false);
+	sdma_v6_0_set_userq_trap_interrupts(adev, false);
 
 	return 0;
 }
-- 
2.49.0

[PATCH 4/4] drm/sdma7: properly reference trap interrupts for userqs

[Alex Deucher]

We need to take a reference to the interrupts to make
sure they stay enabled even if the kernel queues have
disabled them.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 31 +++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 1f3045323c929..669d1ef3fab22 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1352,11 +1352,39 @@ static int sdma_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)
 	return 0;
 }
 
+static int sdma_v7_0_set_userq_trap_interrupts(struct amdgpu_device *adev,
+					       bool enable)
+{
+	unsigned int irq_type;
+	int i, r;
+
+	if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) {
+		for (i = 0; i < adev->sdma.num_instances; i++) {
+			irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i;
+			if (enable)
+				r = amdgpu_irq_get(adev, &adev->sdma.trap_irq,
+						   irq_type);
+			else
+				r = amdgpu_irq_put(adev, &adev->sdma.trap_irq,
+						   irq_type);
+			if (r)
+				return r;
+		}
+	}
+
+	return 0;
+}
+
 static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
+	int r;
 
-	return sdma_v7_0_start(adev);
+	r = sdma_v7_0_start(adev);
+	if (r)
+		return r;
+
+	return sdma_v7_0_set_userq_trap_interrupts(adev, true);
 }
 
 static int sdma_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -1368,6 +1396,7 @@ static int sdma_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)
 
 	sdma_v7_0_ctx_switch_enable(adev, false);
 	sdma_v7_0_enable(adev, false);
+	sdma_v7_0_set_userq_trap_interrupts(adev, false);
 
 	return 0;
 }
-- 
2.49.0

Re: [PATCH 1/4] drm/amdgpu/gfx11: properly reference EOP interrupts for userqs

[Khatri, Sunil]

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This is how i see the future of this code and we can do based on it now 
itself.
disable_kq = 0, Use kernel queues.
disable_kq = 1, Use User queues.

In case of kernel queues we should not be even calling 
gfx_v11_0_set_userq_eop_interrupts at all. Instead its better if we add 
a this check "if (adev->userq_funcs[AMDGPU_HW_IP_GFX])" before calling 
the gfx_v11_0_set_userq_eop_interrupts. I am assuming there wont be any 
mixed use of kernel|user queues together. Let me know if you think 
otherwise. Regards Sunil Khatri

On 4/13/2025 9:36 PM, Alex Deucher wrote:
> Regardless of whether we disable kernel queues, we need
> to take an extra reference to the pipe interrupts for
> user queues to make sure they stay enabled in case we
> disable them for kernel queues.
>
> Signed-off-by: Alex Deucher<alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 ++++++---
>   1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 7274334ecd6fa..40d3c05326c02 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4836,10 +4836,10 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
>   static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>   					      bool enable)
>   {
> -	if (adev->gfx.disable_kq) {
> -		unsigned int irq_type;
> -		int m, p, r;
> +	unsigned int irq_type;
> +	int m, p, r;
>   
> +	if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
>   		for (m = 0; m < adev->gfx.me.num_me; m++) {
>   			for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
>   				irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
> @@ -4853,7 +4853,9 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>   					return r;
>   			}
>   		}
> +	}
>   
> +	if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
>   		for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
>   			for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
>   				irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> @@ -4870,6 +4872,7 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>   			}
>   		}
>   	}
> +
>   	return 0;
>   }
>   

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Re: [PATCH 1/4] drm/amdgpu/gfx11: properly reference EOP interrupts for userqs

[Khatri, Sunil]

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I feel existing implementation makes more sense. Using the disable_kq 
flag to avoid get/put completely. Get/put for userqueues only here and 
for kernel anyways we are handling in ring_init.

if (adev->userq_funcs[AMDGPU_HW_IP_GFX]), this if condition will always be valid once we enable it based on the fw version. so this will be an additional loop and get/put when kernel queues are being used.

Regards
Sunil Khatri

On 4/14/2025 3:12 PM, Khatri, Sunil wrote:

> This is how i see the future of this code and we can do based on it 
> now itself.
> disable_kq = 0, Use kernel queues.
> disable_kq = 1, Use User queues.
>
> In case of kernel queues we should not be even calling 
> gfx_v11_0_set_userq_eop_interrupts at all. Instead its better if we 
> add a this check "if (adev->userq_funcs[AMDGPU_HW_IP_GFX])" before 
> calling the gfx_v11_0_set_userq_eop_interrupts. I am assuming there 
> wont be any mixed use of kernel|user queues together. Let me know if 
> you think otherwise. Regards Sunil Khatri
>
> On 4/13/2025 9:36 PM, Alex Deucher wrote:
>> Regardless of whether we disable kernel queues, we need
>> to take an extra reference to the pipe interrupts for
>> user queues to make sure they stay enabled in case we
>> disable them for kernel queues.
>>
>> Signed-off-by: Alex Deucher<alexander.deucher@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 ++++++---
>>   1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> index 7274334ecd6fa..40d3c05326c02 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> @@ -4836,10 +4836,10 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
>>   static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>>   					      bool enable)
>>   {
>> -	if (adev->gfx.disable_kq) {
>> -		unsigned int irq_type;
>> -		int m, p, r;
>> +	unsigned int irq_type;
>> +	int m, p, r;
>>   
>> +	if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
>>   		for (m = 0; m < adev->gfx.me.num_me; m++) {
>>   			for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
>>   				irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
>> @@ -4853,7 +4853,9 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>>   					return r;
>>   			}
>>   		}
>> +	}
>>   
>> +	if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
>>   		for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
>>   			for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
>>   				irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
>> @@ -4870,6 +4872,7 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>>   			}
>>   		}
>>   	}
>> +
>>   	return 0;
>>   }
>>   

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Re: [PATCH 3/4] drm/sdma6: properly reference trap interrupts for userqs

[Khatri, Sunil]

Same explanation as patch 1 of the series here too. Do we want to depend 
on the disable_kq flag solely to enable/disable sdma trap.
IIUC, we dont want to do it in case of kernel queues at all and only 
needed when using userqueue and that is taken care by using the flag 
disable_kq.

Regards
Sunil Khatri

On 4/13/2025 9:36 PM, Alex Deucher wrote:
> We need to take a reference to the interrupts to make
> sure they stay enabled even if the kernel queues have
> disabled them.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 31 +++++++++++++++++++++++++-
>   1 file changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index 2249a1ef057bf..c3d53974e7f53 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -1377,11 +1377,39 @@ static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)
>   	return 0;
>   }
>   
> +static int sdma_v6_0_set_userq_trap_interrupts(struct amdgpu_device *adev,
> +					       bool enable)
> +{
> +	unsigned int irq_type;
> +	int i, r;
> +
> +	if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) {
> +		for (i = 0; i < adev->sdma.num_instances; i++) {
> +			irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i;
> +			if (enable)
> +				r = amdgpu_irq_get(adev, &adev->sdma.trap_irq,
> +						   irq_type);
> +			else
> +				r = amdgpu_irq_put(adev, &adev->sdma.trap_irq,
> +						   irq_type);
> +			if (r)
> +				return r;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
>   static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
>   {
>   	struct amdgpu_device *adev = ip_block->adev;
> +	int r;
>   
> -	return sdma_v6_0_start(adev);
> +	r = sdma_v6_0_start(adev);
> +	if (r)
> +		return r;
> +
> +	return sdma_v6_0_set_userq_trap_interrupts(adev, true);
>   }
>   
>   static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
> @@ -1393,6 +1421,7 @@ static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
>   
>   	sdma_v6_0_ctxempty_int_enable(adev, false);
>   	sdma_v6_0_enable(adev, false);
> +	sdma_v6_0_set_userq_trap_interrupts(adev, false);
>   
>   	return 0;
>   }

Re: [PATCH 1/4] drm/amdgpu/gfx11: properly reference EOP interrupts for userqs

[Alex Deucher]

On Mon, Apr 14, 2025 at 5:44 AM Khatri, Sunil <sukhatri@amd.com> wrote:
>
> This is how i see the future of this code and we can do based on it now itself.
> disable_kq = 0, Use kernel queues.
> disable_kq = 1, Use User queues.

disable_kq = 0 means allow kernel queues and user queues.  disable_kq
=1 means disable kernel queues.  I think we'd want to allow both at
least on current chips.  I think if we want a general knob for kernel
and user queues, we should do something like:
userq:
-1 auto (whatever we want the default to be per IP)
0 disable user queues (kernel queues only where supported)
1 enable user queues (user queues and kernel queues)
2 enable user queues only (disable kernel queues)

>
> In case of kernel queues we should not be even calling gfx_v11_0_set_userq_eop_interrupts at all. Instead its better if we add a this check "if (adev->userq_funcs[AMDGPU_HW_IP_GFX])" before calling the gfx_v11_0_set_userq_eop_interrupts. I am assuming there wont be any mixed use of kernel|user queues together. Let me know if you think otherwise. Regards Sunil Khatri

We should only be calling it if user queues are enabled.  I think
there will definitely be mixed user and kernel queues on current
hardware as we ramp up on user queues.

Alex

>
> On 4/13/2025 9:36 PM, Alex Deucher wrote:
>
> Regardless of whether we disable kernel queues, we need
> to take an extra reference to the pipe interrupts for
> user queues to make sure they stay enabled in case we
> disable them for kernel queues.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 7274334ecd6fa..40d3c05326c02 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4836,10 +4836,10 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
>  static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>        bool enable)
>  {
> - if (adev->gfx.disable_kq) {
> - unsigned int irq_type;
> - int m, p, r;
> + unsigned int irq_type;
> + int m, p, r;
>
> + if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
>   for (m = 0; m < adev->gfx.me.num_me; m++) {
>   for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
>   irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
> @@ -4853,7 +4853,9 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>   return r;
>   }
>   }
> + }
>
> + if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
>   for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
>   for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
>   irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> @@ -4870,6 +4872,7 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>   }
>   }
>   }
> +
>   return 0;
>  }
>

Re: [PATCH 3/4] drm/sdma6: properly reference trap interrupts for userqs

[Alex Deucher]

On Mon, Apr 14, 2025 at 5:59 AM Khatri, Sunil <sukhatri@amd.com> wrote:
>
> Same explanation as patch 1 of the series here too. Do we want to depend
> on the disable_kq flag solely to enable/disable sdma trap.
> IIUC, we dont want to do it in case of kernel queues at all and only
> needed when using userqueue and that is taken care by using the flag
> disable_kq.

I think doing it this way makes the most sense because you are using
the presence of user queues to determine whether or not to take the
extra references.  We don't really care what the status of kernel
queues are.

Alex

>
> Regards
> Sunil Khatri
>
> On 4/13/2025 9:36 PM, Alex Deucher wrote:
> > We need to take a reference to the interrupts to make
> > sure they stay enabled even if the kernel queues have
> > disabled them.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 31 +++++++++++++++++++++++++-
> >   1 file changed, 30 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> > index 2249a1ef057bf..c3d53974e7f53 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> > @@ -1377,11 +1377,39 @@ static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)
> >       return 0;
> >   }
> >
> > +static int sdma_v6_0_set_userq_trap_interrupts(struct amdgpu_device *adev,
> > +                                            bool enable)
> > +{
> > +     unsigned int irq_type;
> > +     int i, r;
> > +
> > +     if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) {
> > +             for (i = 0; i < adev->sdma.num_instances; i++) {
> > +                     irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i;
> > +                     if (enable)
> > +                             r = amdgpu_irq_get(adev, &adev->sdma.trap_irq,
> > +                                                irq_type);
> > +                     else
> > +                             r = amdgpu_irq_put(adev, &adev->sdma.trap_irq,
> > +                                                irq_type);
> > +                     if (r)
> > +                             return r;
> > +             }
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> >   static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
> >   {
> >       struct amdgpu_device *adev = ip_block->adev;
> > +     int r;
> >
> > -     return sdma_v6_0_start(adev);
> > +     r = sdma_v6_0_start(adev);
> > +     if (r)
> > +             return r;
> > +
> > +     return sdma_v6_0_set_userq_trap_interrupts(adev, true);
> >   }
> >
> >   static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
> > @@ -1393,6 +1421,7 @@ static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
> >
> >       sdma_v6_0_ctxempty_int_enable(adev, false);
> >       sdma_v6_0_enable(adev, false);
> > +     sdma_v6_0_set_userq_trap_interrupts(adev, false);
> >
> >       return 0;
> >   }

Re: [PATCH 1/4] drm/amdgpu/gfx11: properly reference EOP interrupts for userqs

[Khatri, Sunil]

[-- Attachment #1: Type: text/plain, Size: 3400 bytes --]


On 4/14/2025 8:59 PM, Alex Deucher wrote:
> On Mon, Apr 14, 2025 at 5:44 AM Khatri, Sunil<sukhatri@amd.com> wrote:
>> This is how i see the future of this code and we can do based on it now itself.
>> disable_kq = 0, Use kernel queues.
>> disable_kq = 1, Use User queues.
> disable_kq = 0 means allow kernel queues and user queues.  disable_kq
> =1 means disable kernel queues.  I think we'd want to allow both at
> least on current chips.  I think if we want a general knob for kernel
> and user queues, we should do something like:
> userq:
> -1 auto (whatever we want the default to be per IP)
> 0 disable user queues (kernel queues only where supported)
> 1 enable user queues (user queues and kernel queues)
> 2 enable user queues only (disable kernel queues)
>
>> In case of kernel queues we should not be even calling gfx_v11_0_set_userq_eop_interrupts at all. Instead its better if we add a this check "if (adev->userq_funcs[AMDGPU_HW_IP_GFX])" before calling the gfx_v11_0_set_userq_eop_interrupts. I am assuming there wont be any mixed use of kernel|user queues together. Let me know if you think otherwise. Regards Sunil Khatri
> We should only be calling it if user queues are enabled.  I think
> there will definitely be mixed user and kernel queues on current
> hardware as we ramp up on user queues.
Alex, are you saying we could expect some device where Kernel queues and 
user queues will be working in parallel ? If that is the case i can see 
we need eop reference for both the cases and this change then makes 
perfect sense but,  if its either kernel or user then disable_kq feature 
check looked better in control.


Regards
Sunil Khatri
> Alex
>
>> On 4/13/2025 9:36 PM, Alex Deucher wrote:
>>
>> Regardless of whether we disable kernel queues, we need
>> to take an extra reference to the pipe interrupts for
>> user queues to make sure they stay enabled in case we
>> disable them for kernel queues.
>>
>> Signed-off-by: Alex Deucher<alexander.deucher@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 ++++++---
>>   1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> index 7274334ecd6fa..40d3c05326c02 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> @@ -4836,10 +4836,10 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
>>   static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>>         bool enable)
>>   {
>> - if (adev->gfx.disable_kq) {
>> - unsigned int irq_type;
>> - int m, p, r;
>> + unsigned int irq_type;
>> + int m, p, r;
>>
>> + if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
>>    for (m = 0; m < adev->gfx.me.num_me; m++) {
>>    for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
>>    irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
>> @@ -4853,7 +4853,9 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>>    return r;
>>    }
>>    }
>> + }
>>
>> + if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
>>    for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
>>    for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
>>    irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
>> @@ -4870,6 +4872,7 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>>    }
>>    }
>>    }
>> +
>>    return 0;
>>   }
>>

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Re: [PATCH 1/4] drm/amdgpu/gfx11: properly reference EOP interrupts for userqs

[Alex Deucher]

On Mon, Apr 14, 2025 at 1:17 PM Khatri, Sunil <sukhatri@amd.com> wrote:
>
>
> On 4/14/2025 8:59 PM, Alex Deucher wrote:
>
> On Mon, Apr 14, 2025 at 5:44 AM Khatri, Sunil <sukhatri@amd.com> wrote:
>
> This is how i see the future of this code and we can do based on it now itself.
> disable_kq = 0, Use kernel queues.
> disable_kq = 1, Use User queues.
>
> disable_kq = 0 means allow kernel queues and user queues.  disable_kq
> =1 means disable kernel queues.  I think we'd want to allow both at
> least on current chips.  I think if we want a general knob for kernel
> and user queues, we should do something like:
> userq:
> -1 auto (whatever we want the default to be per IP)
> 0 disable user queues (kernel queues only where supported)
> 1 enable user queues (user queues and kernel queues)
> 2 enable user queues only (disable kernel queues)
>
> In case of kernel queues we should not be even calling gfx_v11_0_set_userq_eop_interrupts at all. Instead its better if we add a this check "if (adev->userq_funcs[AMDGPU_HW_IP_GFX])" before calling the gfx_v11_0_set_userq_eop_interrupts. I am assuming there wont be any mixed use of kernel|user queues together. Let me know if you think otherwise. Regards Sunil Khatri
>
> We should only be calling it if user queues are enabled.  I think
> there will definitely be mixed user and kernel queues on current
> hardware as we ramp up on user queues.
>
> Alex, are you saying we could expect some device where Kernel queues and user queues will be working in parallel ? If that is the case i can see we need eop reference for both the cases and this change then makes perfect sense but,  if its either kernel or user then disable_kq feature check looked better in control.
>

That's the case right now for gfx11 and gfx12 dGPUs.  Even if we did
add an option to disable user queues, everything would still work as
expected with the way things are coded in these patches.  The presence
of the userq function pointers determines whether user queues are
enabled for the IP.  If they are NULL, then we skip the extra
references so the logic works for any combination of user queues and
kernel queues.

Alex

>
> Regards
> Sunil Khatri
>
> Alex
>
> On 4/13/2025 9:36 PM, Alex Deucher wrote:
>
> Regardless of whether we disable kernel queues, we need
> to take an extra reference to the pipe interrupts for
> user queues to make sure they stay enabled in case we
> disable them for kernel queues.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 7274334ecd6fa..40d3c05326c02 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4836,10 +4836,10 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
>  static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>        bool enable)
>  {
> - if (adev->gfx.disable_kq) {
> - unsigned int irq_type;
> - int m, p, r;
> + unsigned int irq_type;
> + int m, p, r;
>
> + if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
>   for (m = 0; m < adev->gfx.me.num_me; m++) {
>   for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
>   irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
> @@ -4853,7 +4853,9 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>   return r;
>   }
>   }
> + }
>
> + if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
>   for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
>   for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
>   irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> @@ -4870,6 +4872,7 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>   }
>   }
>   }
> +
>   return 0;
>  }
>

Re: [PATCH 1/4] drm/amdgpu/gfx11: properly reference EOP interrupts for userqs

[Khatri, Sunil]

[-- Attachment #1: Type: text/plain, Size: 4120 bytes --]


On 4/14/2025 10:54 PM, Alex Deucher wrote:
> On Mon, Apr 14, 2025 at 1:17 PM Khatri, Sunil<sukhatri@amd.com> wrote:
>>
>> On 4/14/2025 8:59 PM, Alex Deucher wrote:
>>
>> On Mon, Apr 14, 2025 at 5:44 AM Khatri, Sunil<sukhatri@amd.com> wrote:
>>
>> This is how i see the future of this code and we can do based on it now itself.
>> disable_kq = 0, Use kernel queues.
>> disable_kq = 1, Use User queues.
>>
>> disable_kq = 0 means allow kernel queues and user queues.  disable_kq
>> =1 means disable kernel queues.  I think we'd want to allow both at
>> least on current chips.  I think if we want a general knob for kernel
>> and user queues, we should do something like:
>> userq:
>> -1 auto (whatever we want the default to be per IP)
>> 0 disable user queues (kernel queues only where supported)
>> 1 enable user queues (user queues and kernel queues)
>> 2 enable user queues only (disable kernel queues)
>>
>> In case of kernel queues we should not be even calling gfx_v11_0_set_userq_eop_interrupts at all. Instead its better if we add a this check "if (adev->userq_funcs[AMDGPU_HW_IP_GFX])" before calling the gfx_v11_0_set_userq_eop_interrupts. I am assuming there wont be any mixed use of kernel|user queues together. Let me know if you think otherwise. Regards Sunil Khatri
>>
>> We should only be calling it if user queues are enabled.  I think
>> there will definitely be mixed user and kernel queues on current
>> hardware as we ramp up on user queues.
>>
>> Alex, are you saying we could expect some device where Kernel queues and user queues will be working in parallel ? If that is the case i can see we need eop reference for both the cases and this change then makes perfect sense but,  if its either kernel or user then disable_kq feature check looked better in control.
>>
> That's the case right now for gfx11 and gfx12 dGPUs.  Even if we did
> add an option to disable user queues, everything would still work as
> expected with the way things are coded in these patches.  The presence
> of the userq function pointers determines whether user queues are
> enabled for the IP.  If they are NULL, then we skip the extra
> references so the logic works for any combination of user queues and
> kernel queues.
Fair enough,  we do enable the function pointers based on IP.

Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
> Alex
>
>> Regards
>> Sunil Khatri
>>
>> Alex
>>
>> On 4/13/2025 9:36 PM, Alex Deucher wrote:
>>
>> Regardless of whether we disable kernel queues, we need
>> to take an extra reference to the pipe interrupts for
>> user queues to make sure they stay enabled in case we
>> disable them for kernel queues.
>>
>> Signed-off-by: Alex Deucher<alexander.deucher@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 ++++++---
>>   1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> index 7274334ecd6fa..40d3c05326c02 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> @@ -4836,10 +4836,10 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
>>   static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>>         bool enable)
>>   {
>> - if (adev->gfx.disable_kq) {
>> - unsigned int irq_type;
>> - int m, p, r;
>> + unsigned int irq_type;
>> + int m, p, r;
>>
>> + if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
>>    for (m = 0; m < adev->gfx.me.num_me; m++) {
>>    for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
>>    irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
>> @@ -4853,7 +4853,9 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>>    return r;
>>    }
>>    }
>> + }
>>
>> + if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
>>    for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
>>    for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
>>    irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
>> @@ -4870,6 +4872,7 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>>    }
>>    }
>>    }
>> +
>>    return 0;
>>   }
>>

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Re: [PATCH 3/4] drm/sdma6: properly reference trap interrupts for userqs

[Khatri, Sunil]

On 4/14/2025 9:02 PM, Alex Deucher wrote:
> On Mon, Apr 14, 2025 at 5:59 AM Khatri, Sunil <sukhatri@amd.com> wrote:
>> Same explanation as patch 1 of the series here too. Do we want to depend
>> on the disable_kq flag solely to enable/disable sdma trap.
>> IIUC, we dont want to do it in case of kernel queues at all and only
>> needed when using userqueue and that is taken care by using the flag
>> disable_kq.
> I think doing it this way makes the most sense because you are using
> the presence of user queues to determine whether or not to take the
> extra references.  We don't really care what the status of kernel
> queues are.
With the understanding from patch 1. Reviewed-by: Sunil Khatri 
<sunil.khatri@amd.com>

Regards
Sunil Khatri
> Alex
>
>> Regards
>> Sunil Khatri
>>
>> On 4/13/2025 9:36 PM, Alex Deucher wrote:
>>> We need to take a reference to the interrupts to make
>>> sure they stay enabled even if the kernel queues have
>>> disabled them.
>>>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>>    drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 31 +++++++++++++++++++++++++-
>>>    1 file changed, 30 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>>> index 2249a1ef057bf..c3d53974e7f53 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>>> @@ -1377,11 +1377,39 @@ static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)
>>>        return 0;
>>>    }
>>>
>>> +static int sdma_v6_0_set_userq_trap_interrupts(struct amdgpu_device *adev,
>>> +                                            bool enable)
>>> +{
>>> +     unsigned int irq_type;
>>> +     int i, r;
>>> +
>>> +     if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) {
>>> +             for (i = 0; i < adev->sdma.num_instances; i++) {
>>> +                     irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i;
>>> +                     if (enable)
>>> +                             r = amdgpu_irq_get(adev, &adev->sdma.trap_irq,
>>> +                                                irq_type);
>>> +                     else
>>> +                             r = amdgpu_irq_put(adev, &adev->sdma.trap_irq,
>>> +                                                irq_type);
>>> +                     if (r)
>>> +                             return r;
>>> +             }
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>>    static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
>>>    {
>>>        struct amdgpu_device *adev = ip_block->adev;
>>> +     int r;
>>>
>>> -     return sdma_v6_0_start(adev);
>>> +     r = sdma_v6_0_start(adev);
>>> +     if (r)
>>> +             return r;
>>> +
>>> +     return sdma_v6_0_set_userq_trap_interrupts(adev, true);
>>>    }
>>>
>>>    static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
>>> @@ -1393,6 +1421,7 @@ static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
>>>
>>>        sdma_v6_0_ctxempty_int_enable(adev, false);
>>>        sdma_v6_0_enable(adev, false);
>>> +     sdma_v6_0_set_userq_trap_interrupts(adev, false);
>>>
>>>        return 0;
>>>    }

Re: [PATCH 4/4] drm/sdma7: properly reference trap interrupts for userqs

[Khatri, Sunil]

Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>

On 4/13/2025 9:36 PM, Alex Deucher wrote:
> We need to take a reference to the interrupts to make
> sure they stay enabled even if the kernel queues have
> disabled them.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 31 +++++++++++++++++++++++++-
>   1 file changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> index 1f3045323c929..669d1ef3fab22 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> @@ -1352,11 +1352,39 @@ static int sdma_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)
>   	return 0;
>   }
>   
> +static int sdma_v7_0_set_userq_trap_interrupts(struct amdgpu_device *adev,
> +					       bool enable)
> +{
> +	unsigned int irq_type;
> +	int i, r;
> +
> +	if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) {
> +		for (i = 0; i < adev->sdma.num_instances; i++) {
> +			irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i;
> +			if (enable)
> +				r = amdgpu_irq_get(adev, &adev->sdma.trap_irq,
> +						   irq_type);
> +			else
> +				r = amdgpu_irq_put(adev, &adev->sdma.trap_irq,
> +						   irq_type);
> +			if (r)
> +				return r;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
>   static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block)
>   {
>   	struct amdgpu_device *adev = ip_block->adev;
> +	int r;
>   
> -	return sdma_v7_0_start(adev);
> +	r = sdma_v7_0_start(adev);
> +	if (r)
> +		return r;
> +
> +	return sdma_v7_0_set_userq_trap_interrupts(adev, true);
>   }
>   
>   static int sdma_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)
> @@ -1368,6 +1396,7 @@ static int sdma_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)
>   
>   	sdma_v7_0_ctx_switch_enable(adev, false);
>   	sdma_v7_0_enable(adev, false);
> +	sdma_v7_0_set_userq_trap_interrupts(adev, false);
>   
>   	return 0;
>   }

Re: [PATCH 1/4] drm/amdgpu/gfx11: properly reference EOP interrupts for userqs

[Khatri, Sunil]

Series is Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>

On 4/13/2025 9:36 PM, Alex Deucher wrote:
> Regardless of whether we disable kernel queues, we need
> to take an extra reference to the pipe interrupts for
> user queues to make sure they stay enabled in case we
> disable them for kernel queues.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 9 ++++++---
>   1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 7274334ecd6fa..40d3c05326c02 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4836,10 +4836,10 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
>   static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>   					      bool enable)
>   {
> -	if (adev->gfx.disable_kq) {
> -		unsigned int irq_type;
> -		int m, p, r;
> +	unsigned int irq_type;
> +	int m, p, r;
>   
> +	if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
>   		for (m = 0; m < adev->gfx.me.num_me; m++) {
>   			for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
>   				irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
> @@ -4853,7 +4853,9 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>   					return r;
>   			}
>   		}
> +	}
>   
> +	if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
>   		for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
>   			for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
>   				irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> @@ -4870,6 +4872,7 @@ static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
>   			}
>   		}
>   	}
> +
>   	return 0;
>   }
>