[PATCH 0/2] drm: Support HDMI 2.2 FRL rates from the sink

[PATCH 0/2] drm: Support HDMI 2.2 FRL rates from the sink

[Fangzhi Zuo]

The HDMI 2.2 spec defines three new FRL rates - 16, 20 and 24 Gbps per
lane over 4 lanes (Max_FRL_Rate values 7, 8 and 9 in the HF-SCDB). The
current code stops at the HDMI 2.1 ceiling of 12 Gbps per lane, so a
sink that advertises an HDMI 2.2 rate is treated as having no FRL
support at all and the link ends up trained far below what the sink
actually supports.

Patch 1 teaches the DRM EDID parser to decode the three new rates.
Patch 2 maps them back to the FRL rate index used by DC in amdgpu_dm
and extends the KUnit coverage.

Fangzhi Zuo (2):
  drm/edid: Parse HDMI 2.2 FRL rates from the SCDS
  drm/amd/display: Accept HDMI 2.2 FRL rates from the sink EDID

 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  6 ++++
 .../amdgpu_dm/tests/amdgpu_dm_helpers_test.c  | 30 +++++++++++++++++++
 drivers/gpu/drm/drm_edid.c                    | 12 ++++++++
 3 files changed, 48 insertions(+)

-- 
2.53.0

[PATCH 1/2] drm/edid: Parse HDMI 2.2 FRL rates from the SCDS

[Fangzhi Zuo]

[Why]
drm_get_max_frl_rate() only decodes Max_FRL_Rate values 1-6, so a sink
advertising an HDMI 2.2 rate (7, 8 or 9) falls into the default case and
is reported as having no FRL support at all.

[How]
Decode the HDMI 2.2 Max_FRL_Rate values 7, 8 and 9 as 16, 20 and 24 Gbps
per lane over 4 lanes.

Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
---
 drivers/gpu/drm/drm_edid.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 42f4e41c459f..48d5c4bd4812 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6193,6 +6193,18 @@ void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane
 		*max_lanes = 4;
 		*max_rate_per_lane = 12;
 		break;
+	case 7:
+		*max_lanes = 4;
+		*max_rate_per_lane = 16;
+		break;
+	case 8:
+		*max_lanes = 4;
+		*max_rate_per_lane = 20;
+		break;
+	case 9:
+		*max_lanes = 4;
+		*max_rate_per_lane = 24;
+		break;
 	case 0:
 	default:
 		*max_lanes = 0;
-- 
2.53.0

[PATCH 2/2] drm/amd/display: Accept HDMI 2.2 FRL rates from the sink EDID

[Fangzhi Zuo]

[Why]
get_max_frl_rate() converts the DRM lane count / per-lane rate pair back
into the FRL rate index used by DC, but it only knows the rates up to
12 Gbps. A sink advertising 16, 20 or 24 Gbps per lane therefore falls
into the else branch and reports edid_caps.max_frl_rate = 0.

[How]
Map the remaining 4-lane rates to the matching hdmi_frl_link_rate values
(16 Gbps -> 7, 20 Gbps -> 8, 24 Gbps -> 9) and extend the KUnit coverage
alongside the existing per-rate cases.

Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  6 ++++
 .../amdgpu_dm/tests/amdgpu_dm_helpers_test.c  | 30 +++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index f0fc6d080c20..3067ac5bb0cd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -1190,6 +1190,12 @@ STATIC_IFN_KUNIT uint8_t get_max_frl_rate(uint8_t max_lanes, uint8_t max_rate_pe
 		max_frl_rate = 5;
 	else if ((max_lanes == 4) && (max_rate_per_lane == 12))
 		max_frl_rate = 6;
+	else if ((max_lanes == 4) && (max_rate_per_lane == 16))
+		max_frl_rate = 7;
+	else if ((max_lanes == 4) && (max_rate_per_lane == 20))
+		max_frl_rate = 8;
+	else if ((max_lanes == 4) && (max_rate_per_lane == 24))
+		max_frl_rate = 9;
 	else
 		max_frl_rate = 0;
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
index 38f53c596f0d..6e564f60b0df 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
@@ -1267,6 +1267,33 @@ static void dm_test_get_max_frl_rate_4lanes_12gbps(struct kunit *test)
 	KUNIT_EXPECT_EQ(test, get_max_frl_rate(4, 12), 6);
 }
 
+/**
+ * dm_test_get_max_frl_rate_4lanes_16gbps - Test Get max frl rate 4lanes 16gbps
+ * @test: The KUnit test context
+ */
+static void dm_test_get_max_frl_rate_4lanes_16gbps(struct kunit *test)
+{
+	KUNIT_EXPECT_EQ(test, get_max_frl_rate(4, 16), 7);
+}
+
+/**
+ * dm_test_get_max_frl_rate_4lanes_20gbps - Test Get max frl rate 4lanes 20gbps
+ * @test: The KUnit test context
+ */
+static void dm_test_get_max_frl_rate_4lanes_20gbps(struct kunit *test)
+{
+	KUNIT_EXPECT_EQ(test, get_max_frl_rate(4, 20), 8);
+}
+
+/**
+ * dm_test_get_max_frl_rate_4lanes_24gbps - Test Get max frl rate 4lanes 24gbps
+ * @test: The KUnit test context
+ */
+static void dm_test_get_max_frl_rate_4lanes_24gbps(struct kunit *test)
+{
+	KUNIT_EXPECT_EQ(test, get_max_frl_rate(4, 24), 9);
+}
+
 /**
  * dm_test_get_max_frl_rate_unknown - Test Get max frl rate unknown
  * @test: The KUnit test context
@@ -4893,6 +4920,9 @@ static struct kunit_case amdgpu_dm_helpers_test_cases[] = {
 	KUNIT_CASE(dm_test_get_max_frl_rate_4lanes_8gbps),
 	KUNIT_CASE(dm_test_get_max_frl_rate_4lanes_10gbps),
 	KUNIT_CASE(dm_test_get_max_frl_rate_4lanes_12gbps),
+	KUNIT_CASE(dm_test_get_max_frl_rate_4lanes_16gbps),
+	KUNIT_CASE(dm_test_get_max_frl_rate_4lanes_20gbps),
+	KUNIT_CASE(dm_test_get_max_frl_rate_4lanes_24gbps),
 	KUNIT_CASE(dm_test_get_max_frl_rate_unknown),
 	/* dm_dtn_log_begin / dm_dtn_log_append_v / dm_dtn_log_end */
 	KUNIT_CASE(dm_test_dtn_log_buffer_accumulates),
-- 
2.53.0

Re: [PATCH 1/2] drm/edid: Parse HDMI 2.2 FRL rates from the SCDS

[Jani Nikula]

On Wed, 28 Oct 2026, Fangzhi Zuo <jerry.zuo@amd.com> wrote:
> [Why]
> drm_get_max_frl_rate() only decodes Max_FRL_Rate values 1-6, so a sink
> advertising an HDMI 2.2 rate (7, 8 or 9) falls into the default case and
> is reported as having no FRL support at all.
>
> [How]
> Decode the HDMI 2.2 Max_FRL_Rate values 7, 8 and 9 as 16, 20 and 24 Gbps
> per lane over 4 lanes.
>
> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/drm_edid.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 42f4e41c459f..48d5c4bd4812 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6193,6 +6193,18 @@ void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane
>  		*max_lanes = 4;
>  		*max_rate_per_lane = 12;
>  		break;
> +	case 7:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 16;
> +		break;
> +	case 8:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 20;
> +		break;
> +	case 9:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 24;
> +		break;
>  	case 0:
>  	default:
>  		*max_lanes = 0;

-- 
Jani Nikula, Intel

Re: [PATCH 0/2] drm: Support HDMI 2.2 FRL rates from the sink

[Harry Wentland]

On 2026-10-28 20:44, Fangzhi Zuo wrote:
> The HDMI 2.2 spec defines three new FRL rates - 16, 20 and 24 Gbps per
> lane over 4 lanes (Max_FRL_Rate values 7, 8 and 9 in the HF-SCDB). The
> current code stops at the HDMI 2.1 ceiling of 12 Gbps per lane, so a
> sink that advertises an HDMI 2.2 rate is treated as having no FRL
> support at all and the link ends up trained far below what the sink
> actually supports.
> 
> Patch 1 teaches the DRM EDID parser to decode the three new rates.
> Patch 2 maps them back to the FRL rate index used by DC in amdgpu_dm
> and extends the KUnit coverage.
> 

Series is
Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> Fangzhi Zuo (2):
>   drm/edid: Parse HDMI 2.2 FRL rates from the SCDS
>   drm/amd/display: Accept HDMI 2.2 FRL rates from the sink EDID
> 
>  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  6 ++++
>  .../amdgpu_dm/tests/amdgpu_dm_helpers_test.c  | 30 +++++++++++++++++++
>  drivers/gpu/drm/drm_edid.c                    | 12 ++++++++
>  3 files changed, 48 insertions(+)
>