From: Dinh Nguyen <dinguyen@kernel.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast
Date: Thu, 8 Mar 2018 15:44:27 -0600 [thread overview]
Message-ID: <367297fb-1224-5b7d-44bd-e3540704c666@kernel.org> (raw)
In-Reply-To: <1520517675.2582.11.camel@intel.com>
On 03/08/2018 08:01 AM, See, Chin Liang wrote:
> On Thu, 2018-03-01 at 17:17 +0100, Marek Vasut wrote:
>> On 02/28/2018 06:12 AM, chin.liang.see at intel.com wrote:
>>>
>>> From: Chin Liang See <chin.liang.see@intel.com>
>>>
>>> Enabling cache and TLB maintenance broadcast through ACTLR as
>>> required
>>> by Linux.
>> This needs far more clarification. What is the problem you're fixing
>> here ? How does it fix the problem ?
>
> Sure. When the 2 processors is enabled with SMP, popen operation would
> fail as content are different after the copy. This issue goes away when
> we force Linux to run with 1 core only. Checked with ARM, this bit is
> required by Linux when running SMP.
>
What's a "popen" operation? Shouldn't you also set the SMP along with
the FW bit?
Dinh
prev parent reply other threads:[~2018-03-08 21:44 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-28 5:12 [U-Boot] [PATCH] arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast chin.liang.see at intel.com
2018-03-01 16:17 ` Marek Vasut
2018-03-08 14:01 ` See, Chin Liang
2018-03-08 21:44 ` Dinh Nguyen [this message]
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