From: Khem Raj <raj.khem@gmail.com>
To: mark.hatle@kernel.crashing.org, openembedded-core@lists.openembedded.org
Subject: Re: [OE-core] [PATCH v3 6/6] qemuriscv: Dynamically configure qemu CPU
Date: Wed, 9 Jul 2025 09:23:51 -0700 [thread overview]
Message-ID: <368a2856-e12a-45dc-940b-cfa269a4bc13@gmail.com> (raw)
In-Reply-To: <a23f5658-d4a8-4ad1-8eb5-924a36d04bad@kernel.crashing.org>
On 7/9/25 7:54 AM, Mark Hatle via lists.openembedded.org wrote:
> I will investigate.
>
> I suspect SOME of this may be test cases with hard coded riscv assembly
> in them using extensions that we've not enabled.
>
> The configuration listed in the logs for the kernel are:
>
> rv64imafdc
>
> '[ 0.000000] riscv: base ISA extensions acdfim\n'
> '[ 0.000000] riscv: ELF capabilities acdfim\n'
>
> The 'v' (vector) extension is intentionally not enabled to match the
> software configuration, but some tests may be trying to use it.
>
> I'll walk through this and attempt to get this identified for real.
We should be enabling the rvb23 (rv64gcv) profile as default for qemu, since
that is the baseline for a RISCV profile that OE will be used as base
infrastructure and we should target that commonly, perhaps changing
default tune for qemuriscv64 to consider that would be a good thing. I
know there is
a value in constructing the ISA+extension set that qemu emulates based
on tune selection and whatever rv64gcv devolves down in terms of
extensions.
>
> --Mark
>
> On 7/9/25 4:17 AM, Richard Purdie via lists.openembedded.org wrote:
>> On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via
>> lists.openembedded.org wrote:
>>> From: Mark Hatle <mark.hatle@amd.com>
>>>
>>> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
>>> options selected by the DEFAULTTUNE.
>>>
>>> Note: OpenSBI currently requires 'c' (compressed instructions) or it
>>> will
>>> not work.
>>>
>>> Change the base device configuration to use a different variable to
>>> select
>>> the emulate devices. This will allow a user to override or append the
>>> QB_OPT_APPEND without the riscv32 override getting in the way.
>>>
>>> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
>>> ---
>>> meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
>>> 1 file changed, 28 insertions(+), 3 deletions(-)
>>>
>>
>> FWIW I narrowed down the ptest failures to this patch.
>>
>> Cheers,
>>
>> Richard
>>
>>
>>
>>
>>
>
>
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next prev parent reply other threads:[~2025-07-09 16:23 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-02 21:44 [PATCH v3 0/6] ISA based RISC-V tune implementation Mark Hatle
2025-07-02 21:44 ` [PATCH v3 1/6] u-boot: Dynamic RISC-V ISA configuration Mark Hatle
2025-07-02 21:44 ` [PATCH v3 2/6] features_check.bbclass: Add support for required TUNE_FEATURES Mark Hatle
2025-07-02 21:44 ` [PATCH v3 3/6] kernel.bbclass: State riscv required tune_features for Linux Mark Hatle
2025-07-02 21:44 ` [PATCH v3 4/6] linux-yocto/6.12: riscv: Enable dynamic ISA selection Mark Hatle
2025-07-02 21:44 ` [PATCH v3 5/6] linux-yocto/6.12: riscv: Enable TUNE_FEATURES based KERNEL_FEATURES Mark Hatle
2025-07-02 21:44 ` [PATCH v3 6/6] qemuriscv: Dynamically configure qemu CPU Mark Hatle
2025-07-09 9:17 ` [OE-core] " Richard Purdie
2025-07-09 14:54 ` Mark Hatle
2025-07-09 16:23 ` Khem Raj [this message]
2025-07-09 21:23 ` Mark Hatle
2025-07-09 7:42 ` [OE-core] [PATCH v3 0/6] ISA based RISC-V tune implementation Richard Purdie
2025-07-09 16:26 ` Khem Raj
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