From: Heiko Stuebner <heiko@sntech.de>
To: Xing Zheng <zhengxing@rock-chips.com>
Cc: dianders@google.com, zhangqing@rock-chips.com,
huangtao@rock-chips.com, briannorris@google.com,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: rockchip: optimize the configuration for 800MHz and 1GHz on RK3399
Date: Wed, 02 Nov 2016 00:25:37 +0100 [thread overview]
Message-ID: <37901081.P92AxpVH96@phil> (raw)
In-Reply-To: <1477970526-26388-1-git-send-email-zhengxing@rock-chips.com>
Am Dienstag, 1. November 2016, 11:22:06 CET schrieb Xing Zheng:
> Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399.
> But dues to the carelessly copying from RK3036 when the RK3399 bringing up,
> the refdiv == 6, it will increase the lock time, and it is not an optimal
> configuration.
>
> Please let's fix them for the lock time and jitter are lower:
> 800 MHz:
> - FVCO == 2.4 GHz, revdiv == 1.
> 1 GHz:
> - FVCO == 3 GHz, revdiv == 1.
>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
applied to my clk-branch for 4.10
Thanks
Heiko
WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stuebner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] clk: rockchip: optimize the configuration for 800MHz and 1GHz on RK3399
Date: Wed, 02 Nov 2016 00:25:37 +0100 [thread overview]
Message-ID: <37901081.P92AxpVH96@phil> (raw)
In-Reply-To: <1477970526-26388-1-git-send-email-zhengxing@rock-chips.com>
Am Dienstag, 1. November 2016, 11:22:06 CET schrieb Xing Zheng:
> Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399.
> But dues to the carelessly copying from RK3036 when the RK3399 bringing up,
> the refdiv == 6, it will increase the lock time, and it is not an optimal
> configuration.
>
> Please let's fix them for the lock time and jitter are lower:
> 800 MHz:
> - FVCO == 2.4 GHz, revdiv == 1.
> 1 GHz:
> - FVCO == 3 GHz, revdiv == 1.
>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
applied to my clk-branch for 4.10
Thanks
Heiko
next prev parent reply other threads:[~2016-11-01 23:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-01 3:22 [PATCH] clk: rockchip: optimize the configuration for 800MHz and 1GHz on RK3399 Xing Zheng
2016-11-01 3:22 ` Xing Zheng
2016-11-01 3:22 ` Xing Zheng
2016-11-01 23:25 ` Heiko Stuebner [this message]
2016-11-01 23:25 ` Heiko Stuebner
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