From: Juergen Gross <jgross@suse.com>
To: Jan Beulich <JBeulich@suse.com>,
Andrew Cooper <andrew.cooper3@citrix.com>
Cc: George Dunlap <George.Dunlap@eu.citrix.com>,
xen-devel <xen-devel@lists.xenproject.org>,
Kevin Tian <kevin.tian@intel.com>,
Jun Nakajima <jun.nakajima@intel.com>
Subject: Re: [PATCH 5/6] x86/HVM: prefill cache with PDPTEs when possible
Date: Tue, 24 Jul 2018 09:27:15 +0200 [thread overview]
Message-ID: <3849db3f-efe0-d0dd-e428-8f28d5a0e323@suse.com> (raw)
In-Reply-To: <5B56CF6402000078001D6F89@prv1-mh.provo.novell.com>
On 24/07/18 09:04, Jan Beulich wrote:
>>>> On 19.07.18 at 21:07, <andrew.cooper3@citrix.com> wrote:
>> Oh - I'd not looked in that much detail at your algorithm. As a first
>> gut feel, tagging by level doesn't sound as if it will interact
>> correctly with linear pagetables.
>>
>> Both the Intel and AMD ORM's maintain paging structure caches so I'd
>> expect that a linear pagetable entry would be served from that cache
>> rather than being read twice from RAM.
>
> Is there anywhere enough detail about the actual implementation of
> the paging structure caches? I could imagine them being per level. It
> wouldn't be very difficult to switch to a tristate here (normal data,
> page table, and PAE L3).
>
From https://www.cs.rice.edu/CS/Architecture/docs/barr-isca10.pdf :
Therefore, both AMD and Intel have implemented MMU
caches for page table entries from the higher levels of the tree [3,
9]. However, their caches have quite different structure. For exam-
ple, AMD’s Page Walk Cache stores page table entries from any
level of the tree, whereas Intel implements distinct caches for each
level of the tree. Also, AMD’s Page Walk Cache is indexed by
the physical address of the cached page table entry, whereas Intel’s
Paging-Structure Caches are indexed by portions of the virtual ad-
dress being translated
Juergen
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next prev parent reply other threads:[~2018-07-24 7:27 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-19 10:39 [PATCH 0/6] x86/HVM: implement memory read caching Jan Beulich
2018-07-19 10:46 ` [PATCH 1/6] x86/mm: add optional cache to GLA->GFN translation Jan Beulich
2018-07-19 13:12 ` Paul Durrant
2018-07-19 10:47 ` [PATCH 2/6] x86/mm: use optional cache in guest_walk_tables() Jan Beulich
2018-07-19 13:22 ` Paul Durrant
2018-09-03 15:12 ` Jan Beulich
2018-07-19 10:48 ` [PATCH 3/6] x86/HVM: implement memory read caching Jan Beulich
2018-07-19 14:20 ` Paul Durrant
2018-07-24 10:28 ` Jan Beulich
2018-07-23 15:45 ` Tim Deegan
2018-07-19 10:49 ` [PATCH 4/6] VMX: correct PDPTE load checks Jan Beulich
2018-08-28 11:59 ` Ping: " Jan Beulich
2018-08-28 13:12 ` Andrew Cooper
2018-08-30 1:24 ` Tian, Kevin
2018-08-30 13:58 ` Jan Beulich
2018-07-19 10:50 ` [PATCH 5/6] x86/HVM: prefill cache with PDPTEs when possible Jan Beulich
2018-07-19 11:15 ` Andrew Cooper
2018-07-19 11:47 ` Jan Beulich
2018-07-19 11:55 ` Andrew Cooper
2018-07-19 18:37 ` Jan Beulich
2018-07-19 18:47 ` Andrew Cooper
2018-07-19 19:00 ` Jan Beulich
2018-07-19 19:07 ` Andrew Cooper
2018-07-24 7:04 ` Jan Beulich
2018-07-24 7:27 ` Juergen Gross [this message]
2018-07-24 7:44 ` Jan Beulich
2018-07-19 10:51 ` [PATCH 6/6] x86/shadow: a little bit of style cleanup Jan Beulich
2018-07-23 15:05 ` Tim Deegan
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