From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: George Dunlap <George.Dunlap@eu.citrix.com>,
xen-devel <xen-devel@lists.xenproject.org>,
Kevin Tian <kevin.tian@intel.com>,
Jun Nakajima <jun.nakajima@intel.com>
Subject: Re: [PATCH 5/6] x86/HVM: prefill cache with PDPTEs when possible
Date: Thu, 19 Jul 2018 12:55:45 +0100 [thread overview]
Message-ID: <65e2cc63-e956-86ca-2c46-55dd0157ae9e@citrix.com> (raw)
In-Reply-To: <5B507A6102000078001D5DDD@prv1-mh.provo.novell.com>
On 19/07/18 12:47, Jan Beulich wrote:
>>>> On 19.07.18 at 13:15, <andrew.cooper3@citrix.com> wrote:
>> On 19/07/18 11:50, Jan Beulich wrote:
>>> Since strictly speaking it is incorrect for guest_walk_tables() to read
>>> L3 entries during PAE page walks, try to overcome this where possible by
>>> pre-loading the values from hardware into the cache. Sadly the
>>> information is available in the EPT case only. On the positive side for
>>> NPT the spec spells out that L3 entries are actually read on walks, so
>>> us reading them is consistent with hardware behavior in that case.
>>>
>>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>> I'm afraid that this isn't architecturally correct. It means that an
>> emulated memory access will read the PDPTE register values, rather than
>> what is actually in RAM.
> I'm afraid I don't understand: A CR3 load loads the PDPTEs into
> registers, and walks use those registers, not memory. That's the very
> difference between PAE and all other walks.
Patch 3 causes memory reads to come from the cache.
This patch feeds the PDPTE registers into the cache, which breaks the
architectural correctness of patch 3, because the PDPTE registers may
legitimately be stale WRT the content in memory.
The pagewalk reading of top_map doesn't require that top_map points into
guest space. If you read the PDPTE registers onto the stack, and pass a
pointer to the stack into the pagewalk in the 3-level case, then you fix
the issue described here without breaking patch 3.
~Andrew
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next prev parent reply other threads:[~2018-07-19 11:55 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-19 10:39 [PATCH 0/6] x86/HVM: implement memory read caching Jan Beulich
2018-07-19 10:46 ` [PATCH 1/6] x86/mm: add optional cache to GLA->GFN translation Jan Beulich
2018-07-19 13:12 ` Paul Durrant
2018-07-19 10:47 ` [PATCH 2/6] x86/mm: use optional cache in guest_walk_tables() Jan Beulich
2018-07-19 13:22 ` Paul Durrant
2018-09-03 15:12 ` Jan Beulich
2018-07-19 10:48 ` [PATCH 3/6] x86/HVM: implement memory read caching Jan Beulich
2018-07-19 14:20 ` Paul Durrant
2018-07-24 10:28 ` Jan Beulich
2018-07-23 15:45 ` Tim Deegan
2018-07-19 10:49 ` [PATCH 4/6] VMX: correct PDPTE load checks Jan Beulich
2018-08-28 11:59 ` Ping: " Jan Beulich
2018-08-28 13:12 ` Andrew Cooper
2018-08-30 1:24 ` Tian, Kevin
2018-08-30 13:58 ` Jan Beulich
2018-07-19 10:50 ` [PATCH 5/6] x86/HVM: prefill cache with PDPTEs when possible Jan Beulich
2018-07-19 11:15 ` Andrew Cooper
2018-07-19 11:47 ` Jan Beulich
2018-07-19 11:55 ` Andrew Cooper [this message]
2018-07-19 18:37 ` Jan Beulich
2018-07-19 18:47 ` Andrew Cooper
2018-07-19 19:00 ` Jan Beulich
2018-07-19 19:07 ` Andrew Cooper
2018-07-24 7:04 ` Jan Beulich
2018-07-24 7:27 ` Juergen Gross
2018-07-24 7:44 ` Jan Beulich
2018-07-19 10:51 ` [PATCH 6/6] x86/shadow: a little bit of style cleanup Jan Beulich
2018-07-23 15:05 ` Tim Deegan
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