All of lore.kernel.org
 help / color / mirror / Atom feed
From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] irqchip: irq-mvebu-odmi: new driver for platform MSI on Marvell 7K/8K
Date: Thu, 18 Feb 2016 17:08:05 +0100	[thread overview]
Message-ID: <3923904.c50oLNXXZ1@wuerfel> (raw)
In-Reply-To: <1455811134-3679-1-git-send-email-thomas.petazzoni@free-electrons.com>

On Thursday 18 February 2016 16:58:54 Thomas Petazzoni wrote:
> +- marvell,spi-base     : List of GIC base SPI interrupts, one for each
> +                         ODMI frame. Those SPI interrupts are 0-based,
> +                         i.e marvell,spi-base = <128> will use SPI #96.
> +                         See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
> +                         for details about the GIC Device Tree binding.
> 

Why are these not just in an 'interrupts' property as we do for other
nested irqchips?

	Arnd

WARNING: multiple messages have this Message-ID (diff)
From: Arnd Bergmann <arnd@arndb.de>
To: linux-arm-kernel@lists.infradead.org
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <marc.zyngier@arm.com>,
	linux-kernel@vger.kernel.org, Lior Amsalem <alior@marvell.com>,
	Andrew Lunn <andrew@lunn.ch>, Nadav Haklai <nadavh@marvell.com>,
	Gregory Clement <gregory.clement@free-electrons.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v2] irqchip: irq-mvebu-odmi: new driver for platform MSI on Marvell 7K/8K
Date: Thu, 18 Feb 2016 17:08:05 +0100	[thread overview]
Message-ID: <3923904.c50oLNXXZ1@wuerfel> (raw)
In-Reply-To: <1455811134-3679-1-git-send-email-thomas.petazzoni@free-electrons.com>

On Thursday 18 February 2016 16:58:54 Thomas Petazzoni wrote:
> +- marvell,spi-base     : List of GIC base SPI interrupts, one for each
> +                         ODMI frame. Those SPI interrupts are 0-based,
> +                         i.e marvell,spi-base = <128> will use SPI #96.
> +                         See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
> +                         for details about the GIC Device Tree binding.
> 

Why are these not just in an 'interrupts' property as we do for other
nested irqchips?

	Arnd

  reply	other threads:[~2016-02-18 16:08 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-18 15:58 [PATCH v2] irqchip: irq-mvebu-odmi: new driver for platform MSI on Marvell 7K/8K Thomas Petazzoni
2016-02-18 15:58 ` Thomas Petazzoni
2016-02-18 16:08 ` Arnd Bergmann [this message]
2016-02-18 16:08   ` Arnd Bergmann
2016-02-18 16:16   ` Thomas Petazzoni
2016-02-18 16:16     ` Thomas Petazzoni
2016-02-18 16:27     ` Arnd Bergmann
2016-02-18 16:27       ` Arnd Bergmann
2016-02-18 16:41 ` Marc Zyngier
2016-02-18 16:41   ` Marc Zyngier
2016-02-19  9:35   ` Thomas Petazzoni
2016-02-19  9:35     ` Thomas Petazzoni

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=3923904.c50oLNXXZ1@wuerfel \
    --to=arnd@arndb.de \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.