[Qemu-devel] [PATCH] RDSTC TSD Flag Support

[Qemu-devel] [PATCH] RDSTC TSD Flag Support

[Matthew Schulkind]

[-- Attachment #1: Type: text/plain, Size: 332 bytes --]

I'm not on the list, so any replies should be CC'ed to me personally.

I have attached a very small patch to implement TSD flag checking when
the RDTSC instruction is executed on the x86 guest architecture. A GPF
is supposed to be raised if the CPL is not 0 and the TSD flag in the
CR4 register is enabled.

-Matt Schulkind

[-- Attachment #2: rdtsc.patch --]
[-- Type: application/octet-stream, Size: 1001 bytes --]

diff -U4 -r --exclude=CVS qemu-orig/target-i386/helper.c qemu/target-i386/helper.c
--- qemu-orig/target-i386/helper.c	2005-07-24 10:33:17.000000000 -0400
+++ qemu/target-i386/helper.c	2005-08-14 21:40:57.000000000 -0400
@@ -2328,8 +2328,12 @@
 
 void helper_rdtsc(void)
 {
     uint64_t val;
+
+    if( (env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0) ) {
+        raise_exception( EXCP0D_GPF );
+    }
     
     val = cpu_get_tsc(env);
     EAX = (uint32_t)(val);
     EDX = (uint32_t)(val >> 32);
diff -U4 -r --exclude=CVS qemu-orig/target-i386/translate.c qemu/target-i386/translate.c
--- qemu-orig/target-i386/translate.c	2005-07-23 13:41:26.000000000 -0400
+++ qemu/target-i386/translate.c	2005-08-14 21:32:37.000000000 -0400
@@ -5365,8 +5365,9 @@
                 gen_op_wrmsr();
         }
         break;
     case 0x131: /* rdtsc */
+        gen_jmp_im(pc_start - s->cs_base);
         gen_op_rdtsc();
         break;
     case 0x134: /* sysenter */
         if (CODE64(s))