From: Dan Malek <dan@mvista.com>
To: "Dan A. Dickey" <ddickey@charter.net>
Cc: "linuxppc-embedded@lists.linuxppc.org"
<linuxppc-embedded@lists.linuxppc.org>
Subject: Re: ethernet on fads850sar board?
Date: Mon, 02 Oct 2000 01:02:16 -0400 [thread overview]
Message-ID: <39D816D8.35ED965E@mvista.com> (raw)
In-Reply-To: 39D7F8FB.9C508CF1@charter.net
"Dan A. Dickey" wrote:
> Any ideas?
Make sure the GP I/O pins are configured properly to be SCC2 Ethernet
control/status lines. Make sure the BCSR bits enable and properly
configure the PHY (half/full duplex, loopback, etc.).
> (And why do the baud rate generators that feed the ethernet
> clocks need to run at 2Mhz?)
Ummm, no.....The PHY provides the clocks, they are inputs to port.
I don't know why an external clock would be set to that value.
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2000-10-02 5:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-10-02 2:54 ethernet on fads850sar board? Dan A. Dickey
2000-10-02 5:02 ` Dan Malek [this message]
2000-10-02 11:22 ` Dan A. Dickey
2000-10-04 15:50 ` Dan A. Dickey
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