SMP P4 APIC/interrupt balancing

SMP P4 APIC/interrupt balancing

[James Bourne]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 1566 bytes --]

Hi All,
Ok, we have a Dell PE4600 with dual P4X processors.  It will not balance
interrupts between the two cpus, CPU0 always receives the bulk
of the interrupts, although both processors are being utilized
by processes on the system.  This system is not yet in production, so I
have some time to try things on it.

Current kernel is 2.4.18 with the LSE APIC Routing patch
(http://sourceforge.net/projects/lse).  2.4.18 stock (well ok, -rc4) has
much the same results.

I have tried Ingos' patch from early Feb and it managed to hang the system
on CPU0 initialization... 

This is a newer system and uses the ServerWorks GCHE South Bridge I
believe, dmesg actually comes up with a few unknown devices.

I'm attaching dmesg output, .config, lspci -v output, and output
from /proc/cpuinfo and /proc/interrupts.

If anything else is needed, just let me know.  

Thanks and Regards,
James Bourne

-- 
James Bourne, Supervisor Data Centre Operations
Mount Royal College, Calgary, AB, CA
www.mtroyal.ab.ca

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[-- Attachment #2: lspci output --]
[-- Type: TEXT/PLAIN, Size: 6513 bytes --]

00:00.0 Host bridge: ServerWorks CMIC-HE (rev 22)
	Flags: fast devsel

00:00.1 Host bridge: ServerWorks CMIC-HE
	Flags: fast devsel

00:00.2 Host bridge: ServerWorks CMIC-HE
	Flags: fast devsel

00:00.3 Host bridge: ServerWorks CMIC-HE
	Flags: fast devsel

00:04.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 08)
	Subsystem: Dell Computer Corporation: Unknown device 0106
	Flags: bus master, medium devsel, latency 32, IRQ 19
	Memory at fe203000 (32-bit, non-prefetchable) [size=4K]
	I/O ports at ecc0 [size=64]
	Memory at fe000000 (32-bit, non-prefetchable) [size=1M]
	Capabilities: [dc] Power Management version 2

00:06.0 SCSI storage controller: Adaptec AHA-2940U2/U2W / 7890/7891 (rev 01)
	Subsystem: Dell Computer Corporation: Unknown device 0106
	Flags: bus master, medium devsel, latency 32, IRQ 18
	BIST result: 00
	I/O ports at e800 [disabled] [size=256]
	Memory at fe202000 (64-bit, non-prefetchable) [size=4K]
	Expansion ROM at fe100000 [disabled] [size=128K]
	Capabilities: [dc] Power Management version 1

00:0e.0 VGA compatible controller: ATI Technologies Inc Rage XL (rev 27) (prog-if 00 [VGA])
	Subsystem: Dell Computer Corporation: Unknown device 0106
	Flags: bus master, VGA palette snoop, stepping, medium devsel, latency 32
	Memory at fd000000 (32-bit, non-prefetchable) [size=16M]
	I/O ports at e400 [size=256]
	Memory at fe201000 (32-bit, non-prefetchable) [size=4K]
	Expansion ROM at <unassigned> [disabled] [size=128K]
	Capabilities: [5c] Power Management version 2

00:0f.0 Host bridge: ServerWorks CSB5 South Bridge (rev 93)
	Subsystem: ServerWorks CSB5 South Bridge
	Flags: bus master, medium devsel, latency 32

00:0f.1 IDE interface: ServerWorks CSB5 IDE Controller (rev 93) (prog-if 82 [Master PriP])
	Subsystem: ServerWorks CSB5 IDE Controller
	Flags: bus master, medium devsel, latency 0
	I/O ports at 08c0 [size=8]
	I/O ports at 08c8 [size=4]
	I/O ports at 08d0 [size=8]
	I/O ports at 08d8 [size=4]
	I/O ports at 08b0 [size=16]

00:0f.3 ISA bridge: ServerWorks: Unknown device 0225
	Subsystem: ServerWorks: Unknown device 0230
	Flags: bus master, medium devsel, latency 0

00:10.0 Host bridge: ServerWorks CIOB30 (rev 03)
	Flags: 66Mhz, medium devsel
	Capabilities: [60] PCI-X non-bridge device.

00:10.2 Host bridge: ServerWorks CIOB30 (rev 03)
	Flags: 66Mhz, medium devsel
	Capabilities: [60] PCI-X non-bridge device.

00:11.0 Host bridge: ServerWorks CIOB30 (rev 03)
	Flags: 66Mhz, medium devsel
	Capabilities: [60] PCI-X non-bridge device.

00:11.2 Host bridge: ServerWorks CIOB30 (rev 03)
	Flags: 66Mhz, medium devsel
	Capabilities: [60] PCI-X non-bridge device.

01:06.0 Ethernet controller: BROADCOM Corporation NetXtreme BCM5700 Gigabit Ethernet (rev 14)
	Subsystem: Dell Computer Corporation NetXtreme 1000BaseTX
	Flags: bus master, 66Mhz, medium devsel, latency 32, IRQ 22
	Memory at fcf00000 (64-bit, non-prefetchable) [size=64K]
	Capabilities: [40] PCI-X non-bridge device.
	Capabilities: [48] Power Management version 2
	Capabilities: [50] Vital Product Data
	Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable-

01:08.0 PCI bridge: Intel Corp.: Unknown device 0309 (rev 01) (prog-if 00 [Normal decode])
	Flags: bus master, 66Mhz, slow devsel, latency 32
	Bus: primary=01, secondary=02, subordinate=02, sec-latency=32
	I/O behind bridge: 0000d000-0000dfff
	Memory behind bridge: fcd00000-fcefffff
	Capabilities: [68] Power Management version 2

02:06.0 SCSI storage controller: Adaptec AIC-7899P U160/m (rev 01)
	Subsystem: Dell Computer Corporation: Unknown device 0106
	Flags: bus master, 66Mhz, medium devsel, latency 32, IRQ 20
	BIST result: 00
	I/O ports at dc00 [disabled] [size=256]
	Memory at fcdff000 (64-bit, non-prefetchable) [size=4K]
	Expansion ROM at fce00000 [disabled] [size=128K]
	Capabilities: [dc] Power Management version 2

02:06.1 SCSI storage controller: Adaptec AIC-7899P U160/m (rev 01)
	Subsystem: Dell Computer Corporation: Unknown device 0106
	Flags: bus master, 66Mhz, medium devsel, latency 32, IRQ 21
	BIST result: 00
	I/O ports at d800 [disabled] [size=256]
	Memory at fcdfe000 (64-bit, non-prefetchable) [size=4K]
	Expansion ROM at fce00000 [disabled] [size=128K]
	Capabilities: [dc] Power Management version 2

03:06.0 PCI bridge: Intel Corp.: Unknown device b154 (prog-if 00 [Normal decode])
	Flags: bus master, 66Mhz, medium devsel, latency 32
	Bus: primary=03, secondary=04, subordinate=05, sec-latency=32
	I/O behind bridge: 0000b000-0000bfff
	Memory behind bridge: fad00000-faffffff
	Prefetchable memory behind bridge: 00000000f0000000-00000000f7f00000
	Capabilities: [dc] Power Management version 1

04:00.0 PCI bridge: Intel Corp.: Unknown device b154 (prog-if 00 [Normal decode])
	Flags: bus master, medium devsel, latency 32
	Bus: primary=04, secondary=05, subordinate=05, sec-latency=32
	Memory behind bridge: faf00000-faffffff
	Prefetchable memory behind bridge: 00000000f0000000-00000000f7f00000
	Capabilities: [dc] Power Management version 1

04:01.0 SCSI storage controller: QLogic Corp. ISP12160 Dual Channel Ultra3 SCSI Processor (rev 06)
	Subsystem: American Megatrends Inc. QLA12160 on AMI MegaRAID
	Flags: bus master, 66Mhz, medium devsel, latency 32, IRQ 28
	I/O ports at bc00 [size=256]
	Memory at fadff000 (32-bit, non-prefetchable) [size=4K]
	Expansion ROM at fae00000 [disabled] [size=128K]
	Capabilities: [44] Power Management version 1

05:00.0 RAID bus controller: American Megatrends Inc. MegaRAID (rev 20)
	Subsystem: Dell Computer Corporation PowerEdge RAID Controller 3/DC
	Flags: bus master, medium devsel, latency 32, IRQ 27
	Memory at f0000000 (32-bit, prefetchable) [size=128M]
	Expansion ROM at faf00000 [disabled] [size=32K]
	Capabilities: [80] Power Management version 2

0a:06.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 0d)
	Subsystem: Intel Corp. EtherExpress PRO/100 S Server Adapter
	Flags: bus master, medium devsel, latency 32, IRQ 35
	Memory at eff41000 (32-bit, non-prefetchable) [size=4K]
	I/O ports at 8cc0 [size=64]
	Memory at eff20000 (32-bit, non-prefetchable) [size=128K]
	Capabilities: [dc] Power Management version 2

0a:08.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 0d)
	Subsystem: Intel Corp. EtherExpress PRO/100 S Server Adapter
	Flags: bus master, medium devsel, latency 32, IRQ 31
	Memory at eff40000 (32-bit, non-prefetchable) [size=4K]
	I/O ports at 8c80 [size=64]
	Memory at eff00000 (32-bit, non-prefetchable) [size=128K]
	Capabilities: [dc] Power Management version 2


[-- Attachment #3: dmesg output --]
[-- Type: TEXT/PLAIN, Size: 15279 bytes --]

BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 00000000000a0000 (usable)
 BIOS-e820: 0000000000100000 - 000000007fff0000 (usable)
 BIOS-e820: 000000007fff0000 - 000000007fffec00 (ACPI data)
 BIOS-e820: 000000007fffec00 - 000000007ffff000 (reserved)
 BIOS-e820: 00000000fec00000 - 00000000fec10000 (reserved)
 BIOS-e820: 00000000fee00000 - 00000000fee10000 (reserved)
 BIOS-e820: 00000000fff80000 - 0000000100000000 (reserved)
1151MB HIGHMEM available.
found SMP MP-table at 000fe710
hm, page 000fe000 reserved twice.
hm, page 000ff000 reserved twice.
hm, page 000f0000 reserved twice.
On node 0 totalpages: 524272
zone(0): 4096 pages.
zone(1): 225280 pages.
zone(2): 294896 pages.
Intel MultiProcessor Specification v1.4
    Virtual Wire compatibility mode.
OEM ID: DELL     Product ID: PE 0106      APIC at: 0xFEE00000
Processor #0 Unknown CPU [15:2] APIC version 20
Processor #2 Unknown CPU [15:2] APIC version 20
I/O APIC #4 Version 17 at 0xFEC00000.
I/O APIC #5 Version 17 at 0xFEC01000.
I/O APIC #6 Version 17 at 0xFEC02000.
Processors: 2
Kernel command line: BOOT_IMAGE=linuxp4 ro root=808 BOOT_FILE=/boot/vmlinuz-2.4.18-PE4600-P4 idle=poll
using polling idle threads.
Initializing CPU#0
Detected 1791.317 MHz processor.
Console: colour VGA+ 80x25
Calibrating delay loop... 3565.15 BogoMIPS
Memory: 2061820k/2097088k available (1085k kernel code, 34884k reserved, 296k data, 208k init, 1179584k highmem)
Dentry-cache hash table entries: 262144 (order: 9, 2097152 bytes)
Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
Mount-cache hash table entries: 32768 (order: 6, 262144 bytes)
Buffer-cache hash table entries: 131072 (order: 7, 524288 bytes)
Page-cache hash table entries: 524288 (order: 9, 2097152 bytes)
CPU: Before vendor init, caps: 3febfbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 12K, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Physical Processor ID: 0
CPU: After vendor init, caps: 3febfbff 00000000 00000000 00000000
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU:     After generic, caps: 3febfbff 00000000 00000000 00000000
CPU:             Common caps: 3febfbff 00000000 00000000 00000000
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
mtrr: v1.40 (20010327) Richard Gooch (rgooch@atnf.csiro.au)
mtrr: detected mtrr type: Intel
CPU: Before vendor init, caps: 3febfbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 12K, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Physical Processor ID: 0
CPU: After vendor init, caps: 3febfbff 00000000 00000000 00000000
Intel machine check reporting enabled on CPU#0.
CPU:     After generic, caps: 3febfbff 00000000 00000000 00000000
CPU:             Common caps: 3febfbff 00000000 00000000 00000000
CPU0: Intel(R) XEON(TM) CPU 1.80GHz stepping 04
per-CPU timeslice cutoff: 1462.83 usecs.
enabled ExtINT on CPU#0
ESR value before enabling vector: 00000040
ESR value after enabling vector: 00000000
Booting processor 1/2 eip 2000
Initializing CPU#1
masked ExtINT on CPU#1
ESR value before enabling vector: 00000000
ESR value after enabling vector: 00000000
Calibrating delay loop... 3578.26 BogoMIPS
CPU: Before vendor init, caps: 3febfbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 12K, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Physical Processor ID: 3
CPU: After vendor init, caps: 3febfbff 00000000 00000000 00000000
Intel machine check reporting enabled on CPU#1.
CPU:     After generic, caps: 3febfbff 00000000 00000000 00000000
CPU:             Common caps: 3febfbff 00000000 00000000 00000000
CPU1: Intel(R) XEON(TM) CPU 1.80GHz stepping 04
Total of 2 processors activated (7143.42 BogoMIPS).
WARNING: No sibling found for CPU 0.
WARNING: No sibling found for CPU 1.
ENABLING IO-APIC IRQs
Setting 4 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 4 ... ok.
Setting 5 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 5 ... ok.
Setting 6 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 6 ... ok.
init IO_APIC IRQs
 IO-APIC (apicid-pin) 4-0, 4-10, 4-11, 4-13, 6-15 not connected.
..TIMER: vector=0x31 pin1=2 pin2=0
..MP-BIOS bug: 8254 timer not connected to IO-APIC
...trying to set up timer (IRQ0) through the 8259A ... 
..... (found pin 0) ...works.
number of MP IRQ sources: 50.
number of IO-APIC #4 registers: 16.
number of IO-APIC #5 registers: 16.
number of IO-APIC #6 registers: 16.
testing the IO APIC.......................

IO APIC #4......
.... register #00: 04000000
.......    : physical APIC id: 04
.... register #01: 000F0011
.......     : max redirection entries: 000F
.......     : PRQ implemented: 0
.......     : IO APIC version: 0011
.... register #02: 04000000
.......     : arbitration: 04
.... IRQ redirection table:
 NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:   
 00 003 03  0    0    0   0   0    1    1    31
 01 003 03  0    0    0   0   0    1    1    39
 02 000 00  1    0    0   0   0    0    0    00
 03 003 03  0    0    0   0   0    1    1    41
 04 003 03  0    0    0   0   0    1    1    49
 05 003 03  0    0    0   0   0    1    1    51
 06 003 03  0    0    0   0   0    1    1    59
 07 003 03  0    0    0   0   0    1    1    61
 08 003 03  0    0    0   0   0    1    1    69
 09 003 03  0    0    0   0   0    1    1    71
 0a 000 00  1    0    0   0   0    0    0    00
 0b 000 00  1    0    0   0   0    0    0    00
 0c 003 03  0    0    0   0   0    1    1    79
 0d 000 00  1    0    0   0   0    0    0    00
 0e 003 03  0    0    0   0   0    1    1    81
 0f 003 03  0    0    0   0   0    1    1    89

IO APIC #5......
.... register #00: 05000000
.......    : physical APIC id: 05
.... register #01: 000F0011
.......     : max redirection entries: 000F
.......     : PRQ implemented: 0
.......     : IO APIC version: 0011
.... register #02: 05000000
.......     : arbitration: 05
.... IRQ redirection table:
 NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:   
 00 003 03  1    1    0   1   0    1    1    91
 01 003 03  1    1    0   1   0    1    1    99
 02 003 03  1    1    0   1   0    1    1    A1
 03 003 03  1    1    0   1   0    1    1    A9
 04 003 03  1    1    0   1   0    1    1    B1
 05 003 03  1    1    0   1   0    1    1    B9
 06 003 03  1    1    0   1   0    1    1    C1
 07 003 03  1    1    0   1   0    1    1    C9
 08 003 03  1    1    0   1   0    1    1    D1
 09 003 03  1    1    0   1   0    1    1    D9
 0a 003 03  1    1    0   1   0    1    1    E1
 0b 003 03  1    1    0   1   0    1    1    E9
 0c 003 03  1    1    0   1   0    1    1    32
 0d 003 03  1    1    0   1   0    1    1    3A
 0e 003 03  1    1    0   1   0    1    1    42
 0f 003 03  1    1    0   1   0    1    1    4A

IO APIC #6......
.... register #00: 06000000
.......    : physical APIC id: 06
.... register #01: 000F0011
.......     : max redirection entries: 000F
.......     : PRQ implemented: 0
.......     : IO APIC version: 0011
.... register #02: 06000000
.......     : arbitration: 06
.... IRQ redirection table:
 NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:   
 00 003 03  1    1    0   1   0    1    1    52
 01 003 03  1    1    0   1   0    1    1    5A
 02 003 03  1    1    0   1   0    1    1    62
 03 003 03  1    1    0   1   0    1    1    6A
 04 003 03  1    1    0   1   0    1    1    72
 05 003 03  1    1    0   1   0    1    1    7A
 06 003 03  1    1    0   1   0    1    1    82
 07 003 03  1    1    0   1   0    1    1    8A
 08 003 03  1    1    0   1   0    1    1    92
 09 003 03  1    1    0   1   0    1    1    9A
 0a 003 03  1    1    0   1   0    1    1    A2
 0b 003 03  1    1    0   1   0    1    1    AA
 0c 003 03  1    1    0   1   0    1    1    B2
 0d 003 03  1    1    0   1   0    1    1    BA
 0e 003 03  1    1    0   1   0    1    1    C2
 0f 000 00  1    0    0   0   0    0    0    00
IRQ to pin mappings:
IRQ0 -> 0:2
IRQ1 -> 0:1
IRQ3 -> 0:3
IRQ4 -> 0:4
IRQ5 -> 0:5
IRQ6 -> 0:6
IRQ7 -> 0:7
IRQ8 -> 0:8
IRQ9 -> 0:9
IRQ12 -> 0:12
IRQ14 -> 0:14
IRQ15 -> 0:15
IRQ16 -> 1:0
IRQ17 -> 1:1
IRQ18 -> 1:2
IRQ19 -> 1:3
IRQ20 -> 1:4
IRQ21 -> 1:5
IRQ22 -> 1:6
IRQ23 -> 1:7
IRQ24 -> 1:8
IRQ25 -> 1:9
IRQ26 -> 1:10
IRQ27 -> 1:11
IRQ28 -> 1:12
IRQ29 -> 1:13
IRQ30 -> 1:14
IRQ31 -> 1:15
IRQ32 -> 2:0
IRQ33 -> 2:1
IRQ34 -> 2:2
IRQ35 -> 2:3
IRQ36 -> 2:4
IRQ37 -> 2:5
IRQ38 -> 2:6
IRQ39 -> 2:7
IRQ40 -> 2:8
IRQ41 -> 2:9
IRQ42 -> 2:10
IRQ43 -> 2:11
IRQ44 -> 2:12
IRQ45 -> 2:13
IRQ46 -> 2:14
.................................... done.
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 1791.5168 MHz.
..... host bus clock speed is 99.5284 MHz.
cpu: 0, clocks: 995284, slice: 331761
CPU0<T0:995280,T1:663504,D:15,S:331761,C:995284>
cpu: 1, clocks: 995284, slice: 331761
CPU1<T0:995280,T1:331744,D:14,S:331761,C:995284>
checking TSC synchronization across CPUs: passed.
Waiting on wait_init_idle (map = 0x2)
All processors have done init_idle
PCI: PCI BIOS revision 2.10 entry at 0xfc67e, last bus=15
PCI: Using configuration type 1
PCI: Probing PCI hardware
Unknown bridge resource 2: assuming transparent
PCI: Discovered primary peer bus 01 [IRQ]
Unknown bridge resource 0: assuming transparent
PCI: Discovered primary peer bus 03 [IRQ]
PCI: Discovered primary peer bus 0a [IRQ]
PCI: Discovered primary peer bus 0f [IRQ]
PCI: Using IRQ router ServerWorks [1166/0201] at 00:0f.0
PCI->APIC IRQ transform: (B0,I4,P0) -> 19
PCI->APIC IRQ transform: (B0,I6,P0) -> 18
PCI->APIC IRQ transform: (B1,I6,P0) -> 22
PCI->APIC IRQ transform: (B2,I6,P0) -> 20
PCI->APIC IRQ transform: (B2,I6,P1) -> 21
PCI->APIC IRQ transform: (B4,I1,P0) -> 28
PCI->APIC IRQ transform: (B5,I0,P0) -> 27
PCI->APIC IRQ transform: (B10,I6,P0) -> 35
PCI->APIC IRQ transform: (B10,I8,P0) -> 31
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Starting kswapd
allocated 32 pages and 32 bhs reserved for the highmem bounces
VFS: Diskquotas version dquot_6.4.0 initialized
Journalled Block Device driver loaded
pty: 256 Unix98 ptys configured
Real Time Clock Driver v1.10e
block: 128 slots per queue, batch=32
eepro100.c:v1.09j-t 9/29/99 Donald Becker http://www.scyld.com/network/eepro100.html
eepro100.c: $Revision: 1.36 $ 2000/11/17 Modified by Andrey V. Savochkin <saw@saw.sw.com.sg> and others
eth0: Intel Corp. 82557 [Ethernet Pro 100], 00:B0:D0:FC:71:67, IRQ 19.
  Receiver lock-up bug exists -- enabling work-around.
  Board assembly 07195d-000, Physical connectors present: RJ45
  Primary interface chip i82555 PHY #1.
  General self-test: passed.
  Serial sub-system self-test: passed.
  Internal registers self-test: passed.
  ROM checksum self-test: passed (0x04f4518b).
  Receiver lock-up workaround activated.
eth1: OEM i82557/i82558 10/100 Ethernet, 00:02:B3:9E:60:8D, IRQ 35.
  Board assembly a64083-001, Physical connectors present: RJ45
  Primary interface chip i82555 PHY #1.
    Secondary interface chip i82555.
  General self-test: passed.
  Serial sub-system self-test: passed.
  Internal registers self-test: passed.
  ROM checksum self-test: passed (0xb874c1d3).
eth2: OEM i82557/i82558 10/100 Ethernet, 00:02:B3:9E:60:88, IRQ 31.
  Board assembly a64083-001, Physical connectors present: RJ45
  Primary interface chip i82555 PHY #1.
    Secondary interface chip i82555.
  General self-test: passed.
  Serial sub-system self-test: passed.
  Internal registers self-test: passed.
  ROM checksum self-test: passed (0xb874c1d3).
SCSI subsystem driver Revision: 1.00
scsi0 : Adaptec AIC7XXX EISA/VLB/PCI SCSI HBA DRIVER, Rev 6.2.4
        <Adaptec aic7890/91 Ultra2 SCSI adapter>
        aic7890/91: Ultra2 Wide Channel A, SCSI Id=7, 32/253 SCBs

scsi1 : Adaptec AIC7XXX EISA/VLB/PCI SCSI HBA DRIVER, Rev 6.2.4
        <Adaptec aic7899 Ultra160 SCSI adapter>
        aic7899: Ultra160 Wide Channel A, SCSI Id=7, 32/253 SCBs

scsi2 : Adaptec AIC7XXX EISA/VLB/PCI SCSI HBA DRIVER, Rev 6.2.4
        <Adaptec aic7899 Ultra160 SCSI adapter>
        aic7899: Ultra160 Wide Channel B, SCSI Id=7, 32/253 SCBs

megaraid: v1.18 (Release Date: Thu Oct 11 15:02:53 EDT 2001)
megaraid: found 0x101e:0x1960:idx 0:bus 5:slot 0:func 0
scsi3 : Found a MegaRAID controller at 0xf880c000, IRQ: 27
scsi3 : Enabling 64 bit support
megaraid: [161J:3.17] detected 2 logical drives
megaraid: channel[1] is raid.
megaraid: channel[2] is raid.
scsi3 : LSI Logic MegaRAID 161J 254 commands 16 targs 5 chans 7 luns
scsi3: scanning channel 0 for devices.
  Vendor: PE/PV     Model: 1x2 SCSI BP       Rev: 0.25
  Type:   Processor                          ANSI SCSI revision: 02
scsi3: scanning channel 1 for devices.
  Vendor: PE/PV     Model: 1x8 SCSI BP       Rev: 0.25
  Type:   Processor                          ANSI SCSI revision: 02
scsi3: scanning virtual channel 1 for logical drives.
  Vendor: MegaRAID  Model: LD0 RAID1 17278R  Rev: 161J
  Type:   Direct-Access                      ANSI SCSI revision: 02
  Vendor: MegaRAID  Model: LD1 RAID5 34556R  Rev: 161J
  Type:   Direct-Access                      ANSI SCSI revision: 02
scsi3: scanning virtual channel 2 for logical drives.
scsi3: scanning virtual channel 3 for logical drives.
scsi3: scanning virtual channel 4 for logical drives.
Attached scsi disk sda at scsi3, channel 2, id 0, lun 0
Attached scsi disk sdb at scsi3, channel 2, id 1, lun 0
SCSI device sda: 35385344 512-byte hdwr sectors (18117 MB)
Partition check:
 sda: sda1 sda2 sda3 sda4 < sda5 sda6 sda7 sda8 >
SCSI device sdb: 70770688 512-byte hdwr sectors (36235 MB)
 sdb: sdb1 sdb2 sdb3 sdb4 < sdb5 >
Attached scsi generic sg0 at scsi3, channel 0, id 6, lun 0,  type 3
Attached scsi generic sg1 at scsi3, channel 1, id 6, lun 0,  type 3
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP
IP: routing cache hash table of 16384 buckets, 128Kbytes
TCP: Hash tables configured (established 262144 bind 65536)
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
kjournald starting.  Commit interval 5 seconds
EXT3-fs: mounted filesystem with ordered data mode.
VFS: Mounted root (ext3 filesystem) readonly.
Freeing unused kernel memory: 208k freed
Adding Swap: 2096440k swap-space (priority -1)
Adding Swap: 2096472k swap-space (priority -2)
Adding Swap: 2096472k swap-space (priority -3)
Adding Swap: 2096440k swap-space (priority -4)
EXT3 FS 2.4-0.9.17, 10 Jan 2002 on sd(8,8), internal journal
md: md driver 0.90.0 MAX_MD_DEVS=256, MD_SB_DISKS=27
kjournald starting.  Commit interval 5 seconds
EXT3 FS 2.4-0.9.17, 10 Jan 2002 on sd(8,2), internal journal
EXT3-fs: mounted filesystem with ordered data mode.
kjournald starting.  Commit interval 5 seconds
EXT3 FS 2.4-0.9.17, 10 Jan 2002 on sd(8,7), internal journal
EXT3-fs: mounted filesystem with ordered data mode.
kjournald starting.  Commit interval 5 seconds
EXT3 FS 2.4-0.9.17, 10 Jan 2002 on sd(8,3), internal journal
EXT3-fs: mounted filesystem with ordered data mode.
kjournald starting.  Commit interval 5 seconds
EXT3 FS 2.4-0.9.17, 10 Jan 2002 on sd(8,5), internal journal
EXT3-fs: mounted filesystem with ordered data mode.
kjournald starting.  Commit interval 5 seconds
EXT3 FS 2.4-0.9.17, 10 Jan 2002 on sd(8,17), internal journal
EXT3-fs: mounted filesystem with ordered data mode.

[-- Attachment #4: kernel config --]
[-- Type: TEXT/PLAIN, Size: 19364 bytes --]

#
# Automatically generated make config: don't edit
#
CONFIG_X86=y
CONFIG_ISA=y
# CONFIG_SBUS is not set
CONFIG_UID16=y

#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y

#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODVERSIONS=y
CONFIG_KMOD=y

#
# Processor type and features
#
# CONFIG_M386 is not set
# CONFIG_M486 is not set
# CONFIG_M586 is not set
# CONFIG_M586TSC is not set
# CONFIG_M586MMX is not set
# CONFIG_M686 is not set
# CONFIG_MPENTIUMIII is not set
CONFIG_MPENTIUM4=y
# CONFIG_MK6 is not set
# CONFIG_MK7 is not set
# CONFIG_MELAN is not set
# CONFIG_MCRUSOE is not set
# CONFIG_MWINCHIPC6 is not set
# CONFIG_MWINCHIP2 is not set
# CONFIG_MWINCHIP3D is not set
# CONFIG_MCYRIXIII is not set
CONFIG_X86_WP_WORKS_OK=y
CONFIG_X86_INVLPG=y
CONFIG_X86_CMPXCHG=y
CONFIG_X86_XADD=y
CONFIG_X86_BSWAP=y
CONFIG_X86_POPAD_OK=y
# CONFIG_RWSEM_GENERIC_SPINLOCK is not set
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_X86_L1_CACHE_SHIFT=7
CONFIG_X86_TSC=y
CONFIG_X86_GOOD_APIC=y
CONFIG_X86_PGE=y
CONFIG_X86_USE_PPRO_CHECKSUM=y
# CONFIG_TOSHIBA is not set
# CONFIG_I8K is not set
# CONFIG_MICROCODE is not set
CONFIG_X86_MSR=m
# CONFIG_X86_CPUID is not set
# CONFIG_NOHIGHMEM is not set
CONFIG_HIGHMEM4G=y
# CONFIG_HIGHMEM64G is not set
CONFIG_HIGHMEM=y
# CONFIG_MATH_EMULATION is not set
CONFIG_MTRR=y
CONFIG_SMP=y
# CONFIG_MULTIQUAD is not set
CONFIG_HAVE_DEC_LOCK=y

#
# General setup
#
CONFIG_NET=y
CONFIG_X86_IO_APIC=y
CONFIG_X86_LOCAL_APIC=y
CONFIG_PCI=y
# CONFIG_PCI_GOBIOS is not set
# CONFIG_PCI_GODIRECT is not set
CONFIG_PCI_GOANY=y
CONFIG_PCI_BIOS=y
CONFIG_PCI_DIRECT=y
CONFIG_PCI_NAMES=y
# CONFIG_EISA is not set
# CONFIG_MCA is not set
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
# CONFIG_HOTPLUG_PCI is not set
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_SYSCTL=y
CONFIG_KCORE_ELF=y
# CONFIG_KCORE_AOUT is not set
CONFIG_BINFMT_AOUT=m
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_MISC=m
# CONFIG_PM is not set
# CONFIG_ACPI is not set
# CONFIG_APM is not set

#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set

#
# Parallel port support
#
CONFIG_PARPORT=m
CONFIG_PARPORT_PC=m
CONFIG_PARPORT_PC_CML1=m
# CONFIG_PARPORT_SERIAL is not set
# CONFIG_PARPORT_PC_FIFO is not set
# CONFIG_PARPORT_PC_SUPERIO is not set
# CONFIG_PARPORT_AMIGA is not set
# CONFIG_PARPORT_MFC3 is not set
# CONFIG_PARPORT_ATARI is not set
# CONFIG_PARPORT_GSC is not set
# CONFIG_PARPORT_SUNBPP is not set
# CONFIG_PARPORT_OTHER is not set
# CONFIG_PARPORT_1284 is not set

#
# Plug and Play configuration
#
CONFIG_PNP=y
# CONFIG_ISAPNP is not set

#
# Block devices
#
CONFIG_BLK_DEV_FD=m
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
CONFIG_BLK_DEV_LOOP=m
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=m
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_INITRD is not set

#
# Multi-device support (RAID and LVM)
#
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID5=m
CONFIG_MD_MULTIPATH=m
CONFIG_BLK_DEV_LVM=m

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
# CONFIG_NETLINK_DEV is not set
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
CONFIG_INET_ECN=y
CONFIG_SYN_COOKIES=y
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set

#
#  
#
CONFIG_IPX=m
CONFIG_IPX_INTERN=y
# CONFIG_ATALK is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set

#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set

#
# Telephony Support
#
# CONFIG_PHONE is not set
# CONFIG_PHONE_IXJ is not set
# CONFIG_PHONE_IXJ_PCMCIA is not set

#
# ATA/IDE/MFM/RLL support
#
CONFIG_IDE=m

#
# IDE, ATA and ATAPI Block devices
#
CONFIG_BLK_DEV_IDE=m

#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_HD_IDE is not set
# CONFIG_BLK_DEV_HD is not set
CONFIG_BLK_DEV_IDEDISK=m
# CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
# CONFIG_BLK_DEV_IDEDISK_IBM is not set
# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
# CONFIG_BLK_DEV_IDEDISK_WD is not set
# CONFIG_BLK_DEV_COMMERIAL is not set
# CONFIG_BLK_DEV_TIVO is not set
# CONFIG_BLK_DEV_IDECS is not set
CONFIG_BLK_DEV_IDECD=m
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_BLK_DEV_IDESCSI is not set

#
# IDE chipset support/bugfixes
#
CONFIG_BLK_DEV_CMD640=y
# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
# CONFIG_BLK_DEV_ISAPNP is not set
CONFIG_BLK_DEV_RZ1000=y
CONFIG_BLK_DEV_IDEPCI=y
# CONFIG_IDEPCI_SHARE_IRQ is not set
CONFIG_BLK_DEV_IDEDMA_PCI=y
CONFIG_BLK_DEV_ADMA=y
# CONFIG_BLK_DEV_OFFBOARD is not set
# CONFIG_IDEDMA_PCI_AUTO is not set
CONFIG_BLK_DEV_IDEDMA=y
# CONFIG_IDEDMA_PCI_WIP is not set
# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
# CONFIG_BLK_DEV_AEC62XX is not set
# CONFIG_AEC62XX_TUNING is not set
# CONFIG_BLK_DEV_ALI15X3 is not set
# CONFIG_WDC_ALI15X3 is not set
# CONFIG_BLK_DEV_AMD74XX is not set
# CONFIG_AMD74XX_OVERRIDE is not set
# CONFIG_BLK_DEV_CMD64X is not set
# CONFIG_BLK_DEV_CY82C693 is not set
# CONFIG_BLK_DEV_CS5530 is not set
# CONFIG_BLK_DEV_HPT34X is not set
# CONFIG_HPT34X_AUTODMA is not set
# CONFIG_BLK_DEV_HPT366 is not set
CONFIG_BLK_DEV_PIIX=y
# CONFIG_PIIX_TUNING is not set
# CONFIG_BLK_DEV_NS87415 is not set
# CONFIG_BLK_DEV_OPTI621 is not set
# CONFIG_BLK_DEV_PDC202XX is not set
# CONFIG_PDC202XX_BURST is not set
# CONFIG_PDC202XX_FORCE is not set
# CONFIG_BLK_DEV_SVWKS is not set
# CONFIG_BLK_DEV_SIS5513 is not set
# CONFIG_BLK_DEV_SLC90E66 is not set
# CONFIG_BLK_DEV_TRM290 is not set
# CONFIG_BLK_DEV_VIA82CXXX is not set
# CONFIG_IDE_CHIPSETS is not set
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_IDEDMA_IVB is not set
# CONFIG_DMA_NONPCI is not set
CONFIG_BLK_DEV_IDE_MODES=y
# CONFIG_BLK_DEV_ATARAID is not set
# CONFIG_BLK_DEV_ATARAID_PDC is not set
# CONFIG_BLK_DEV_ATARAID_HPT is not set

#
# SCSI support
#
CONFIG_SCSI=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_SD_EXTRA_DEVS=40
CONFIG_CHR_DEV_ST=m
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=m
# CONFIG_BLK_DEV_SR_VENDOR is not set
CONFIG_SR_EXTRA_DEVS=2
CONFIG_CHR_DEV_SG=y

#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_DEBUG_QUEUES is not set
CONFIG_SCSI_MULTI_LUN=y
CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_LOGGING is not set

#
# SCSI low-level drivers
#
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_7000FASST is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AHA152X is not set
# CONFIG_SCSI_AHA1542 is not set
# CONFIG_SCSI_AHA1740 is not set
# CONFIG_SCSI_AACRAID is not set
CONFIG_SCSI_AIC7XXX=y
CONFIG_AIC7XXX_CMDS_PER_DEVICE=8
CONFIG_AIC7XXX_RESET_DELAY_MS=15000
# CONFIG_AIC7XXX_BUILD_FIRMWARE is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_AM53C974 is not set
CONFIG_SCSI_MEGARAID=y
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_CPQFCTS is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_DTC3280 is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_EATA_DMA is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_PPA is not set
# CONFIG_SCSI_IMM is not set
# CONFIG_SCSI_NCR53C406A is not set
# CONFIG_SCSI_NCR53C7xx is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_NCR53C8XX is not set
# CONFIG_SCSI_SYM53C8XX is not set
# CONFIG_SCSI_PAS16 is not set
# CONFIG_SCSI_PCI2000 is not set
# CONFIG_SCSI_PCI2220I is not set
# CONFIG_SCSI_PSI240I is not set
# CONFIG_SCSI_QLOGIC_FAS is not set
# CONFIG_SCSI_QLOGIC_ISP is not set
# CONFIG_SCSI_QLOGIC_FC is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_SEAGATE is not set
# CONFIG_SCSI_SIM710 is not set
# CONFIG_SCSI_SYM53C416 is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_T128 is not set
# CONFIG_SCSI_U14_34F is not set
# CONFIG_SCSI_ULTRASTOR is not set
# CONFIG_SCSI_DEBUG is not set

#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
# CONFIG_FUSION_BOOT is not set
# CONFIG_FUSION_ISENSE is not set
# CONFIG_FUSION_CTL is not set
# CONFIG_FUSION_LAN is not set

#
# IEEE 1394 (FireWire) support (EXPERIMENTAL)
#
# CONFIG_IEEE1394 is not set

#
# I2O device support
#
CONFIG_I2O=m
CONFIG_I2O_PCI=m
CONFIG_I2O_BLOCK=m
# CONFIG_I2O_LAN is not set
CONFIG_I2O_SCSI=m
# CONFIG_I2O_PROC is not set

#
# Network device support
#
CONFIG_NETDEVICES=y

#
# ARCnet devices
#
# CONFIG_ARCNET is not set
CONFIG_DUMMY=m
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set

#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_SUNLANCE is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_AT1700 is not set
# CONFIG_DEPCA is not set
# CONFIG_HP100 is not set
# CONFIG_NET_ISA is not set
CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_AC3200 is not set
# CONFIG_APRICOT is not set
# CONFIG_CS89x0 is not set
# CONFIG_TULIP is not set
# CONFIG_DE4X5 is not set
# CONFIG_DGRS is not set
# CONFIG_DM9102 is not set
CONFIG_EEPRO100=y
# CONFIG_LNE390 is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_NE3210 is not set
# CONFIG_ES3210 is not set
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_8139TOO_PIO is not set
# CONFIG_8139TOO_TUNE_TWISTER is not set
# CONFIG_8139TOO_8129 is not set
# CONFIG_8139_NEW_RX_RESET is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_VIA_RHINE_MMIO is not set
# CONFIG_WINBOND_840 is not set
# CONFIG_NET_POCKET is not set

#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set

#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set

#
# Token Ring devices
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set

#
# Wan interfaces
#
# CONFIG_WAN is not set

#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set

#
# IrDA (infrared) support
#
# CONFIG_IRDA is not set

#
# ISDN subsystem
#
# CONFIG_ISDN is not set

#
# Old CD-ROM drivers (not SCSI, not IDE)
#
# CONFIG_CD_NO_IDESCSI is not set

#
# Input core support
#
# CONFIG_INPUT is not set
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set

#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_SERIAL=m
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
CONFIG_PRINTER=m
# CONFIG_LP_CONSOLE is not set
# CONFIG_PPDEV is not set

#
# I2C support
#
# CONFIG_I2C is not set

#
# Mice
#
# CONFIG_BUSMOUSE is not set
CONFIG_MOUSE=y
CONFIG_PSMOUSE=y
# CONFIG_82C710_MOUSE is not set
# CONFIG_PC110_PAD is not set

#
# Joysticks
#
# CONFIG_INPUT_GAMEPORT is not set

#
# Input core support is needed for gameports
#

#
# Input core support is needed for joysticks
#
# CONFIG_QIC02_TAPE is not set

#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
CONFIG_INTEL_RNG=y
CONFIG_NVRAM=m
CONFIG_RTC=y
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_SONYPI is not set

#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_MWAVE is not set

#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set

#
# File systems
#
CONFIG_QUOTA=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
CONFIG_EXT3_FS=y
CONFIG_JBD=y
CONFIG_JBD_DEBUG=y
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
# CONFIG_UMSDOS_FS is not set
CONFIG_VFAT_FS=m
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=m
CONFIG_TMPFS=y
CONFIG_RAMFS=m
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
# CONFIG_ZISOFS is not set
CONFIG_MINIX_FS=m
# CONFIG_VXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
CONFIG_ROMFS_FS=m
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
CONFIG_UFS_FS=m
# CONFIG_UFS_FS_WRITE is not set

#
# Network File Systems
#
CONFIG_CODA_FS=m
CONFIG_INTERMEZZO_FS=m
CONFIG_NFS_FS=m
CONFIG_NFS_V3=y
# CONFIG_ROOT_NFS is not set
CONFIG_NFSD=m
CONFIG_NFSD_V3=y
CONFIG_SUNRPC=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_SMB_FS=m
CONFIG_SMB_NLS_DEFAULT=y
CONFIG_SMB_NLS_REMOTE="cp437"
CONFIG_NCP_FS=m
CONFIG_NCPFS_PACKET_SIGNING=y
CONFIG_NCPFS_IOCTL_LOCKING=y
CONFIG_NCPFS_STRONG=y
CONFIG_NCPFS_NFS_NS=y
CONFIG_NCPFS_OS2_NS=y
# CONFIG_NCPFS_SMALLDOS is not set
CONFIG_NCPFS_NLS=y
CONFIG_NCPFS_EXTRAS=y
# CONFIG_ZISOFS_FS is not set
CONFIG_ZLIB_FS_INFLATE=m

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
CONFIG_OSF_PARTITION=y
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
CONFIG_LDM_PARTITION=y
# CONFIG_LDM_DEBUG is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
CONFIG_SUN_PARTITION=y
CONFIG_SMB_NLS=y
CONFIG_NLS=y

#
# Native Language Support
#
CONFIG_NLS_DEFAULT="cp437"
CONFIG_NLS_CODEPAGE_437=m
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ISO8859_1=m
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set

#
# Console drivers
#
CONFIG_VGA_CONSOLE=y
# CONFIG_VIDEO_SELECT is not set
# CONFIG_MDA_CONSOLE is not set

#
# Frame-buffer support
#
# CONFIG_FB is not set

#
# Sound
#
# CONFIG_SOUND is not set

#
# USB support
#
# CONFIG_USB is not set

#
# USB Controllers
#
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
# CONFIG_USB_OHCI is not set

#
# USB Device Class drivers
#
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_STORAGE is not set
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_HP8200e is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set

#
# USB Human Interface Devices (HID)
#

#
#   Input core support is needed for USB HID
#

#
# USB Imaging devices
#
# CONFIG_USB_DC2XX is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_SCANNER is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_HPUSBSCSI is not set

#
# USB Multimedia devices
#

#
#   Video4Linux support is needed for USB Multimedia device support
#

#
# USB Network adaptors
#
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_CDCETHER is not set
# CONFIG_USB_USBNET is not set

#
# USB port drivers
#
# CONFIG_USB_USS720 is not set

#
# USB Serial Converter support
#
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SERIAL_GENERIC is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_IPAQ is not set
# CONFIG_USB_SERIAL_IR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_KLSI is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_XIRCOM is not set
# CONFIG_USB_SERIAL_OMNINET is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_RIO500 is not set

#
# Bluetooth support
#
# CONFIG_BLUEZ is not set

#
# Kernel hacking
#
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_HIGHMEM is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_IOVIRT is not set
CONFIG_MAGIC_SYSRQ=y
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_BUGVERBOSE is not set

[-- Attachment #5: /proc info --]
[-- Type: TEXT/PLAIN, Size: 1478 bytes --]

output from /proc/cpuinfo
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 15
model		: 2
model name	: Intel(R) XEON(TM) CPU 1.80GHz
stepping	: 4
cpu MHz		: 1791.317
cache size	: 512 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 2
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm
bogomips	: 3565.15

processor	: 1
vendor_id	: GenuineIntel
cpu family	: 15
model		: 2
model name	: Intel(R) XEON(TM) CPU 1.80GHz
stepping	: 4
cpu MHz		: 1791.317
cache size	: 512 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 2
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm
bogomips	: 3578.26

output from /proc/interrupts
           CPU0       CPU1       
  0:     469709        221    IO-APIC-edge  timer
  1:          3          0    IO-APIC-edge  keyboard
  2:          0          0          XT-PIC  cascade
  8:          2          0    IO-APIC-edge  rtc
 18:         15          0   IO-APIC-level  aic7xxx
 19:      42366        148   IO-APIC-level  eth0
 20:         16          0   IO-APIC-level  aic7xxx
 21:         16          0   IO-APIC-level  aic7xxx
 27:       6508         46   IO-APIC-level  megaraid
NMI:          0          0 
LOC:     469721     469658 
ERR:          0
MIS:          0

Re: SMP P4 APIC/interrupt balancing

[Martin J. Bligh]

> Current kernel is 2.4.18 with the LSE APIC Routing patch
> (http://sourceforge.net/projects/lse).  2.4.18 stock (well ok, -rc4) 
> has much the same results.

I hate to ask trivial questions, but you did read the notes that
come with the APIC routing patch, and actually enable it, right?
IIRC, there was something about a command line parameter needed.

just checking ...

M.

Re: SMP P4 APIC/interrupt balancing

[James Bourne]

On Tue, 16 Apr 2002, Martin J. Bligh wrote:

> > Current kernel is 2.4.18 with the LSE APIC Routing patch
> > (http://sourceforge.net/projects/lse).  2.4.18 stock (well ok, -rc4) 
> > has much the same results.
> 
> I hate to ask trivial questions, but you did read the notes that
> come with the APIC routing patch, and actually enable it, right?
> IIRC, there was something about a command line parameter needed.
> 
> just checking ...

:) I knew I should have included that in the original message, but it's
also in the dmesg output.  append"idle=poll" is there.

There may be other issues, and I need to get physical access to the system
to check (tomorrow)...  

Regards
James Bourne

> 
> M.
> 

-- 
James Bourne, Supervisor Data Centre Operations
Mount Royal College, Calgary, AB, CA
www.mtroyal.ab.ca

******************************************************************************
This communication is intended for the use of the recipient to which it is
addressed, and may contain confidential, personal, and or privileged
information. Please contact the sender immediately if you are not the
intended recipient of this communication, and do not copy, distribute, or
take action relying on it. Any communication received in error, or
subsequent reply, should be deleted or destroyed.
******************************************************************************

Re: SMP P4 APIC/interrupt balancing

[Shuji YAMAMURA]

At Tue, 16 Apr 2002 16:29:32 -0600 (MDT),
James Bourne <jbourne@MtRoyal.AB.CA> wrote:
> Hi All,
> Ok, we have a Dell PE4600 with dual P4X processors.  It will not balance
> interrupts between the two cpus, CPU0 always receives the bulk
> of the interrupts, although both processors are being utilized
> by processes on the system.  This system is not yet in production, so I
> have some time to try things on it.
> 
> Current kernel is 2.4.18 with the LSE APIC Routing patch
> (http://sourceforge.net/projects/lse).  2.4.18 stock (well ok, -rc4) has
> much the same results.

We observed the similar problem on our i860 based P4 SMP machine.
We examined several tests and got the following fact:

    - Only the upper 4 bits of the task priority is effective on
      Pentium 4.

The LSE APIC Routing patch assigns values from 0x10 to 0x18 to TPR for
setting task priority, that means the upper 4 bits are always '0001'.
Based on the previous obserbation, these values are useless in terms
of proper interrupt distribution.

To get an expected operation, upper 4 bits must be changed.

You may refer the following thread that talks this problem.
  "P4 SMP load balancing"
  http://marc.theaimsgroup.com/?t=100287923700006&r=1&w=2


Appendix.

Our experiments were examined on two different systems.

The following table shows the relations between the TPR value of each
CPU and the interrupt destination.

Pentium4 Machine:
  CPU: Pentium4 Xeon 2.0GHz x 2
  Motherboard: Supermicro P4DCE
  Chipset: Intel860

Pentium3 Machine:
  CPU: Pentium3 500MHz x 2
  Motherboard: ASUS CUR-DLS
  Chipset: Serverworks ServerSet3 LE

Boot Processor: CPU#0
   TPR Value     Interrupt CPU
  CPU#0 CPU#1     Pen3   Pen4
=========================================
    01    02      0or1    0
    02    01      0or1    0
    0f    00      0or1    0
-----------------------------------------
    10    01       1      1
    10    11       0      0
    11    10       1      0
    1f    10       1      0
    11    11      0or1    0
-----------------------------------------
    20    20      0or1    0
    20    10       1      1
    20    21       0      0
    21    20       1      0
-----------------------------------------

----
Shuji YAMAMURA
Grid Computing & Bioinformatics Laboratory, FUJITSU Laboratories, LTD.
E-mail: yamamura@flab.fujitsu.co.jp

Re: SMP P4 APIC/interrupt balancing

[Ingo Molnar]

On Wed, 17 Apr 2002, James Bourne wrote:

> After Ingo forwarded me his original patch (I found his patch via a web
> based medium, which had converted all of the left shifts to compares,
> and now I'm very glad it didn't boot...) and the system is booted and is
> balancing most of the interrupts at least.  Here's the current output of
> /proc/interrupts
> 
> brynhild:bash$ cat /proc/interrupts 
>            CPU0       CPU1       
>   0:     171414          0    IO-APIC-edge  timer
>   1:          3          2    IO-APIC-edge  keyboard
>   2:          0          0          XT-PIC  cascade
>   8:          1          0    IO-APIC-edge  rtc
>  18:          8          7   IO-APIC-level  aic7xxx
>  19:      13566      12799   IO-APIC-level  eth0
>  20:          9          7   IO-APIC-level  aic7xxx
>  21:          9          7   IO-APIC-level  aic7xxx
>  27:       1572       5371   IO-APIC-level  megaraid
> NMI:          0          0 
> LOC:     171315     171251 
> ERR:          0
> MIS:          0

it's looking good.

> So, the timer isn't being balanced still, others are (is there a
> specific case in your patch for irq 0 (< 1)?  I couldn't see it but it
> almost looks as though it's being missed..)

it's a separate bug, solved by a separate patch.

	Ingo

Re: SMP P4 APIC/interrupt balancing

[James Bourne]

Ok,
After Ingo forwarded me his original patch (I found his patch via a web
based medium, which had converted all of the left shifts to compares, and
now I'm very glad it didn't boot...) and the system is booted and is
balancing most of the interrupts at least.  Here's the current output
of /proc/interrupts

brynhild:bash$ cat /proc/interrupts 
           CPU0       CPU1       
  0:     171414          0    IO-APIC-edge  timer
  1:          3          2    IO-APIC-edge  keyboard
  2:          0          0          XT-PIC  cascade
  8:          1          0    IO-APIC-edge  rtc
 18:          8          7   IO-APIC-level  aic7xxx
 19:      13566      12799   IO-APIC-level  eth0
 20:          9          7   IO-APIC-level  aic7xxx
 21:          9          7   IO-APIC-level  aic7xxx
 27:       1572       5371   IO-APIC-level  megaraid
NMI:          0          0 
LOC:     171315     171251 
ERR:          0
MIS:          0

So, the timer isn't being balanced still, others are (is there a
specific case in your patch for irq 0 (< 1)?  I couldn't see it but
it almost looks as though it's being missed..)

Thanks to all that replied.

Regards
James 

-- 
James Bourne, Supervisor Data Centre Operations
Mount Royal College, Calgary, AB, CA
www.mtroyal.ab.ca

******************************************************************************
This communication is intended for the use of the recipient to which it is
addressed, and may contain confidential, personal, and or privileged
information. Please contact the sender immediately if you are not the
intended recipient of this communication, and do not copy, distribute, or
take action relying on it. Any communication received in error, or
subsequent reply, should be deleted or destroyed.
******************************************************************************

Re: SMP P4 APIC/interrupt balancing

[Ingo Molnar]

On Wed, 17 Apr 2002, Steffen Persvold wrote:

> Are any of these patches going into the mainline kernel soon ?

my irqbalance patch is in Linus' tree already, it should show up in the
next 2.5.9-pre kernel.

	Ingo

Re: SMP P4 APIC/interrupt balancing

[Ingo Molnar]

On Wed, 17 Apr 2002, James Bourne wrote:

> Where would I find this separate patch?  Is there something I could do
> some testing on?

the timer irq inbalance problem should be solved by the attached patch.

	Ingo

diff -up --recursive --new-file linux-2.4.18.macro/arch/i386/kernel/io_apic.c linux-2.4.18/arch/i386/kernel/io_apic.c
--- linux-2.4.18.macro/arch/i386/kernel/io_apic.c	Fri Nov 23 15:32:04 2001
+++ linux-2.4.18/arch/i386/kernel/io_apic.c	Fri Mar  1 14:58:20 2002
@@ -67,7 +67,7 @@ static struct irq_pin_list {
  * shared ISA-space IRQs, so we have to support them. We are super
  * fast in the common case, and fast for shared ISA-space IRQs.
  */
-static void add_pin_to_irq(unsigned int irq, int apic, int pin)
+static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
 {
 	static int first_free_entry = NR_IRQS;
 	struct irq_pin_list *entry = irq_2_pin + irq;
@@ -85,6 +85,26 @@ static void add_pin_to_irq(unsigned int 
 	entry->pin = pin;
 }
 
+/*
+ * Reroute an IRQ to a different pin.
+ */
+static void __init replace_pin_at_irq(unsigned int irq,
+				      int oldapic, int oldpin,
+				      int newapic, int newpin)
+{
+	struct irq_pin_list *entry = irq_2_pin + irq;
+
+	while (1) {
+		if (entry->apic == oldapic && entry->pin == oldpin) {
+			entry->apic = newapic;
+			entry->pin = newpin;
+		}
+		if (!entry->next)
+			break;
+		entry = irq_2_pin + entry->next;
+	}
+}
+
 #define __DO_ACTION(R, ACTION, FINAL)					\
 									\
 {									\
@@ -1533,6 +1553,10 @@ static inline void check_timer(void)
 		setup_ExtINT_IRQ0_pin(pin2, vector);
 		if (timer_irq_works()) {
 			printk("works.\n");
+			if (pin1 != -1)
+				replace_pin_at_irq(0, 0, pin1, 0, pin2);
+			else
+				add_pin_to_irq(0, 0, pin2);
 			if (nmi_watchdog == NMI_IO_APIC) {
 				setup_nmi();
 				check_nmi_watchdog();

Re: SMP P4 APIC/interrupt balancing

[Steffen Persvold]

On Wed, 17 Apr 2002, Ingo Molnar wrote:

>
> On Wed, 17 Apr 2002, James Bourne wrote:
>
> > After Ingo forwarded me his original patch (I found his patch via a web
> > based medium, which had converted all of the left shifts to compares,
> > and now I'm very glad it didn't boot...) and the system is booted and is
> > balancing most of the interrupts at least.  Here's the current output of
> > /proc/interrupts
> >
> > brynhild:bash$ cat /proc/interrupts
> >            CPU0       CPU1
> >   0:     171414          0    IO-APIC-edge  timer
> >   1:          3          2    IO-APIC-edge  keyboard
> >   2:          0          0          XT-PIC  cascade
> >   8:          1          0    IO-APIC-edge  rtc
> >  18:          8          7   IO-APIC-level  aic7xxx
> >  19:      13566      12799   IO-APIC-level  eth0
> >  20:          9          7   IO-APIC-level  aic7xxx
> >  21:          9          7   IO-APIC-level  aic7xxx
> >  27:       1572       5371   IO-APIC-level  megaraid
> > NMI:          0          0
> > LOC:     171315     171251
> > ERR:          0
> > MIS:          0
>
> it's looking good.
>
> > So, the timer isn't being balanced still, others are (is there a
> > specific case in your patch for irq 0 (< 1)?  I couldn't see it but it
> > almost looks as though it's being missed..)
>
> it's a separate bug, solved by a separate patch.
>
> 	Ingo
>

Ingo,

Are any of these patches going into the mainline kernel soon ?

Regards,
-- 
  Steffen Persvold   | Scalable Linux Systems |   Try out the world's best
 mailto:sp@scali.com |  http://www.scali.com  | performing MPI implementation:
Tel: (+47) 2262 8950 |   Olaf Helsets vei 6   |      - ScaMPI 1.13.8 -
Fax: (+47) 2262 8951 |   N0621 Oslo, NORWAY   | >320MBytes/s and <4uS latency

Re: SMP P4 APIC/interrupt balancing

[James Bourne]

On Wed, 17 Apr 2002, Ingo Molnar wrote:

> 
> On Wed, 17 Apr 2002, James Bourne wrote:
> > So, the timer isn't being balanced still, others are (is there a
> > specific case in your patch for irq 0 (< 1)?  I couldn't see it but it
> > almost looks as though it's being missed..)
> 
> it's a separate bug, solved by a separate patch.
> 

Where would I find this separate patch?  Is there something I could do
some testing on?

Thanks and regards
James

> 	Ingo
> 

-- 
James Bourne, Supervisor Data Centre Operations
Mount Royal College, Calgary, AB, CA
www.mtroyal.ab.ca

******************************************************************************
This communication is intended for the use of the recipient to which it is
addressed, and may contain confidential, personal, and or privileged
information. Please contact the sender immediately if you are not the
intended recipient of this communication, and do not copy, distribute, or
take action relying on it. Any communication received in error, or
subsequent reply, should be deleted or destroyed.
******************************************************************************

Re: SMP P4 APIC/interrupt balancing

[Steffen Persvold]

On Wed, 17 Apr 2002, Ingo Molnar wrote:

>
> On Wed, 17 Apr 2002, James Bourne wrote:
>
> > After Ingo forwarded me his original patch (I found his patch via a web
> > based medium, which had converted all of the left shifts to compares,
> > and now I'm very glad it didn't boot...) and the system is booted and is
> > balancing most of the interrupts at least.  Here's the current output of
> > /proc/interrupts
> >
> > brynhild:bash$ cat /proc/interrupts
> >            CPU0       CPU1
> >   0:     171414          0    IO-APIC-edge  timer
> >   1:          3          2    IO-APIC-edge  keyboard
> >   2:          0          0          XT-PIC  cascade
> >   8:          1          0    IO-APIC-edge  rtc
> >  18:          8          7   IO-APIC-level  aic7xxx
> >  19:      13566      12799   IO-APIC-level  eth0
> >  20:          9          7   IO-APIC-level  aic7xxx
> >  21:          9          7   IO-APIC-level  aic7xxx
> >  27:       1572       5371   IO-APIC-level  megaraid
> > NMI:          0          0
> > LOC:     171315     171251
> > ERR:          0
> > MIS:          0
>
> it's looking good.
>
> > So, the timer isn't being balanced still, others are (is there a
> > specific case in your patch for irq 0 (< 1)?  I couldn't see it but it
> > almost looks as though it's being missed..)
>
> it's a separate bug, solved by a separate patch.
>

Hi again,

Hmm, is that something ServerWorks specific because on my Plumas chipset
the timer interrupt is balanced just fine :

(sp@puma2:~)> cat /proc/interrupts
           CPU0       CPU1
  0:   14358402   14297319    IO-APIC-edge  timer
  1:          2          1    IO-APIC-edge  keyboard
  2:          0          0          XT-PIC  cascade
  4:        336        325    IO-APIC-edge  serial
  8:          1          0    IO-APIC-edge  rtc
  9:          0          0    IO-APIC-edge  acpi
 15:          3          1    IO-APIC-edge  ide1
 16:          0          0   IO-APIC-level  usb-uhci
 17:     576744     574959   IO-APIC-level  eth0
 18:          0          0   IO-APIC-level  usb-uhci
 19:          0          0   IO-APIC-level  usb-uhci
 28:      72602      71619   IO-APIC-level  aic7xxx
 29:          8          8   IO-APIC-level  aic7xxx
 31:          0          0   IO-APIC-level  e1000
 48:     289545     269389   IO-APIC-level  ssci
NMI:          0          0
LOC:   28654183   28654202
PMC:          0          0
ERR:          0
MIS:          0

Regards,
-- 
  Steffen Persvold   | Scalable Linux Systems |   Try out the world's best
 mailto:sp@scali.com |  http://www.scali.com  | performing MPI implementation:
Tel: (+47) 2262 8950 |   Olaf Helsets vei 6   |      - ScaMPI 1.13.8 -
Fax: (+47) 2262 8951 |   N0621 Oslo, NORWAY   | >320MBytes/s and <4uS latency

Re: SMP P4 APIC/interrupt balancing

[Steffen Persvold]

On Wed, 17 Apr 2002, Ingo Molnar wrote:

>
> On Wed, 17 Apr 2002, Steffen Persvold wrote:
>
> > Are any of these patches going into the mainline kernel soon ?
>
> my irqbalance patch is in Linus' tree already, it should show up in the
> next 2.5.9-pre kernel.
>

What about 2.4.x ?

Regards,
-- 
  Steffen Persvold   | Scalable Linux Systems |   Try out the world's best
 mailto:sp@scali.com |  http://www.scali.com  | performing MPI implementation:
Tel: (+47) 2262 8950 |   Olaf Helsets vei 6   |      - ScaMPI 1.13.8 -
Fax: (+47) 2262 8951 |   N0621 Oslo, NORWAY   | >320MBytes/s and <4uS latency

Re: SMP P4 APIC/interrupt balancing

[James Bourne]

On Wed, 17 Apr 2002, Steffen Persvold wrote:

> On Wed, 17 Apr 2002, Ingo Molnar wrote:
> 
> >
> > On Wed, 17 Apr 2002, James Bourne wrote:
> >
> > > After Ingo forwarded me his original patch (I found his patch via a web
> > > based medium, which had converted all of the left shifts to compares,
> > > and now I'm very glad it didn't boot...) and the system is booted and is
> > > balancing most of the interrupts at least.  Here's the current output of
> > > /proc/interrupts
> > >
> > > brynhild:bash$ cat /proc/interrupts
> > >            CPU0       CPU1
> > >   0:     171414          0    IO-APIC-edge  timer
> > >   1:          3          2    IO-APIC-edge  keyboard
> > >   2:          0          0          XT-PIC  cascade
> > >   8:          1          0    IO-APIC-edge  rtc
> > >  18:          8          7   IO-APIC-level  aic7xxx
> > >  19:      13566      12799   IO-APIC-level  eth0
> > >  20:          9          7   IO-APIC-level  aic7xxx
> > >  21:          9          7   IO-APIC-level  aic7xxx
> > >  27:       1572       5371   IO-APIC-level  megaraid
> > > NMI:          0          0
> > > LOC:     171315     171251
> > > ERR:          0
> > > MIS:          0
> >
> > it's looking good.
> >
> > > So, the timer isn't being balanced still, others are (is there a
> > > specific case in your patch for irq 0 (< 1)?  I couldn't see it but it
> > > almost looks as though it's being missed..)
> >
> > it's a separate bug, solved by a separate patch.
> >
> 
> Hi again,
> 
> Hmm, is that something ServerWorks specific because on my Plumas chipset
> the timer interrupt is balanced just fine :

Hi,
This has a ServerWorks GCHE chipset if I'm reading the docs I've found
correctly.

http://www.serverworks.com/products/GCHE.html

Regards,
James


-- 
James Bourne, Supervisor Data Centre Operations
Mount Royal College, Calgary, AB, CA
www.mtroyal.ab.ca

******************************************************************************
This communication is intended for the use of the recipient to which it is
addressed, and may contain confidential, personal, and or privileged
information. Please contact the sender immediately if you are not the
intended recipient of this communication, and do not copy, distribute, or
take action relying on it. Any communication received in error, or
subsequent reply, should be deleted or destroyed.
******************************************************************************

Re: SMP P4 APIC/interrupt balancing

[James Bourne]

On Wed, 17 Apr 2002, Ingo Molnar wrote:

> 
> On Wed, 17 Apr 2002, James Bourne wrote:
> 
> > Where would I find this separate patch?  Is there something I could do
> > some testing on?
> 
> the timer irq inbalance problem should be solved by the attached patch.

Thanks Ingo,
That has balanced the timer irqs.  I've also enabled hyper threading
(append="acpismp=force").

Here's the output from /proc/interrupts:
brynhild:bash$ cat /proc/interrupts 
           CPU0       CPU1       CPU2       CPU3       
  0:       3033       2911       2871       2880    IO-APIC-edge  timer
  1:          1          0          2          0    IO-APIC-edge  keyboard
  2:          0          0          0          0          XT-PIC  cascade
  8:          1          0          0          0    IO-APIC-edge  rtc
 18:          5          3          3          4   IO-APIC-level  aic7xxx
 19:        480        421        412        529   IO-APIC-level  eth0
 20:          5          3          4          4   IO-APIC-level  aic7xxx
 21:          5          3          4          4   IO-APIC-level  aic7xxx
 27:        588       1010        654        943   IO-APIC-level  megaraid
NMI:          0          0          0          0 
LOC:      11530      11528      11528      11466 
ERR:          0
MIS:          0

And, you've gotta like this line:
Total of 4 processors activated (14299.95 BogoMIPS).

I'm going to do some testing on it to check it's stability.
I'll let you know the results.

Thanks again and regards,
James

> 
> 	Ingo
> 

-- 
James Bourne, Supervisor Data Centre Operations
Mount Royal College, Calgary, AB, CA
www.mtroyal.ab.ca

******************************************************************************
This communication is intended for the use of the recipient to which it is
addressed, and may contain confidential, personal, and or privileged
information. Please contact the sender immediately if you are not the
intended recipient of this communication, and do not copy, distribute, or
take action relying on it. Any communication received in error, or
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******************************************************************************

Re: Hyperthreading

[Robert Love]

On Wed, 2002-04-17 at 17:10, Martin J. Bligh wrote:
> > Total of 4 processors activated (14299.95 BogoMIPS).
> 
> Before you get too excited about that, how much performance boost do 
> you actually get by turning on Hyperthreading? ;-)

Certainly not the mips*4 that bogomips is showing :)

I guess that is a "bug" ?

	Robert Love

Re: Hyperthreading

[Dave Jones]

On Wed, Apr 17, 2002 at 04:15:42PM -0400, Robert Love wrote:
 > > > Total of 4 processors activated (14299.95 BogoMIPS).
 > Certainly not the mips*4 that bogomips is showing :)
 > I guess that is a "bug" ?

Well, it justifies a comment in arch/i386/kernel/smpboot.c

1181     /*
1182      * Allow the user to impress friends.
1183      */

8-)

    Dave.

-- 
| Dave Jones.        http://www.codemonkey.org.uk
| SuSE Labs

Re: Hyperthreading

[James Bourne]

On Wed, 17 Apr 2002, Martin J. Bligh wrote:

> > That has balanced the timer irqs.  I've also enabled hyper threading
> > (append="acpismp=force").
> > ...
> > And, you've gotta like this line:
> > Total of 4 processors activated (14299.95 BogoMIPS).
> 
> Before you get too excited about that, how much performance boost do 
> you actually get by turning on Hyperthreading? ;-)

Well, that's something I'm working on finding out.

But, you have to like the looks of it!

James

> 
> M.
> 

-- 
James Bourne, Supervisor Data Centre Operations
Mount Royal College, Calgary, AB, CA
www.mtroyal.ab.ca

******************************************************************************
This communication is intended for the use of the recipient to which it is
addressed, and may contain confidential, personal, and or privileged
information. Please contact the sender immediately if you are not the
intended recipient of this communication, and do not copy, distribute, or
take action relying on it. Any communication received in error, or
subsequent reply, should be deleted or destroyed.
******************************************************************************

Hyperthreading

[Martin J. Bligh]

> That has balanced the timer irqs.  I've also enabled hyper threading
> (append="acpismp=force").
> ...
> And, you've gotta like this line:
> Total of 4 processors activated (14299.95 BogoMIPS).

Before you get too excited about that, how much performance boost do 
you actually get by turning on Hyperthreading? ;-)

M.

Re: Hyperthreading

[Jeff V. Merkey]

Beware!  I have seen lockups and driver sickness with hyperthreading 
enabled on some motherboards.  Most notably, Tyan with 2.4.19 and
2.5.6.  


Jeff

On Wed, Apr 17, 2002 at 04:15:42PM -0400, Robert Love wrote:
> On Wed, 2002-04-17 at 17:10, Martin J. Bligh wrote:
> > > Total of 4 processors activated (14299.95 BogoMIPS).
> > 
> > Before you get too excited about that, how much performance boost do 
> > you actually get by turning on Hyperthreading? ;-)
> 
> Certainly not the mips*4 that bogomips is showing :)
> 
> I guess that is a "bug" ?
> 
> 	Robert Love
> 
> 
> -
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

Re: Hyperthreading

[Jeff V. Merkey]

On Wed, Apr 17, 2002 at 02:10:52PM -0700, Martin J. Bligh wrote:
> > That has balanced the timer irqs.  I've also enabled hyper threading
> > (append="acpismp=force").
> > ...
> > And, you've gotta like this line:
> > Total of 4 processors activated (14299.95 BogoMIPS).
> 
> Before you get too excited about that, how much performance boost do 
> you actually get by turning on Hyperthreading? ;-)
> 

In my testing with SCI, it speeds up some operations and with 3Ware 
it increases throuput about 10 MB/S.  Not a lot but there is some 
improvement (if you can get around the lockups during boot).

Jeff


> M.
> 
> -
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

Re: Hyperthreading

[Alan Cox]

> > And, you've gotta like this line:
> > Total of 4 processors activated (14299.95 BogoMIPS).
> 
> Before you get too excited about that, how much performance boost do 
> you actually get by turning on Hyperthreading? ;-)

10-30% typically. I've actually seen code where you can't measure the
improvement because the main cpu code path is precision tuned to the 
cache...

Re: Hyperthreading

[Martin J. Bligh]

>> Before you get too excited about that, how much performance boost do 
>> you actually get by turning on Hyperthreading? ;-)
> 
> In my testing with SCI, it speeds up some operations and with 3Ware 
> it increases throuput about 10 MB/S.  Not a lot but there is some 
> improvement (if you can get around the lockups during boot).

What's that 10MB/s as a percentage of the overall performance?

M.

Re: Hyperthreading

[Jeff V. Merkey]

On Wed, Apr 17, 2002 at 05:31:05PM -0700, Martin J. Bligh wrote:
> >> Before you get too excited about that, how much performance boost do 
> >> you actually get by turning on Hyperthreading? ;-)
> > 
> > In my testing with SCI, it speeds up some operations and with 3Ware 
> > it increases throuput about 10 MB/S.  Not a lot but there is some 
> > improvement (if you can get around the lockups during boot).
> 
> What's that 10MB/s as a percentage of the overall performance?
> 
> M.

247-251 (with) vs. 227-238 (without) MB/S

Jeff  

Re: SMP P4 APIC/interrupt balancing

[Maciej W. Rozycki]

On Wed, 17 Apr 2002, Steffen Persvold wrote:

> Hmm, is that something ServerWorks specific because on my Plumas chipset
> the timer interrupt is balanced just fine :

 It's specific to certain timer IRQ routing setups, ServerWorks being one
of them.  I consider them braindamaged but that's just my opinion.  We
handle them fine (modulo bugs).

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

Re: SMP P4 APIC/interrupt balancing

[Bill Davidsen]

On Wed, 17 Apr 2002, James Bourne wrote:

> After Ingo forwarded me his original patch (I found his patch via a web
> based medium, which had converted all of the left shifts to compares, and
> now I'm very glad it didn't boot...) and the system is booted and is
> balancing most of the interrupts at least.  Here's the current output
> of /proc/interrupts

  Is this positive or negative on performance? If you have a system
getting so many interrupts that one CPU can't handle them, obviously there
is a gain. However, by thrashing the cache of all CPUs instead of just one
you have some memory performance cost.

  I first looked at this for a mainframe vendor who decided that putting
all the interrupts in one CPU was better. That was then, this is now, but
I am curious about metrics, like real and system time doing a kernel
compile, etc.

-- 
bill davidsen <davidsen@tmr.com>
  CTO, TMR Associates, Inc
Doing interesting things with little computers since 1979.

Re: SMP P4 APIC/interrupt balancing

[Dave Olien]

Cache warmth in handling interrupts is good.  In fact, this is one
of the reasons to use interrupt affinity.

But, directing all interrupts to single processor penalizes unfairly any
tasks that are scheduled to run on that processor.  Under heavy interrupt
load, a tasks can become effectively "pinned" onto that processor, unable
to get cpu time to make progress, and unable to be scheduled somewhere
else.

Under really heavy interrupt load, it's good to have
many processors handling interrupts.  It increases rate the system
can handle interrupts, and it reduces the latency of individual interrupts.


Dave.


> From linux-kernel-owner@vger.kernel.org Thu Apr 18 09:11:22 2002
> Date: 	Thu, 18 Apr 2002 12:04:35 -0400 (EDT)
> From: Bill Davidsen <davidsen@tmr.com>
> To: James Bourne <jbourne@MtRoyal.AB.CA>
> cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
>    Ingo Molnar <mingo@elte.hu>
> Subject: Re: SMP P4 APIC/interrupt balancing
> 
>   Is this positive or negative on performance? If you have a system
> getting so many interrupts that one CPU can't handle them, obviously there
> is a gain. However, by thrashing the cache of all CPUs instead of just one
> you have some memory performance cost.
> 
>   I first looked at this for a mainframe vendor who decided that putting
> all the interrupts in one CPU was better. That was then, this is now, but
> I am curious about metrics, like real and system time doing a kernel
> compile, etc.
> 

Re: SMP P4 APIC/interrupt balancing

[Maciej W. Rozycki]

On Thu, 18 Apr 102 rico-linux-kernel@patternassociates.com wrote:

> Interrupts are nicely load-balanced on my ServerWorks machine under 2.4.17:

 This is always the case for dedicated inter-APIC bus setups, i.e. 
everything up to P3, as the bus protocol supports priority arbitration. 

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

Re: SMP P4 APIC/interrupt balancing

[Ingo Molnar]

On Thu, 18 Apr 2002, Dave Olien wrote:

> Cache warmth in handling interrupts is good.  In fact, this is one of
> the reasons to use interrupt affinity.

and in fact this is why IRQ handlers in the irqbalance patch stay affine
to a single CPU for at least 10 msecs. So for most practical purposes when
there is no direct affinity between tasks and IRQs, this brings us very
close the highest possible affinity that can be achieved.

/proc/irq/*/smp_affinity is still preserved for those workloads when some
direct relationship can be established between process activity and IRQ
load. (such as perfectly partitioned server workloads.)

> But, directing all interrupts to single processor penalizes unfairly any
> tasks that are scheduled to run on that processor.  Under heavy
> interrupt load, a tasks can become effectively "pinned" onto that
> processor, unable to get cpu time to make progress, and unable to be
> scheduled somewhere else.
> 
> Under really heavy interrupt load, it's good to have many processors
> handling interrupts.  It increases rate the system can handle
> interrupts, and it reduces the latency of individual interrupts.

yes, this is why the irqbalance patch goes to great lengths to assure that
distribution of IRQs is as random as possible, with the following
variation: idle CPUs are more likely to be used by the IRQ balancing
mechanism than busy CPUs.

	Ingo

Re: SMP P4 APIC/interrupt balancing

[Mark Hounschell]

Bill Davidsen wrote:
> 
> On Wed, 17 Apr 2002, James Bourne wrote:
> 
> > After Ingo forwarded me his original patch (I found his patch via a web
> > based medium, which had converted all of the left shifts to compares, and
> > now I'm very glad it didn't boot...) and the system is booted and is
> > balancing most of the interrupts at least.  Here's the current output
> > of /proc/interrupts
> 

Is there a version of this patch for 2.4.18? I also found the one on the web site wouldn't
boot but would very much like to have a copy that would work for 2.4.18. Where might I find
this?

Ragards
Mark

Re: SMP P4 APIC/interrupt balancing

[James Bourne]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 1988 bytes --]

On Fri, 19 Apr 2002, Mark Hounschell wrote:

> Bill Davidsen wrote:
> > 
> > On Wed, 17 Apr 2002, James Bourne wrote:
> > 
> > > After Ingo forwarded me his original patch (I found his patch via a web
> > > based medium, which had converted all of the left shifts to compares, and
> > > now I'm very glad it didn't boot...) and the system is booted and is
> > > balancing most of the interrupts at least.  Here's the current output
> > > of /proc/interrupts
> > 
> 
> Is there a version of this patch for 2.4.18? I also found the one on the web site wouldn't
> boot but would very much like to have a copy that would work for 2.4.18. Where might I find
> this?

Ingos' irqbalance-2.4.17-B1.patch applies cleanly to 2.4.18. This and the 
timer-irq-balance-2.4.18.patch are attached.  Also attached is a 2
line patch to identify the CPUs on boot, instead of getting unknown cpu
errors (cosmetic only).

These are currently running on a system with hyper threading
turned on, for the past 2 days or so and it seems stable.  

Regards
James


> 
> Ragards
> Mark
> -
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 

-- 
James Bourne, Supervisor Data Centre Operations
Mount Royal College, Calgary, AB, CA
www.mtroyal.ab.ca

******************************************************************************
This communication is intended for the use of the recipient to which it is
addressed, and may contain confidential, personal, and or privileged
information. Please contact the sender immediately if you are not the
intended recipient of this communication, and do not copy, distribute, or
take action relying on it. Any communication received in error, or
subsequent reply, should be deleted or destroyed.
******************************************************************************

[-- Attachment #2: irq balance patch --]
[-- Type: TEXT/PLAIN, Size: 4898 bytes --]

--- linux/kernel/sched.c.orig	Tue Feb  5 13:11:35 2002
+++ linux/kernel/sched.c	Tue Feb  5 13:12:48 2002
@@ -118,6 +118,11 @@
 #define can_schedule(p,cpu) \
 	((p)->cpus_runnable & (p)->cpus_allowed & (1 << cpu))
 
+int idle_cpu(int cpu)
+{
+	return cpu_curr(cpu) == idle_task(cpu);
+}
+
 #else
 
 #define idle_task(cpu) (&init_task)
--- linux/include/linux/sched.h.orig	Tue Feb  5 13:13:09 2002
+++ linux/include/linux/sched.h	Tue Feb  5 13:14:00 2002
@@ -144,6 +144,7 @@
 
 extern void sched_init(void);
 extern void init_idle(void);
+extern int idle_cpu(int cpu);
 extern void show_state(void);
 extern void cpu_init (void);
 extern void trap_init(void);
--- linux/include/asm-i386/hardirq.h.orig	Tue Feb  5 13:10:39 2002
+++ linux/include/asm-i386/hardirq.h	Tue Feb  5 13:14:00 2002
@@ -12,6 +12,7 @@
 	unsigned int __local_bh_count;
 	unsigned int __syscall_count;
 	struct task_struct * __ksoftirqd_task; /* waitqueue is too large */
+	unsigned long idle_timestamp;
 	unsigned int __nmi_count;	/* arch dependent */
 } ____cacheline_aligned irq_cpustat_t;
 
--- linux/arch/i386/kernel/io_apic.c.orig	Tue Feb  5 13:10:37 2002
+++ linux/arch/i386/kernel/io_apic.c	Tue Feb  5 13:15:23 2002
@@ -28,6 +28,7 @@
 #include <linux/config.h>
 #include <linux/smp_lock.h>
 #include <linux/mc146818rtc.h>
+#include <linux/compiler.h>
 
 #include <asm/io.h>
 #include <asm/smp.h>
@@ -163,6 +164,86 @@
 			clear_IO_APIC_pin(apic, pin);
 }
 
+static void set_ioapic_affinity (unsigned int irq, unsigned long mask)
+{
+	unsigned long flags;
+
+	/*
+	 * Only the first 8 bits are valid.
+	 */
+	mask = mask << 24;
+	spin_lock_irqsave(&ioapic_lock, flags);
+	__DO_ACTION(1, = mask, )
+	spin_unlock_irqrestore(&ioapic_lock, flags);
+}
+
+#if CONFIG_SMP
+
+typedef struct {
+	unsigned int cpu;
+	unsigned long timestamp;
+} ____cacheline_aligned irq_balance_t;
+
+static irq_balance_t irq_balance[NR_IRQS] __cacheline_aligned
+			= { [ 0 ... NR_IRQS-1 ] = { 1, 0 } };
+
+extern unsigned long irq_affinity [NR_IRQS];
+
+#endif
+
+#define IDLE_ENOUGH(cpu,now) \
+		(idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
+
+#define IRQ_ALLOWED(cpu,allowed_mask) \
+		((1 << cpu) & (allowed_mask))
+
+static unsigned long move(int curr_cpu, unsigned long allowed_mask, unsigned long now, int direction)
+{
+	int search_idle = 1;
+	int cpu = curr_cpu;
+
+	goto inside;
+
+	do {
+		if (unlikely(cpu == curr_cpu))
+			search_idle = 0;
+inside:
+		if (direction == 1) {
+			cpu++;
+			if (cpu >= smp_num_cpus)
+				cpu = 0;
+		} else {
+			cpu--;
+			if (cpu == -1)
+				cpu = smp_num_cpus-1;
+		}
+	} while (!IRQ_ALLOWED(cpu,allowed_mask) ||
+			(search_idle && !IDLE_ENOUGH(cpu,now)));
+
+	return cpu;
+}
+
+static inline void balance_irq(int irq)
+{
+#if CONFIG_SMP
+	irq_balance_t *entry = irq_balance + irq;
+	unsigned long now = jiffies;
+
+	if (unlikely(entry->timestamp != now)) {
+		unsigned long allowed_mask;
+		int random_number;
+
+		rdtscl(random_number);
+		random_number &= 1;
+
+		allowed_mask = cpu_online_map & irq_affinity[irq];
+		entry->timestamp = now;
+		entry->cpu = move(entry->cpu, allowed_mask, now, random_number);
+		set_ioapic_affinity(irq, 1 << entry->cpu);
+	}
+#endif
+}
+
 /*
  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
  * specific CPU-side IRQs.
@@ -653,8 +734,7 @@
 }
 
 /*
- * Set up the 8259A-master output pin as broadcast to all
- * CPUs.
+ * Set up the 8259A-master output pin:
  */
 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 {
@@ -1174,6 +1254,7 @@
  */
 static void ack_edge_ioapic_irq(unsigned int irq)
 {
+	balance_irq(irq);
 	if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
 					== (IRQ_PENDING | IRQ_DISABLED))
 		mask_IO_APIC_irq(irq);
@@ -1213,6 +1294,7 @@
 	unsigned long v;
 	int i;
 
+	balance_irq(irq);
 /*
  * It appears there is an erratum which affects at least version 0x11
  * of I/O APIC (that's the 82093AA and cores integrated into various
@@ -1268,19 +1350,6 @@
 }
 
 static void mask_and_ack_level_ioapic_irq (unsigned int irq) { /* nothing */ }
-
-static void set_ioapic_affinity (unsigned int irq, unsigned long mask)
-{
-	unsigned long flags;
-	/*
-	 * Only the first 8 bits are valid.
-	 */
-	mask = mask << 24;
-
-	spin_lock_irqsave(&ioapic_lock, flags);
-	__DO_ACTION(1, = mask, )
-	spin_unlock_irqrestore(&ioapic_lock, flags);
-}
 
 /*
  * Level and edge triggered IO-APIC interrupts need different handling,
--- linux/arch/i386/kernel/irq.c.orig	Tue Feb  5 13:10:34 2002
+++ linux/arch/i386/kernel/irq.c	Tue Feb  5 13:11:15 2002
@@ -1076,7 +1076,7 @@
 
 static struct proc_dir_entry * smp_affinity_entry [NR_IRQS];
 
-static unsigned long irq_affinity [NR_IRQS] = { [0 ... NR_IRQS-1] = ~0UL };
+unsigned long irq_affinity [NR_IRQS] = { [0 ... NR_IRQS-1] = ~0UL };
 static int irq_affinity_read_proc (char *page, char **start, off_t off,
 			int count, int *eof, void *data)
 {

[-- Attachment #3: timer balance patch --]
[-- Type: TEXT/PLAIN, Size: 1610 bytes --]

diff -up --recursive --new-file linux-2.4.18.macro/arch/i386/kernel/io_apic.c linux-2.4.18/arch/i386/kernel/io_apic.c
--- linux-2.4.18.macro/arch/i386/kernel/io_apic.c	Fri Nov 23 15:32:04 2001
+++ linux-2.4.18/arch/i386/kernel/io_apic.c	Fri Mar  1 14:58:20 2002
@@ -67,7 +67,7 @@ static struct irq_pin_list {
  * shared ISA-space IRQs, so we have to support them. We are super
  * fast in the common case, and fast for shared ISA-space IRQs.
  */
-static void add_pin_to_irq(unsigned int irq, int apic, int pin)
+static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
 {
 	static int first_free_entry = NR_IRQS;
 	struct irq_pin_list *entry = irq_2_pin + irq;
@@ -85,6 +85,26 @@ static void add_pin_to_irq(unsigned int 
 	entry->pin = pin;
 }
 
+/*
+ * Reroute an IRQ to a different pin.
+ */
+static void __init replace_pin_at_irq(unsigned int irq,
+				      int oldapic, int oldpin,
+				      int newapic, int newpin)
+{
+	struct irq_pin_list *entry = irq_2_pin + irq;
+
+	while (1) {
+		if (entry->apic == oldapic && entry->pin == oldpin) {
+			entry->apic = newapic;
+			entry->pin = newpin;
+		}
+		if (!entry->next)
+			break;
+		entry = irq_2_pin + entry->next;
+	}
+}
+
 #define __DO_ACTION(R, ACTION, FINAL)					\
 									\
 {									\
@@ -1533,6 +1553,10 @@ static inline void check_timer(void)
 		setup_ExtINT_IRQ0_pin(pin2, vector);
 		if (timer_irq_works()) {
 			printk("works.\n");
+			if (pin1 != -1)
+				replace_pin_at_irq(0, 0, pin1, 0, pin2);
+			else
+				add_pin_to_irq(0, 0, pin2);
 			if (nmi_watchdog == NMI_IO_APIC) {
 				setup_nmi();
 				check_nmi_watchdog();

[-- Attachment #4: ident patch --]
[-- Type: TEXT/PLAIN, Size: 350 bytes --]

--- linux-2.4.18/arch/i386/kernel/mpparse.c~	Fri Nov  9 15:58:18 2001
+++ linux-2.4.18/arch/i386/kernel/mpparse.c	Wed Apr 17 12:57:08 2002
@@ -113,6 +113,8 @@
 		case 0x0F:
 			if (model == 0x00)
 				return("Pentium 4(tm)");
+			if (model == 0x02)
+				return("Pentium 4(tm) XEON(tm)");
 			if (model == 0x0F)
 				return("Special controller");
 	}