From: Dave Engebretsen <engebret@vnet.ibm.com>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: linux-kernel@vger.kernel.org
Subject: Re: Memory Barrier Definitions
Date: Tue, 07 May 2002 16:23:28 -0500 [thread overview]
Message-ID: <3CD845D0.ACB6BB2B@vnet.ibm.com> (raw)
In-Reply-To: <3CD830BE.CAB7FA96@vnet.ibm.com> <E175BY8-0008S4-00@the-village.bc.nu>
Alan Cox wrote:
>
> > forms of processor memory barrier instructions. It is _very_ expensive
> I think I follow
>
> You have
>
> Compiler ordering
> CPU v CPU memory ordering
> CPU v I/O memory ordering
> I/O v I/O memory ordering
>
Yep, that is a good summary. And the problem arises from the very large
penalty for the syncronization form used for CPU v I/O ordering. You
only want to pay that when necessary, certainly not when only CPU v CPU
ordering is required. The difference can be on the order of a 1000
cycles (depending on many factors, of course).
Dave.
next prev parent reply other threads:[~2002-05-07 21:24 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-05-07 19:07 Memory Barrier Definitions Dave Engebretsen
2002-05-07 19:49 ` Alan Cox
2002-05-07 19:53 ` Dave Engebretsen
2002-05-07 20:27 ` Alan Cox
2002-05-07 21:23 ` Dave Engebretsen [this message]
2002-05-07 22:15 ` justincarlson
2002-05-08 2:49 ` Dave Engebretsen
2002-05-08 13:54 ` Justin Carlson
2002-05-08 15:27 ` Dave Engebretsen
2002-05-08 15:49 ` Andi Kleen
2002-05-08 17:07 ` David Mosberger
2002-05-09 7:36 ` Rusty Russell
2002-05-09 8:01 ` Keith Owens
2002-05-09 15:00 ` David Mosberger
2002-05-13 3:26 ` Rusty Russell
2002-05-13 16:36 ` David Mosberger
2002-05-13 16:50 ` Linus Torvalds
2002-05-13 17:53 ` David Mosberger
2002-05-13 23:28 ` Rusty Russell
2002-05-07 22:57 ` Anton Blanchard
2002-05-13 18:16 ` Jesse Barnes
-- strict thread matches above, loose matches on Subject: below --
2002-05-09 11:33 Manfred Spraul
2002-05-09 19:38 ` Dave Engebretsen
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