From: Ralph Blach <rblach@intrex.net>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: Todd Poynor <tpoynor@mvista.com>, linuxppc-embedded@lists.linuxppc.org
Subject: Re: very minor 405GP and 405GPr PCI difference
Date: Thu, 24 Oct 2002 19:50:33 -0400 [thread overview]
Message-ID: <3DB88749.3020209@intrex.net> (raw)
In-Reply-To: 20021 <20021023040850.GC1198@zax
David,
Let me expain
On the 405gp, the PMM0 enable is hardwired 1 and cannot be overwritten
by software. This makes the PMM0 region permantly enabled on the
405GP. I cannot be turned off.
When the technology port was done, the design of the PCI was changed
slightly because the designer made the PMM0 enable bit writable. It is
still initalized to a 1, but it can written to a 0.
In the current software, the initialization software writes a 0 to PMM0
and to PMM1. This was fine on the 405gp because the enable bit for PMM0
could not be changed. On the 405GPr this disabled PMM0 and with PMM1
disabled, bad things happened.
The initialization software simply need to write a 1 to the PMM0 enable
bit and all will be well.
Chip
David Gibson wrote:
> On Tue, Oct 22, 2002 at 02:55:47PM -0700, Todd Poynor wrote:
>
>>David Gibson wrote (regarding Rainier PMM1 bios_fixup in MVL):
>>
>>
>>>Well, it may be in a different place, but it looks like it has the
>>>same problem. It is still establishing a PCI window at PLB address
>>>0x80000000, which is the same address used for the PMM0 window - or is
>>>that also different in the MV kernel?
>>>
>>>I'd be trying to work out what that mapping's actually for, first. I
>>>still can't see how it can possibly work - if there are overlapping
>>>PMM windows, what actually happens to accesses in that (PLB) range?
>>
>>Yes, it looks like MVL only sets up the one window using PMM1... we've
>>started an effort to have the Rainier-knowedgeable folks get the code
>>sync'ed up with the community and this should happen soon.
>
>
> Hang on, so just to clarify - MVL sets up PMM1 with the code you
> posted, but doesn't set up PMM0 anywhere? From my reading of that
> code, it sets up a window at the same address as the "standard"
> (Walnut) mapping, except that it is only 128kB instead of 1GB. Is
> there a reason that Rainier must have such a small window?
>
> --
> David Gibson | For every complex problem there is a
> david@gibson.dropbear.id.au | solution which is simple, neat and
> | wrong.
> http://www.ozlabs.org/people/dgibson
>
>
>
> .
>
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2002-10-24 23:50 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-09-27 12:27 very minor 405GP and 405GPr PCI difference Ralph Blach
2002-09-30 4:01 ` David Gibson
2002-10-01 5:21 ` David Gibson
2002-10-01 8:37 ` "David Müller (ELSOFT AG)"
2002-10-02 1:42 ` David Gibson
2002-10-02 4:26 ` Allen Curtis
2002-10-02 5:34 ` David Gibson
2002-10-02 17:03 ` Matt Porter
2002-10-03 1:10 ` David Gibson
2002-10-03 15:14 ` Matt Porter
2002-10-04 2:48 ` David Gibson
2002-10-04 18:33 ` Todd Poynor
2002-10-08 4:17 ` David Gibson
2002-10-08 19:39 ` Todd Poynor
2002-10-09 2:14 ` David Gibson
[not found] ` <20021 <20021023040850.GC1198@zax>
2002-10-24 23:50 ` Ralph Blach [this message]
2002-10-25 1:19 ` David Gibson
2002-10-02 7:46 ` "David Müller (ELSOFT AG)"
2002-10-03 1:12 ` David Gibson
2002-10-03 8:28 ` "David Müller (ELSOFT AG)"
2002-10-06 5:23 ` Andrew May
2002-10-07 1:31 ` Matt Porter
2002-10-08 4:14 ` David Gibson
2002-10-08 5:21 ` Andrew May
2002-10-08 14:56 ` Matt Porter
2002-10-08 17:31 ` Andrew May
2002-10-08 18:20 ` Matt Porter
2002-10-09 1:58 ` David Gibson
2002-10-09 10:35 ` Kenneth Johansson
2002-10-09 15:21 ` Allen Curtis
2002-10-11 19:37 ` Andrew May
2002-10-14 1:20 ` David Gibson
2002-10-08 6:19 ` Allen Curtis
2002-10-08 15:18 ` Matt Porter
2002-10-09 2:10 ` David Gibson
2002-10-22 21:55 ` Todd Poynor
2002-10-23 4:08 ` David Gibson
-- strict thread matches above, loose matches on Subject: below --
2002-10-23 13:10 Ralph Blach
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