* [parisc-linux] Affined IRQs. @ 2003-08-11 6:54 Naresh 2003-08-11 7:43 ` Thibaut VARENE 0 siblings, 1 reply; 7+ messages in thread From: Naresh @ 2003-08-11 6:54 UTC (permalink / raw) To: parisc-linux@lists.parisc-linux.org Hi, The IA-64 Linux kernel has a concept of affined IRQs, wherein IRQs can be bound/affined to particular CPUs. The affinity information shows up in '/proc/irq/#/smp_affinity'. I cannot see any affinity of IRQs to CPUs in PA ( iosapic.c and irq.c).. Is my understanding correct? Regards, Naresh. ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [parisc-linux] Affined IRQs. 2003-08-11 6:54 [parisc-linux] Affined IRQs Naresh @ 2003-08-11 7:43 ` Thibaut VARENE 2003-08-11 12:33 ` Naresh 0 siblings, 1 reply; 7+ messages in thread From: Thibaut VARENE @ 2003-08-11 7:43 UTC (permalink / raw) To: knaresh; +Cc: parisc-linux@lists.parisc-linux.org On Mon, 11 Aug 2003 12:24:10 +0530 Naresh <knaresh@india.hp.com> wrote: > Hi, > The IA-64 Linux kernel has a concept of affined IRQs, wherein IRQs can > be bound/affined to particular CPUs. The affinity information shows up > in '/proc/irq/#/smp_affinity'. I cannot see any affinity of IRQs to CPUs > in PA ( iosapic.c and irq.c).. Is my understanding correct? > Regards, > Naresh. This has to be implemented for parisc and is on my todo list ;) (BTW, on vacation till Aug 25th.) Thibaut VARENE The PA/Linux ESIEE Team http://pateam.esiee.fr/ ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [parisc-linux] Affined IRQs. 2003-08-11 7:43 ` Thibaut VARENE @ 2003-08-11 12:33 ` Naresh 2003-08-11 13:44 ` Thibaut VARÈNE 2003-08-11 15:44 ` Grant Grundler 0 siblings, 2 replies; 7+ messages in thread From: Naresh @ 2003-08-11 12:33 UTC (permalink / raw) To: Thibaut VARENE; +Cc: parisc-linux@lists.parisc-linux.org A couple of questions: 1. Do does this mean interrupts can go to any CPU? 2. If a CPU on an SMP system is stopped or its interrupts are blocked, will its interrupts automatically be serviced on another online CPU, due to their non-affining nature? Regards, Naresh. Thibaut VARENE wrote: > > Hi, > > The IA-64 Linux kernel has a concept of affined IRQs, wherein IRQs can > > be bound/affined to particular CPUs. The affinity information shows up > > in '/proc/irq/#/smp_affinity'. I cannot see any affinity of IRQs to CPUs > > in PA ( iosapic.c and irq.c).. Is my understanding correct? > > Regards, > > Naresh. > > This has to be implemented for parisc and is on my todo list ;) > > (BTW, on vacation till Aug 25th.) > > Thibaut VARENE > The PA/Linux ESIEE Team > http://pateam.esiee.fr/ > _______________________________________________ > parisc-linux mailing list > parisc-linux@lists.parisc-linux.org > http://lists.parisc-linux.org/mailman/listinfo/parisc-linux ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [parisc-linux] Affined IRQs. 2003-08-11 12:33 ` Naresh @ 2003-08-11 13:44 ` Thibaut VARÈNE 2003-08-11 16:00 ` Grant Grundler 2003-08-11 15:44 ` Grant Grundler 1 sibling, 1 reply; 7+ messages in thread From: Thibaut VARÈNE @ 2003-08-11 13:44 UTC (permalink / raw) To: knaresh; +Cc: parisc-linux@lists.parisc-linux.org Le lundi, 11 ao=FB 2003, =E0 14:33 Europe/Paris, Naresh a =E9crit : > A couple of questions: > 1. Do does this mean interrupts can go to any CPU? there are several cases, depending on the hardware. For instance, on A500, IRQs are distributed to both CPUs, on J5000,=20 only one of the two CPUs gets all IRQs. This is IOSAPIC programmation that has to be reviewed: on J5000: [varenet@k2000 ~]$ uname -a Linux k2000 2.4.20-pa18 #1 SMP Sun Jan 12 02:41:51 CET 2003 parisc64=20 GNU/Linux [varenet@k2000 ~]$ cat /proc/interrupts CPU00 CPU01 64: 1053803311 1053803113 PARISC-CPU timer 65: 2598316 12633504 PARISC-CPU IPI 66: 68320843 0 PARISC-CPU IO-SAPIC00-L2 67: 0 0 PARISC-CPU IO-SAPIC00-L3 68: 326 0 PARISC-CPU IO-SAPIC00-L0 69: 0 0 PARISC-CPU IO-SAPIC00-L1 70: 6616979 0 PARISC-CPU IO-SAPIC00-L1 128: 326 0 IO-SAPIC00 SuperIO 129: 6616979 0 IO-SAPIC00 sym53c8xx, sym53c8xx 130: 68320843 0 IO-SAPIC00 eth0 195: 323 0 SuperIO serial 199: 3 0 SuperIO ide0 on A500: [varenet@mkhppa3 ~]$ uname -a Linux mkhppa3 2.4.20-pa28 #1 SMP Sun Mar 9 23:56:53 CET 2003 parisc64=20 GNU/Linux [varenet@mkhppa3 ~]$ cat /proc/interrupts CPU00 CPU01 64: 727337429 727336565 PARISC-CPU timer 65: 31826972 39174091 PARISC-CPU IPI 66: 42581516 0 PARISC-CPU IO-SAPIC00-L0 67: 0 30 PARISC-CPU IO-SAPIC00-L1 68: 0 0 PARISC-CPU IO-SAPIC00-L2 69: 0 696338 PARISC-CPU IO-SAPIC00-L2 70: 3672511 0 PARISC-CPU IO-SAPIC00-L3 71: 0 209 PARISC-CPU IO-SAPIC00-L4 72: 0 0 PARISC-CPU IO-SAPIC00-L5 128: 42581516 0 IO-SAPIC00 eth0 129: 0 30 IO-SAPIC00 sym53c8xx 130: 0 696338 IO-SAPIC00 sym53c8xx, sym53c8xx 131: 3672511 0 IO-SAPIC00 sym53c8xx 132: 0 209 IO-SAPIC00 serial > 2. If a CPU on an SMP system is stopped or its interrupts are blocked,=20= > will > its interrupts automatically be serviced on another online CPU, due to=20= > their > non-affining nature? CPU deconfiguration is also on my todo list ;) So you can't stop a CPU on a PARISC SMP system atm. the second part of the question is an iodood (Grant Grundler ;)=20 question, but to my understanding IRQs won't probably be serviced by=20 another CPU unless the IOSAPIC is reprogrammed to do so. HTH, Thibaut VARENE The PA/Linux ESIEE Team http://pateam.esiee.fr/ > Regards, > Naresh. > > Thibaut VARENE wrote: > >>> Hi, >>> The IA-64 Linux kernel has a concept of affined IRQs, wherein IRQs=20= >>> can >>> be bound/affined to particular CPUs. The affinity information shows=20= >>> up >>> in '/proc/irq/#/smp_affinity'. I cannot see any affinity of IRQs to=20= >>> CPUs >>> in PA ( iosapic.c and irq.c).. Is my understanding correct? >>> Regards, >>> Naresh. >> >> This has to be implemented for parisc and is on my todo list ;) >> >> (BTW, on vacation till Aug 25th.) >> >> Thibaut VARENE >> The PA/Linux ESIEE Team >> http://pateam.esiee.fr/ >> _______________________________________________ >> parisc-linux mailing list >> parisc-linux@lists.parisc-linux.org >> http://lists.parisc-linux.org/mailman/listinfo/parisc-linux > > > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [parisc-linux] Affined IRQs. 2003-08-11 13:44 ` Thibaut VARÈNE @ 2003-08-11 16:00 ` Grant Grundler 0 siblings, 0 replies; 7+ messages in thread From: Grant Grundler @ 2003-08-11 16:00 UTC (permalink / raw) To: Thibaut VAR?NE; +Cc: knaresh, parisc-linux@lists.parisc-linux.org On Mon, Aug 11, 2003 at 03:44:02PM +0200, Thibaut VAR?NE wrote: > For instance, on A500, IRQs are distributed to both CPUs, on J5000, > only one of the two CPUs gets all IRQs. I'm pretty sure this is a bug in the j5000 (Legacy PDC) init sequence. Not a limitation of the j5000 HW. > but to my understanding IRQs won't probably be serviced by > another CPU unless the IOSAPIC is reprogrammed to do so. correct. grant ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [parisc-linux] Affined IRQs. 2003-08-11 12:33 ` Naresh 2003-08-11 13:44 ` Thibaut VARÈNE @ 2003-08-11 15:44 ` Grant Grundler 2003-08-11 15:49 ` Matthew Wilcox 1 sibling, 1 reply; 7+ messages in thread From: Grant Grundler @ 2003-08-11 15:44 UTC (permalink / raw) To: Naresh; +Cc: Thibaut VARENE, parisc-linux@lists.parisc-linux.org On Mon, Aug 11, 2003 at 06:03:03PM +0530, Naresh wrote: > A couple of questions: > 1. Do does this mean interrupts can go to any CPU? Interrupts can be direct at any one CPU. ia64 and parisc IPI use the same method as IO devices. The code does a round-robin when assigning IO interrupts to CPUs. ie assign interrupts to a sequential order of the CPUs. A minor improvement would be to round-robin based on device class. But I want this intelligence in user space, not the kernel. NUMA machines want interrupts directed at CPUs in the same node where the IO is "hosted". > 2. If a CPU on an SMP system is stopped or its interrupts are blocked, > will its interrupts automatically be serviced on another online CPU, no. The interrupt must be "manually" redirected to another CPU. > due to their non-affining nature? Not sure what you mean here. grant > Regards, > Naresh. > > Thibaut VARENE wrote: > > > > Hi, > > > The IA-64 Linux kernel has a concept of affined IRQs, wherein IRQs can > > > be bound/affined to particular CPUs. The affinity information shows up > > > in '/proc/irq/#/smp_affinity'. I cannot see any affinity of IRQs to CPUs > > > in PA ( iosapic.c and irq.c).. Is my understanding correct? > > > Regards, > > > Naresh. > > > > This has to be implemented for parisc and is on my todo list ;) > > > > (BTW, on vacation till Aug 25th.) > > > > Thibaut VARENE > > The PA/Linux ESIEE Team > > http://pateam.esiee.fr/ > > _______________________________________________ > > parisc-linux mailing list > > parisc-linux@lists.parisc-linux.org > > http://lists.parisc-linux.org/mailman/listinfo/parisc-linux > > _______________________________________________ > parisc-linux mailing list > parisc-linux@lists.parisc-linux.org > http://lists.parisc-linux.org/mailman/listinfo/parisc-linux ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [parisc-linux] Affined IRQs. 2003-08-11 15:44 ` Grant Grundler @ 2003-08-11 15:49 ` Matthew Wilcox 0 siblings, 0 replies; 7+ messages in thread From: Matthew Wilcox @ 2003-08-11 15:49 UTC (permalink / raw) To: Grant Grundler Cc: Naresh, Thibaut VARENE, parisc-linux@lists.parisc-linux.org On Mon, Aug 11, 2003 at 09:44:49AM -0600, Grant Grundler wrote: > Interrupts can be direct at any one CPU. > ia64 and parisc IPI use the same method as IO devices. > > The code does a round-robin when assigning IO interrupts to CPUs. > ie assign interrupts to a sequential order of the CPUs. > > A minor improvement would be to round-robin based on device class. > But I want this intelligence in user space, not the kernel. > NUMA machines want interrupts directed at CPUs in the same node > where the IO is "hosted". > > > 2. If a CPU on an SMP system is stopped or its interrupts are blocked, > > will its interrupts automatically be serviced on another online CPU, > > no. The interrupt must be "manually" redirected to another CPU. > > > due to their non-affining nature? > > Not sure what you mean here. I think there's some confusion here. I would say that interrupts on PA-RISC are strongly CPU-affine, but there is currently no mechanism for controlling that affinity. One interrupt will always go to the CPU it's been programmed for. -- "It's not Hollywood. War is real, war is primarily not about defeat or victory, it is about death. I've seen thousands and thousands of dead bodies. Do you think I want to have an academic debate on this subject?" -- Robert Fisk ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2003-08-11 16:00 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2003-08-11 6:54 [parisc-linux] Affined IRQs Naresh 2003-08-11 7:43 ` Thibaut VARENE 2003-08-11 12:33 ` Naresh 2003-08-11 13:44 ` Thibaut VARÈNE 2003-08-11 16:00 ` Grant Grundler 2003-08-11 15:44 ` Grant Grundler 2003-08-11 15:49 ` Matthew Wilcox
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