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From: Kevin Cernekee <cernekee@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH RESEND 5/7] MIPS: Install handlers for BMIPS software IRQs
Date: Tue, 23 Nov 2010 10:26:43 -0800	[thread overview]
Message-ID: <3adc7e6dd933a5bc8295e7bb687f2907@localhost> (raw)
In-Reply-To: <8a8eee995454c8b271cceb440e31699a@localhost>

BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
signaling.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/kernel/irq_cpu.c |   14 ++++++--------
 1 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0262abe..70d4736 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -107,14 +107,12 @@ void __init mips_cpu_irq_init(void)
 	clear_c0_status(ST0_IM);
 	clear_c0_cause(CAUSEF_IP);
 
-	/*
-	 * Only MT is using the software interrupts currently, so we just
-	 * leave them uninitialized for other processors.
-	 */
-	if (cpu_has_mipsmt)
-		for (i = irq_base; i < irq_base + 2; i++)
-			set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
-						 handle_percpu_irq);
+	/* Software interrupts are used for MT/CMT IPI */
+	for (i = irq_base; i < irq_base + 2; i++)
+		set_irq_chip_and_handler(i, cpu_has_mipsmt ?
+					 &mips_mt_cpu_irq_controller :
+					 &mips_cpu_irq_controller,
+					 handle_percpu_irq);
 
 	for (i = irq_base + 2; i < irq_base + 8; i++)
 		set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
-- 
1.7.0.4

WARNING: multiple messages have this Message-ID (diff)
From: Kevin Cernekee <cernekee@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: [PATCH RESEND 5/7] MIPS: Install handlers for BMIPS software IRQs
Date: Tue, 23 Nov 2010 10:26:43 -0800	[thread overview]
Message-ID: <3adc7e6dd933a5bc8295e7bb687f2907@localhost> (raw)
Message-ID: <20101123182643.oBCKOSClBRz7PzLsJESymi1Ylr_S9mPneBAH_xUwPLI@z> (raw)
In-Reply-To: <8a8eee995454c8b271cceb440e31699a@localhost>

BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
signaling.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/kernel/irq_cpu.c |   14 ++++++--------
 1 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0262abe..70d4736 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -107,14 +107,12 @@ void __init mips_cpu_irq_init(void)
 	clear_c0_status(ST0_IM);
 	clear_c0_cause(CAUSEF_IP);
 
-	/*
-	 * Only MT is using the software interrupts currently, so we just
-	 * leave them uninitialized for other processors.
-	 */
-	if (cpu_has_mipsmt)
-		for (i = irq_base; i < irq_base + 2; i++)
-			set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
-						 handle_percpu_irq);
+	/* Software interrupts are used for MT/CMT IPI */
+	for (i = irq_base; i < irq_base + 2; i++)
+		set_irq_chip_and_handler(i, cpu_has_mipsmt ?
+					 &mips_mt_cpu_irq_controller :
+					 &mips_cpu_irq_controller,
+					 handle_percpu_irq);
 
 	for (i = irq_base + 2; i < irq_base + 8; i++)
 		set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
-- 
1.7.0.4

  parent reply	other threads:[~2010-11-23 18:35 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-11-23 18:26 [PATCH RESEND 1/7] MIPS: sync after cacheflush Kevin Cernekee
2010-11-23 18:26 ` Kevin Cernekee
2010-11-23 18:26 ` [PATCH RESEND 2/7] MIPS: pfn_valid() is broken on low memory HIGHMEM systems Kevin Cernekee
2010-11-23 18:26   ` Kevin Cernekee
2010-11-23 18:26 ` [PATCH v2 RESEND 3/7] MIPS: Move FIXADDR_TOP into spaces.h Kevin Cernekee
2010-11-23 18:26   ` Kevin Cernekee
2010-11-23 18:26 ` [PATCH v4 RESEND 4/7] MIPS: HIGHMEM DMA on noncoherent MIPS32 processors Kevin Cernekee
2010-11-23 18:26   ` Kevin Cernekee
2010-11-23 18:26 ` Kevin Cernekee [this message]
2010-11-23 18:26   ` [PATCH RESEND 5/7] MIPS: Install handlers for BMIPS software IRQs Kevin Cernekee
2010-11-23 18:26 ` [PATCH 6/7] MIPS: Fix CP0 COUNTER clockevent race Kevin Cernekee
2010-11-23 18:26   ` Kevin Cernekee
2010-11-24 11:34   ` Ralf Baechle
2010-11-23 18:26 ` [PATCH 7/7] MIPS: Fix regression on BCM4710 processor detection Kevin Cernekee
2010-11-23 18:26   ` Kevin Cernekee
2010-11-24 11:34   ` Ralf Baechle

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