From: "Das, Nirmoy" <nirmoy.das@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH v2 14/30] drm/xe: Clarify 'gt' retrieval for primary tile
Date: Mon, 22 May 2023 13:47:04 +0200 [thread overview]
Message-ID: <3bcd4b89-2f28-950f-cb13-7ef624b701fa@linux.intel.com> (raw)
In-Reply-To: <20230519231827.3572452-15-matthew.d.roper@intel.com>
On 5/20/2023 1:18 AM, Matt Roper wrote:
> There are a bunch of places in the driver where we need to perform
> non-GT MMIO against the platform's primary tile (display code, top-level
> interrupt enable/disable, driver initialization, etc.). Rename
> 'to_gt()' to 'xe_primary_mmio_gt()' to clarify that we're trying to get
> a primary MMIO handle for these top-level operations.
>
> In the future we need to move away from xe_gt as the target for MMIO
> operations (most of which are completely unrelated to GT).
>
> v2:
> - s/xe_primary_mmio_gt/xe_root_mmio_gt/ for more consistency with how
> we refer to tile 0. (Lucas)
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h | 2 +-
> drivers/gpu/drm/xe/xe_device.c | 2 +-
> drivers/gpu/drm/xe/xe_device.h | 11 +++++++++--
> drivers/gpu/drm/xe/xe_irq.c | 6 +++---
> drivers/gpu/drm/xe/xe_mmio.c | 8 ++++----
> drivers/gpu/drm/xe/xe_query.c | 2 +-
> drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 4 ++--
> 7 files changed, 21 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> index 14f195fe275d..fae6213d26f1 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> @@ -14,7 +14,7 @@ static inline struct xe_gt *__fake_uncore_to_gt(struct fake_uncore *uncore)
> {
> struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
>
> - return to_gt(xe);
> + return xe_root_mmio_gt(xe);
> }
>
> static inline u32 intel_uncore_read(struct fake_uncore *uncore,
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index af165ad6f197..43a585b67581 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -394,7 +394,7 @@ static void device_kill_persistent_engines(struct xe_device *xe,
>
> void xe_device_wmb(struct xe_device *xe)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
>
> wmb();
> if (IS_DGFX(xe))
> diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
> index 745dbb16d417..42bc566c53d8 100644
> --- a/drivers/gpu/drm/xe/xe_device.h
> +++ b/drivers/gpu/drm/xe/xe_device.h
> @@ -66,9 +66,16 @@ static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
> }
>
> /*
> - * FIXME: Placeholder until multi-gt lands. Once that lands, kill this function.
> + * Provide a GT structure suitable for performing non-GT MMIO operations against
> + * the primary tile. Primarily intended for early tile initialization, display
> + * handling, top-most interrupt enable/disable, etc. Since anything using the
> + * MMIO handle returned by this function doesn't need GSI offset translation,
> + * we'll return the primary GT from the root tile.
> + *
> + * FIXME: Fix the driver design so that 'gt' isn't the target of all MMIO
> + * operations.
> */
> -static inline struct xe_gt *to_gt(struct xe_device *xe)
> +static inline struct xe_gt *xe_root_mmio_gt(struct xe_device *xe)
> {
> return &xe_device_get_root_tile(xe)->primary_gt;
> }
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 5be31855d789..628057497cd5 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -285,7 +285,7 @@ static void gt_irq_handler(struct xe_device *xe, struct xe_gt *gt,
> static irqreturn_t xelp_irq_handler(int irq, void *arg)
> {
> struct xe_device *xe = arg;
> - struct xe_gt *gt = xe_device_get_gt(xe, 0); /* Only 1 GT here */
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> u32 master_ctl, gu_misc_iir;
> long unsigned int intr_dw[2];
> u32 identity[32];
> @@ -311,7 +311,7 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
>
> static u32 dg1_intr_disable(struct xe_device *xe)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> u32 val;
>
> /* First disable interrupts */
> @@ -329,7 +329,7 @@ static u32 dg1_intr_disable(struct xe_device *xe)
>
> static void dg1_intr_enable(struct xe_device *xe, bool stall)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
>
> xe_mmio_write32(gt, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
> if (stall)
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 17b3a9880409..32427c10ba8a 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -150,7 +150,7 @@ static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
>
> int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_size)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> int err;
> u32 reg_val;
> @@ -287,7 +287,7 @@ int xe_mmio_probe_vram(struct xe_device *xe)
>
> static void xe_mmio_probe_tiles(struct xe_device *xe)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> u32 mtcfg;
> u8 adj_tile_count;
> u8 id;
> @@ -339,7 +339,7 @@ static void mmio_fini(struct drm_device *drm, void *arg)
> int xe_mmio_init(struct xe_device *xe)
> {
> struct xe_tile *root_tile = xe_device_get_root_tile(xe);
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> const int mmio_bar = 0;
> int err;
>
> @@ -398,7 +398,7 @@ int xe_mmio_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> struct xe_device *xe = to_xe_device(dev);
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> struct drm_xe_mmio *args = data;
> unsigned int bits_flag, bytes;
> struct xe_reg reg;
> diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
> index c81652d7f4ec..49fff425adcd 100644
> --- a/drivers/gpu/drm/xe/xe_query.c
> +++ b/drivers/gpu/drm/xe/xe_query.c
> @@ -259,7 +259,7 @@ static int query_gts(struct xe_device *xe, struct drm_xe_device_query *query)
> static int query_hwconfig(struct xe_device *xe,
> struct drm_xe_device_query *query)
> {
> - struct xe_gt *gt = xe_device_get_gt(xe, 0);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> size_t size = xe_guc_hwconfig_size(>->uc.guc);
> void __user *query_ptr = u64_to_user_ptr(query->data);
> void *hwconfig;
> diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> index a3855870321f..012474a6c387 100644
> --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> @@ -54,7 +54,7 @@ bool xe_ttm_stolen_cpu_access_needs_ggtt(struct xe_device *xe)
> static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
> {
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> - struct xe_gt *gt = to_gt(xe);
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> u64 vram_size, stolen_size;
> int err;
>
> @@ -88,7 +88,7 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr
> u32 stolen_size;
> u32 ggc, gms;
>
> - ggc = xe_mmio_read32(to_gt(xe), GGC);
> + ggc = xe_mmio_read32(xe_root_mmio_gt(xe), GGC);
>
> /* check GGMS, should be fixed 0x3 (8MB) */
> if (drm_WARN_ON(&xe->drm, (ggc & GGMS_MASK) != GGMS_MASK))
next prev parent reply other threads:[~2023-05-22 11:47 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-19 23:17 [Intel-xe] [PATCH v2 00/30] Separate GT and tile Matt Roper
2023-05-19 23:17 ` [Intel-xe] [PATCH v2 01/30] drm/xe/mtl: Disable media GT Matt Roper
2023-05-20 5:50 ` Lucas De Marchi
2023-05-19 23:17 ` [Intel-xe] [PATCH v2 02/30] drm/xe: Introduce xe_tile Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 03/30] drm/xe: Add backpointer from gt to tile Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 04/30] drm/xe: Add for_each_tile iterator Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 05/30] drm/xe: Move register MMIO into xe_tile Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 06/30] fixup! drm/xe/display: Implement display support Matt Roper
2023-05-20 5:52 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 07/30] drm/xe: Move GGTT from GT to tile Matt Roper
2023-05-25 23:29 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 08/30] fixup! drm/xe/display: Implement display support Matt Roper
2023-05-25 23:30 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 09/30] drm/xe: Move VRAM from GT to tile Matt Roper
2023-05-26 21:11 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 10/30] fixup! drm/xe/display: Implement display support Matt Roper
2023-05-26 21:12 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 11/30] drm/xe: Memory allocations are tile-based, not GT-based Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 12/30] fixup! drm/xe/display: Implement display support Matt Roper
2023-05-26 21:14 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 13/30] drm/xe: Move migration from GT to tile Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 14/30] drm/xe: Clarify 'gt' retrieval for primary tile Matt Roper
2023-05-22 11:47 ` Das, Nirmoy [this message]
2023-05-26 21:33 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 15/30] drm/xe: Drop vram_id Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 16/30] drm/xe: Drop extra_gts[] declarations and XE_GT_TYPE_REMOTE Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 17/30] drm/xe: Allocate GT dynamically Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 18/30] drm/xe: Add media GT to tile Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 19/30] drm/xe: Move display IRQ postinstall out of GT function Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 20/30] drm/xe: Interrupts are delivered per-tile, not per-GT Matt Roper
2023-05-26 22:16 ` Lucas De Marchi
2023-05-30 6:36 ` Iddamsetty, Aravind
2023-05-30 15:58 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 21/30] drm/xe/irq: Handle ASLE backlight interrupts at same time as display Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 22/30] drm/xe/irq: Ensure primary GuC won't clobber media GuC's interrupt mask Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 23/30] drm/xe/irq: Untangle postinstall functions Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 24/30] drm/xe: Replace xe_gt_irq_postinstall with xe_irq_enable_hwe Matt Roper
2023-05-26 22:20 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 25/30] drm/xe: Invalidate TLB on all affected GTs during GGTT updates Matt Roper
2023-05-22 9:02 ` Das, Nirmoy
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 26/30] drm/xe/tlb: Obtain forcewake when doing GGTT TLB invalidations Matt Roper
2023-05-22 11:47 ` Das, Nirmoy
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 27/30] drm/xe: Allow GT looping and lookup on standalone media Matt Roper
2023-05-26 22:37 ` Lucas De Marchi
2023-05-30 16:41 ` Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 28/30] drm/xe: Update query uapi to support " Matt Roper
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 29/30] drm/xe: Reinstate media GT support Matt Roper
2023-05-26 22:46 ` Lucas De Marchi
2023-05-19 23:18 ` [Intel-xe] [PATCH v2 30/30] drm/xe: Add kerneldoc description of multi-tile devices Matt Roper
2023-05-26 22:52 ` Lucas De Marchi
2023-05-27 0:22 ` Matt Roper
2023-05-19 23:23 ` [Intel-xe] ✓ CI.Patch_applied: success for Separate GT and tile (rev3) Patchwork
2023-05-19 23:26 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
2023-05-19 23:29 ` [Intel-xe] ✓ CI.Build: " Patchwork
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