* [PATCH v6 3/5] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb
2026-08-10 7:11 [PATCH v6 0/5] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
2026-08-10 7:11 ` [PATCH v6 1/5] dt-bindings: soc: " Josua Mayer
2026-08-10 7:11 ` [PATCH v6 2/5] dt-bindings: usb: cypress,hx3: make peer-hub property optional Josua Mayer
@ 2026-08-10 7:11 ` Josua Mayer
2026-08-10 7:26 ` sashiko-bot
2026-08-10 7:11 ` [PATCH v6 4/5] arm64: dts: renesas: add support for solidrun rzv2l " Josua Mayer
` (2 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Josua Mayer @ 2026-08-10 7:11 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara
Cc: Josua Mayer, Jon Nettleton, Mikhail Anikin, Yazan Shhady,
linux-renesas-soc, devicetree, linux-kernel, linux-usb
Add support for the SolidRun RZ/G2L SoM [1] on Hummingboard IIoT [2].
The SoM features:
- 2x 1Gbps Ethernet with PHY
- eMMC
- 1/2GB DDR
- WiFi + Bluetooth
- SDHI Mux switching between eMMC and Carrier Board
The HummingBoard IIoT features:
- 3x USB-2.0 Type A connector
- 2x 1Gbps RJ45 Ethernet
- USB Type-C Console Port
- microSD connector
- RTC with backup battery
- RGB Status LED
- 1x M.2 B-Key connector with USB-2.0 + SIM card holder
- 1x DSI Display Connector
- GPIO header
- 2x RS232/RS485 ports (configurable)
- 2x CAN
Descriptions for eMMC, microSD and RS485 are provided as overlays due to
their dependency on configurable mux states.
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2l-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/renesas/Makefile | 13 +
.../dts/renesas/r9a07g044l2-hummingboard-iiot.dts | 16 +
.../renesas/rzg2l-hummingboard-iiot-common.dtsi | 560 +++++++++++++++++++++
.../renesas/rzg2l-hummingboard-iiot-microsd.dtso | 26 +
.../renesas/rzg2l-hummingboard-iiot-rs485-a.dtso | 17 +
.../renesas/rzg2l-hummingboard-iiot-rs485-b.dtso | 17 +
.../boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi | 49 ++
arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso | 44 ++
arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi | 451 +++++++++++++++++
9 files changed, 1193 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 8bf155badd11..e2af196e18bf 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -170,6 +170,19 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-sr-som-emmc.dtbo
+r9a07g044l2-hummingboard-iiot-emmc-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-emmc.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-microsd.dtbo
+r9a07g044l2-hummingboard-iiot-microsd-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-microsd.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-a.dtbo
+r9a07g044l2-hummingboard-iiot-rs485-a-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-rs485-a.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-b.dtbo
+r9a07g044l2-hummingboard-iiot-rs485-b-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-rs485-b.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-remi-pi.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts
new file mode 100644
index 000000000000..eba4f423c8f0
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "r9a07g044l2.dtsi"
+#include "rzg2l-sr-som.dtsi"
+#include "rzg2l-hummingboard-iiot.dtsi"
+
+/ {
+ compatible = "solidrun,rzg2l-hummingboard-iiot", "solidrun,rzg2l-sr-som",
+ "renesas,r9a07g044l2", "renesas,r9a07g044";
+ model = "SolidRun RZ/G2L HummingBoard IIoT";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
new file mode 100644
index 000000000000..eaec4cca7694
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
@@ -0,0 +1,560 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+/ {
+ /* power for M.2 B-Key connector (J6) */
+ regulator-m2-b {
+ compatible = "regulator-fixed";
+ regulator-name = "m2-b";
+ gpios = <&tca6416_u20 5 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ enable-active-high;
+ };
+
+ /* power for M.2 M-Key connector (J4) */
+ regulator-m2-m {
+ compatible = "regulator-fixed";
+ regulator-name = "m2-m";
+ gpios = <&tca6416_u20 6 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ enable-active-high;
+ };
+
+ /* power for USB-A J27 behind USB Hub Port 3 */
+ regulator-vbus-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus2";
+ regulator-always-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpios = <&tca6416_u20 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /* power for USB-A J27 behind USB Hub Port 4 */
+ regulator-vbus-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus3";
+ regulator-always-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpios = <&tca6416_u20 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ aliases {
+ gpio1 = &tca6408_u48;
+ gpio2 = &tca6408_u37;
+ gpio3 = &tca6416_u20;
+ gpio4 = &tca6416_u21;
+ i2c3 = &i2c_exp;
+ i2c4 = &i2c_csi;
+ i2c5 = &i2c_dsi;
+ i2c6 = &i2c_lvds;
+ rtc0 = &carrier_rtc;
+ rtc1 = &pmic;
+ serial3 = &scif3;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wakeup-event {
+ interrupts-extended = <&tca6416_u21 11 IRQ_TYPE_EDGE_FALLING>;
+ label = "m2-m-wakeup";
+ wakeup-source;
+ linux,code = <KEY_WAKEUP>;
+ };
+ };
+
+ can_mux: mux-controller-1 {
+ compatible = "gpio-mux";
+ /* default J9-55/57/59/61 to on-board transceivers */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux routes CAN bus signals between SoM connector pins,
+ * expansion connector (J22) and on-board transceivers using
+ * two GPIO:
+ * - IO3: 0 = on-board transceivers, 1 = expansion connector
+ * - IO4: 0 = J9-55/57/59/61, 1 = J7-12/16 & J9-54/56
+ */
+ mux-gpios = <&tca6416_u20 3 GPIO_ACTIVE_HIGH>,
+ <&tca6416_u20 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ spi_mux: mux-controller-2 {
+ compatible = "gpio-mux";
+ /* default on-board */
+ idle-state = <0>;
+ /*
+ * Mux switches spi bus between on-board tpm
+ * and expansion connector (J22).
+ */
+ mux-gpios = <&tca6416_u21 0 GPIO_ACTIVE_HIGH>;
+ #mux-control-cells = <0>;
+ };
+
+ scif1_scif3_b2b_mux: mux-controller-3 {
+ compatible = "gpio-mux";
+ /* default on-board */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches both scif1 and scif3 tx/rx between expansion
+ * connector (J22) and on-board rs232/rs485 transceivers
+ * using one GPIO: 0 = on-board, 1 = connector.
+ */
+ mux-gpios = <&tca6416_u20 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ scif1_rs_232_485_mux: mux-controller-4 {
+ compatible = "gpio-mux";
+ /* default rs232 */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches scif1 tx/rx between rs232 and rs485
+ * transceivers. using one GPIO: 0 = rs232, 1 = rs485.
+ */
+ mux-gpios = <&tca6416_u20 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ scif3_rs_232_485_mux: mux-controller-5 {
+ compatible = "gpio-mux";
+ /* default rs232 */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches scif3 tx/rx between rs232 and rs485
+ * transceivers. using one GPIO: 0 = rs232, 1 = rs485.
+ */
+ mux-gpios = <&tca6416_u20 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ v_1_2: regulator-1-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v2";
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ };
+
+ v_3_3: regulator-3-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reg_dsi_panel: regulator-dsi-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "dsi-panel";
+ gpios = <&tca6416_u20 15 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <11200000>;
+ regulator-min-microvolt = <11200000>;
+ enable-active-high;
+ };
+
+ vmmc: regulator-mmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ startup-delay-us = <250>;
+ vin-supply = <&v_3_3>;
+ gpios = <&pinctrl RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /* power for USB-A J5003 */
+ vbus1: regulator-vbus-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus1";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpios = <&tca6416_u20 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ rfkill-m2-b-gnss {
+ compatible = "rfkill-gpio";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_LOW>;
+ label = "m2-b gnss";
+ radio-type = "gps";
+ };
+
+ rfkill-m2-b-wwan {
+ compatible = "rfkill-gpio";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&tca6416_u20 9 GPIO_ACTIVE_HIGH>;
+ label = "m2-b radio";
+ radio-type = "wwan";
+ };
+};
+
+&ehci1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub_2_0: hub@1 {
+ compatible = "usb4b4,6502", "usb4b4,6506";
+ reg = <1>;
+ reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>;
+ vdd2-supply = <&v_3_3>;
+ vdd-supply = <&v_1_2>;
+ };
+};
+
+&i2c0 {
+ /* highest i2c clock supported by all peripherals is 400kHz */
+
+ tca6416_u20: gpio@20 {
+ compatible = "ti,tcal6416";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names = "TCA_INT/EXT_UART", "TCA_UARTA_232/485",
+ "TCA_UARTB_232/485", "TCA_INT/EXT_CAN",
+ "TCA_NXP/REN", "TCA_M.2B_3V3_EN",
+ "TCA_M.2M_3V3_EN", "TCA_M.2M_RESET#",
+ "TCA_M.2B_RESET#", "TCA_M.2B_W_DIS#",
+ "TCA_M.2B_GPS_EN#", "TCA_USB-HUB_RST#",
+ "TCA_USB_HUB3_PWR_EN", "TCA_USB_HUB4_PWR_EN",
+ "TCA_USB1_PWR_EN", "TCA_VIDEO_PWR_EN";
+
+ m2-b-reset-hog {
+ gpios = <8 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ line-name = "m2-b-reset";
+ output-low;
+ };
+
+ m2-m-reset-hog {
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ line-name = "m2-m-reset";
+ /*
+ * M.2 Key-M connector only supports PCI,
+ * but RZ/G2L(C) has no pci controller.
+ * Keep any card in reset.
+ */
+ output-high;
+ };
+ };
+
+ tca6416_u21: gpio@21 {
+ compatible = "ti,tcal6416";
+ reg = <0x21>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#",
+ "TCA_I2C_RST", "TCA_RS232_SHTD#",
+ "TCA_LCD_I2C_RST", "TCA_DIG_OUT1",
+ "TCA_bDIG_IN1", "TCA_SENS_INT",
+ "TCA_ALERT#", "TCA_TPM_PIRQ#",
+ "TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN",
+ "TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#",
+ "", "TCA_POE_AT";
+ /* Level triggered irq does not currently work well on RZ/G2L, fall-back to edge */
+ interrupts-extended = <&pinctrl RZG2L_GPIO(4, 0) IRQ_TYPE_EDGE_FALLING>;
+
+ lcd-i2c-reset-hog {
+ gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ line-name = "lcd-i2c-reset";
+ output-low;
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ */
+ gpio-hog;
+ };
+
+ lvds-irq-hog {
+ gpios = <13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ gpio-hog;
+ input;
+ line-name = "lvds-irq";
+ };
+
+ m2-m-clkreq-hog {
+ gpios = <12 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ input;
+ line-name = "m2-m-clkreq";
+ };
+
+ rs232_shutdown: rs232-shutdown-hog {
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ line-name = "rs232-shutdown";
+ output-low;
+ };
+
+ sensor-irq-hog {
+ gpios = <7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ gpio-hog;
+ input;
+ line-name = "sensor-irq";
+ };
+
+ tpm-irq-hog {
+ gpios = <9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ gpio-hog;
+ input;
+ line-name = "tpm-irq";
+ };
+ };
+
+ led-controller@30 {
+ compatible = "ti,lp5562";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* use internal clock, could use external generated by rtc */
+ clock-mode = /bits/ 8 <1>;
+
+ multi-led@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ color = <LED_COLOR_ID_RGB>;
+ label = "D7";
+
+ led@0 {
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RED>;
+ led-cur = /bits/ 8 <0x32>;
+ max-cur = /bits/ 8 <0x64>;
+ };
+
+ led@1 {
+ reg = <0x1>;
+ color = <LED_COLOR_ID_GREEN>;
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x32>;
+ };
+
+ led@2 {
+ reg = <0x2>;
+ color = <LED_COLOR_ID_BLUE>;
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x32>;
+ };
+ };
+
+ led@3 {
+ reg = <0x3>;
+ chan-name = "D8";
+ color = <LED_COLOR_ID_GREEN>;
+ label = "D8";
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x64>;
+ };
+ };
+
+ light-sensor@44 {
+ compatible = "isil,isl29023";
+ reg = <0x44>;
+ /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
+ interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ accelerometer@53 {
+ compatible = "adi,adxl345";
+ reg = <0x53>;
+ interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_LEVEL_LOW>;
+ /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
+ interrupt-names = "INT1";
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <8>;
+ };
+
+ carrier_rtc: rtc@69 {
+ compatible = "abracon,ab1805";
+ reg = <0x69>;
+ /*
+ * AM1805 RTC used on this board has only nTIRQ pins wired,
+ * which is for countdown timer irqs only.
+ * Driver does not support this, disable for now.
+ *
+ * interrupts-extended = <&tca6416_u21 10 IRQ_TYPE_LEVEL_LOW>;
+ */
+ abracon,tc-diode = "schottky";
+ abracon,tc-resistor = <3>;
+ };
+};
+
+&i2c1 {
+ /* highest i2c clock supported by all peripherals is 400kHz */
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /*
+ * This reset is open drain with HW 10k pull-up resistor,
+ * but reset core does not support GPIO_OPEN_DRAIN flag.
+ * The pull-up and GPIO voltages match, push-pull is safe.
+ */
+ reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>;
+
+ /* channel 0 routed to expansion connector (J22) */
+ i2c_exp: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* channel 1 routed to mipi-csi connector (J23) */
+ i2c_csi: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* channel 2 routed to mipi-dsi connector (J25) */
+ i2c_dsi: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6408_u48: gpio@21 {
+ compatible = "ti,tca6408";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-line-names = "CAM_RST#", "DSI_RESET",
+ "DSI_STBYB", "DSI_PWM_BL",
+ "DSI_L/R", "DSI_U/D",
+ "DSI_CTP_/RST", "CAM_TRIG";
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ *
+ * reset-gpios = <&tca6416_u21 4
+ * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ */
+ gpio-controller;
+ };
+ };
+
+ /* channel 3 routed to lvds connector (J24) */
+ i2c_lvds: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6408_u37: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-line-names = "SELB", "LVDS_RESET",
+ "LVDS_STBYB", "LVDS_PWM_BL",
+ "LVDS_L/R", "LVDS_U/D",
+ "LVDS_CTP_/RST", "";
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ *
+ * reset-gpios = <&tca6416_u21 4
+ * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ */
+ gpio-controller;
+ };
+ };
+ };
+};
+
+&phy0 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* LED_0 pin */
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "keep";
+ function = LED_FUNCTION_LAN;
+ };
+ };
+};
+
+&pinctrl {
+ /* UARTA */
+ scif1_pins: scif1 {
+ pinmux = <RZG2L_PORT_PINMUX(40, 1, 1)>, /* SCIF1_RXD */
+ <RZG2L_PORT_PINMUX(40, 0, 1)>; /* SCIF1_TXD */
+ };
+
+ /* UARTB */
+ scif3_pins: scif3 {
+ pinmux = <RZG2L_PORT_PINMUX(0, 1, 5)>, /* SCIF3_RXD */
+ <RZG2L_PORT_PINMUX(0, 0, 5)>; /* SCIF3_TXD */
+ };
+};
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif3 {
+ pinctrl-0 = <&scif3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&spi1 {
+ /* native cs does not support cs persistence required for tpm */
+ cs-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>;
+ num-cs = <1>;
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi1_muxed: spi@0 {
+ compatible = "spi-mux";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mux-controls = <&spi_mux>;
+ /* mux bandwidth is 2GHz, soc max. spi clock is P0/2 = 50MHz */
+ spi-max-frequency = <50000000>;
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ interrupts-extended = <&tca6416_u21 9 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tca6416_u21 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ spi-max-frequency = <43000000>;
+ };
+ };
+};
+
+&ohci0 {
+ dr_mode = "host";
+};
+
+&usb2_phy0 {
+ vbus-supply = <&vbus1>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso
new file mode 100644
index 000000000000..c86d46956f82
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+* Device Tree Overlay for the RZ/G2L(C) Solidrun SOM SD
+*
+* Copyright (C) 2024 SolidRun Ltd.
+*/
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+&sdhi0 {
+ bus-width = <4>;
+ full-pwr-cycle;
+ mux-states = <&sdhi0_mux 1>;
+ pinctrl-0 = <&sdhi0_4bit_pins>, <&sdhi0_cd_pins>;
+ pinctrl-1 = <&sdhi0_4bit_uhs_pins>, <&sdhi0_cd_pins>;
+ pinctrl-names = "default", "state_uhs";
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ vmmc-supply = <&vmmc>;
+ vqmmc-supply = <®_pmic_ldo1>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso
new file mode 100644
index 000000000000..4bcb22d518f0
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connector J5004.
+ *
+ * Because Renesas uart driver does not support rs485,
+ * users must manually toggle P41_1 between RX & TX.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&scif1_rs_232_485_mux {
+ /* select rs485 */
+ idle-state = <1>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso
new file mode 100644
index 000000000000..6f460b3e0b25
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT on-board RS485 Port B on connector J5004.
+ *
+ * Because Renesas uart driver does not support rs485,
+ * users must manually toggle P41_0 between RX & TX.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&scif3_rs_232_485_mux {
+ /* select rs485 */
+ idle-state = <1>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi
new file mode 100644
index 000000000000..22f066079e69
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include "rzg2l-hummingboard-iiot-common.dtsi"
+
+&canfd {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins>, <&can1_pins>;
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+
+ channel1 {
+ status = "okay";
+ };
+};
+
+&phy1 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* LED_0 pin */
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+};
+
+&pinctrl {
+ /* CANA */
+ can0_pins: can0 {
+ pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* CAN0_TX */
+ <RZG2L_PORT_PINMUX(11, 0, 2)>; /* CAN0_RX */
+ };
+
+ /* CANB */
+ can1_pins: can1 {
+ pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* CAN1_TX */
+ <RZG2L_PORT_PINMUX(13, 0, 2)>; /* CAN1_RX */
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso b/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso
new file mode 100644
index 000000000000..263a36994b03
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+* Device Tree Overlay for the RZ/G2L(C) Solidrun SOM eMMC
+*
+* Copyright (C) 2024 SolidRun Ltd.
+*/
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+®_pmic_ldo1 {
+ /*
+ * This ldo can switch mmc host controller io voltage between
+ * 1.8V and 3.3V. The eMMC IO voltage however is supplied from
+ * reg_pmic_buck3 which is fixed at 1.8V.
+ * Lower this ldo maximum voltage to 1.8V to prevent setting 3.3V.
+ */
+ regulator-max-microvolt = <1800000>;
+};
+
+&sdhi0 {
+ /*
+ * Host controller and eMMC have separate io voltage regulators:
+ * reg_pmic_ldo1 (1.8V/3.3V); reg_pmic_buck3 (1.8V only).
+ * Link to the switchable regulator ensuring that it gets configured.
+ */
+ vqmmc-supply = <®_pmic_ldo1>;
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ mux-states = <&sdhi0_mux 0>;
+ non-removable;
+ no-sdio;
+ pinctrl-0 = <&sdhi0_8bit_uhs_pins>, <&sdhi0_rst_pins>;
+ pinctrl-1 = <&sdhi0_8bit_uhs_pins>, <&sdhi0_rst_pins>;
+ pinctrl-names = "default", "state_uhs";
+ vmmc-supply = <®_pmic_buck4>;
+ /* emmc io voltage is hard-wired for 1.8V, disable sd modes */
+ no-sd;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
new file mode 100644
index 000000000000..32e967aa9e51
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
@@ -0,0 +1,451 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L Solidrun SoM
+ *
+ * Copyright 2023 SolidRun Ltd.
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+/ {
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ gpio0 = &pinctrl;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c3;
+ mmc0 = &sdhi0;
+ mmc1 = &sdhi1;
+ rtc0 = &pmic;
+ serial0 = &scif0;
+ serial1 = &scif1;
+ serial2 = &scif2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sdhi0_mux: mux-controller-0 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ #mux-state-cells = <1>;
+ /*
+ * Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between
+ * on-SoM eMMC and board-to-board connector using one gpio:
+ * Low = connector, High = eMMC.
+ * Define active-low for logical mux state 0 = eMMC, 1 = connector.
+ */
+ mux-gpios = <&pinctrl RZG2L_GPIO(22, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ clk_pmic_32k: pmic-32k-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ reg_pmic_buck1: regulator-pmic-buck1 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ };
+
+ reg_pmic_buck3: regulator-pmic-buck3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ reg_pmic_buck4: regulator-pmic-buck4 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck4";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reg_pmic_ldo1: regulator-pmic-ldo1 {
+ compatible = "regulator-gpio";
+ regulator-name = "pmic-ldo1";
+ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ states = <3300000 1>, <1800000 0>;
+ };
+
+ reg_pmic_ldo2: regulator-pmic-ldo2 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-ldo2";
+ /*
+ * This ldo can switch mmc host controller io voltage between
+ * 1.8V and 3.3V by assembly option of pull-up / pull-dow.
+ * Default assembly is 3.3V.
+ */
+ regulator-min-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mmp_reserved: linux,multimedia@68000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x68000000 0x0 0x8000000>;
+ reusable;
+ };
+
+ global_cma: linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x58000000 0x0 0x10000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ sdhi1_pwrseq: sdhi1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pinctrl RZG2L_GPIO(23, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ /* 32.768kHz crystal */
+ x2: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ memory@40000000 {
+ reg = <0x0 0x40000000 0x0 0x40000000>;
+ device_type = "memory";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+ð0 {
+ phy-handle = <&phy0>;
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ /*
+ * ravb driver does not configure mac internal delays for RZ/G2L(C),
+ * instead delays are added by the MxL86110 phy driver.
+ */
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ interrupts-extended = <&pinctrl RZG2L_GPIO(27, 0) IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ð1 {
+ phy-handle = <&phy1>;
+ pinctrl-0 = <ð1_pins>;
+ pinctrl-names = "default";
+ /*
+ * ravb driver does not configure mac internal delays for RZ/G2L(C),
+ * instead delays are added by the MxL86110 phy driver.
+ */
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy1: ethernet-phy@4 {
+ reg = <4>;
+ interrupts-extended = <&pinctrl RZG2L_GPIO(42, 4) IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&gpu {
+ mali-supply = <®_pmic_buck1>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pmic: pmic@12 {
+ compatible = "renesas,raa215300";
+ reg = <0x12>, <0x6f>;
+ reg-names = "main", "rtc";
+ clocks = <&x2>;
+ clock-names = "xin";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
+&ostm2 {
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
+&pinctrl {
+ eth0_pins: eth0 {
+ pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+ <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+ <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+ <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+ <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+ <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+ <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+ <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+ <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+ <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+ <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+ <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+ };
+
+ eth1_pins: eth1 {
+ pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
+ <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
+ <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
+ <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
+ <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
+ <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
+ <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
+ <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
+ <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
+ <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
+ <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
+ <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
+ <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
+ <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
+ <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
+ };
+
+ i2c0_pins: i2c0 {
+ input-enable;
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ };
+
+ i2c1_pins: i2c1 {
+ input-enable;
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ };
+
+ i2c3_pins: i2c3 {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* RIIC3_SDA */
+ <RZG2L_PORT_PINMUX(18, 1, 3)>; /* RIIC3_SCL */
+ };
+
+ qspi0_pins: qspi0 {
+ pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3",
+ "QSPI0_SPCLK", "QSPI0_SSL";
+ power-source = <1800>;
+ };
+
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* SCIF0_TXD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* SCIF0_RXD */
+ };
+
+ scif2_pins: scif2 {
+ pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* SCIF2_TXD */
+ <RZG2L_PORT_PINMUX(48, 1, 1)>, /* SCIF2_RXD */
+ <RZG2L_PORT_PINMUX(48, 3, 1)>, /* SCIF2_CTS# */
+ <RZG2L_PORT_PINMUX(48, 4, 1)>; /* SCIF2_RTS# */
+ };
+
+ sdhi0_4bit_pins: sdhi0-4bit {
+ sd0_ctrl_dat03 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <3300>;
+ };
+
+ /*
+ * Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
+ * with all pins sharing a single voltage domain.
+ *
+ * Configure as input without pull to avoid overvoltage,
+ * and accidental use e.g. as gpio (default pin-function).
+ */
+ sd0_dat47 {
+ bias-disable;
+ input-enable;
+ pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ power-source = <3300>;
+ };
+ };
+
+ sdhi0_4bit_uhs_pins: sdhi0-4bit-uhs {
+ sd0_ctrl_dat03 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ /*
+ * Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
+ * with all pins sharing a single voltage domain.
+ *
+ * Configure as input without pull to avoid accidental use,
+ * e.g. as gpio (default pin-function).
+ */
+ sd0_dat47 {
+ bias-disable;
+ input-enable;
+ pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ power-source = <1800>;
+ };
+ };
+
+ sdhi0_8bit_uhs_pins: sdhi0-8bit-uhs {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sdhi0_cd_pins: sdhi0-cd {
+ pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
+ };
+
+ /* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */
+ sdhi0_rst_pins: sdhi0-rst {
+ pins = "SD0_RST#";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sdhi1 {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3",
+ "SD1_CLK", "SD1_CMD";
+ power-source = <3300>;
+ };
+
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(44, 2, 1)>, /* RSPI1_MISO */
+ <RZG2L_PORT_PINMUX(44, 1, 1)>, /* RSPI1_MOSI# */
+ <RZG2L_PORT_PINMUX(44, 0, 1)>;
+ };
+
+ spi1_cs_pins: spi1-cs {
+ pinmux = <RZG2L_PORT_PINMUX(44, 3, 1)>; /* RSPI1_SSL */
+ };
+};
+
+&sbc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "winbond,w25q80bl", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* WiFi */
+&sdhi1 {
+ /* Murata 1MW max rate is 50MHz */
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ cap-sdio-irq;
+ mmc-pwrseq = <&sdhi1_pwrseq>;
+ non-removable;
+ no-1-8-v;
+ no-sd;
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_pmic_buck4>;
+ /*
+ * Host controller IO voltage is provided from reg_pmic_ldo2,
+ * WiFi module IO voltage from reg_pmic_buck4.
+ * Neither is configurable at run-time so either can be set here.
+ */
+ vqmmc-supply = <®_pmic_ldo2>;
+ status = "okay";
+};
+
+&usb2_phy0 {
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v6 5/5] arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
2026-08-10 7:11 [PATCH v6 0/5] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
` (3 preceding siblings ...)
2026-08-10 7:11 ` [PATCH v6 4/5] arm64: dts: renesas: add support for solidrun rzv2l " Josua Mayer
@ 2026-08-10 7:11 ` Josua Mayer
2026-09-01 18:29 ` [PATCH v6 0/5] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
5 siblings, 0 replies; 9+ messages in thread
From: Josua Mayer @ 2026-08-10 7:11 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara
Cc: Josua Mayer, Jon Nettleton, Mikhail Anikin, Yazan Shhady,
linux-renesas-soc, devicetree, linux-kernel, linux-usb
Add support for the SolidRun RZ/G2LC SoM [1] on Hummingboard IIoT [2].
The SoM features:
- 1Gbps Ethernet with PHY
- eMMC
- 1/2GB DDR
- WiFi + Bluetooth
- SDHI Mux switching between eMMC and Carrier Board
The HummingBoard IIoT features:
- 3x USB-2.0 Type A connector
- 1x 1Gbps RJ45 Ethernet
- USB Type-C Console Port
- microSD connector
- RTC with backup battery
- RGB Status LED
- 1x M.2 B-Key connector with USB-2.0 + SIM card holder
- 1x DSI Display Connector
- GPIO header
- 2x RS232/RS485 ports (configurable)
The RZ/G2LC SoM was designed to be pin compatible to G2L SoM, with
slightly reduced feature set.
Descriptions for eMMC, microSD, and RS485 are shared with G2L.
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2lc-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/renesas/Makefile | 9 +
.../dts/renesas/r9a07g044c2-hummingboard-iiot.dts | 20 +
arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi | 408 +++++++++++++++++++++
3 files changed, 437 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 4a0cde8cc3b7..69b1f7515601 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -165,6 +165,15 @@ dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtb
r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot.dtb
+r9a07g044c2-hummingboard-iiot-emmc-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-emmc.dtb
+r9a07g044c2-hummingboard-iiot-microsd-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-microsd.dtb
+r9a07g044c2-hummingboard-iiot-rs485-a-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-a.dtb
+r9a07g044c2-hummingboard-iiot-rs485-b-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-b.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts
new file mode 100644
index 000000000000..9cc21ae32ed4
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "r9a07g044c2.dtsi"
+#include "rzg2lc-sr-som.dtsi"
+#include "rzg2l-hummingboard-iiot-common.dtsi"
+
+/ {
+ compatible = "solidrun,rzg2lc-hummingboard-iiot", "solidrun,rzg2lc-sr-som",
+ "renesas,r9a07g044c2", "renesas,r9a07g044";
+ model = "SolidRun RZ/G2LC HummingBoard IIoT";
+};
+
+&vmmc {
+ gpios = <&pinctrl RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
new file mode 100644
index 000000000000..a497cc4dba28
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC Solidrun SOM
+ *
+ * Copyright 2023 SolidRun Ltd.
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+/ {
+ aliases {
+ ethernet0 = ð0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ mmc0 = &sdhi0;
+ mmc1 = &sdhi1;
+ rtc0 = &pmic;
+ serial0 = &scif0;
+ serial1 = &scif1;
+ serial2 = &scif2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sdhi0_mux: mux-controller-0 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ #mux-state-cells = <1>;
+ /*
+ * Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between
+ * on-SoM eMMC and board-to-board connector using one gpio:
+ * High = connector, Low = eMMC.
+ * Define active-high for logical mux state 0 = eMMC, 1 = connector.
+ */
+ mux-gpios = <&pinctrl RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_pmic_buck1: regulator-pmic-buck1 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ };
+
+ reg_pmic_buck3: regulator-pmic-buck3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ reg_pmic_buck4: regulator-pmic-buck4 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck4";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reg_pmic_ldo1: regulator-pmic-ldo1 {
+ compatible = "regulator-gpio";
+ regulator-name = "pmic-ldo1";
+ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ states = <3300000 1>, <1800000 0>;
+ };
+
+ reg_pmic_ldo2: regulator-pmic-ldo2 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-ldo2";
+ /*
+ * This ldo can switch mmc host controller io voltage between
+ * 1.8V and 3.3V by assembly option of pull-up / pull-dow.
+ * Default assembly is 3.3V.
+ */
+ regulator-min-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mmp_reserved: linux,multimedia@68000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x68000000 0x0 0x8000000>;
+ reusable;
+ };
+
+ global_cma: linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x58000000 0x0 0x10000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ sdhi1_pwrseq: sdhi1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ /* 32.768kHz crystal */
+ x2: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ memory@40000000 {
+ reg = <0x0 0x40000000 0x0 0x40000000>;
+ device_type = "memory";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+ð0 {
+ phy-handle = <&phy0>;
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ /*
+ * ravb driver does not configure mac internal delays for RZ/G2L(C),
+ * instead delays are added by the ADIN1200 phy driver.
+ */
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ interrupts-extended = <&pinctrl RZG2L_GPIO(27, 0) IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&gpu {
+ mali-supply = <®_pmic_buck1>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pmic: pmic@12 {
+ compatible = "renesas,raa215300";
+ reg = <0x12>, <0x6f>;
+ reg-names = "main", "rtc";
+ clocks = <&x2>;
+ clock-names = "xin";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
+&ostm2 {
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
+&pinctrl {
+ eth0_pins: eth0 {
+ pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+ <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+ <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+ <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+ <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+ <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+ <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+ <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+ <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+ <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+ <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+ <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+ };
+
+ i2c0_pins: i2c0 {
+ input-enable;
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ };
+
+ i2c1_pins: i2c1 {
+ input-enable;
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ };
+
+ i2c2_pins: i2c2 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* RIIC2_SDA */
+ <RZG2L_PORT_PINMUX(42, 4, 1)>; /* RIIC2_SCL */
+ };
+
+ qspi0_pins: qspi0 {
+ pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3",
+ "QSPI0_SPCLK", "QSPI0_SSL";
+ power-source = <1800>;
+ };
+
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* SCIF0_TXD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* SCIF0_RXD */
+ };
+
+ scif2_pins: scif2 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 0, 4)>, /* SCIF2_TXD */
+ <RZG2L_PORT_PINMUX(42, 1, 4)>, /* SCIF2_RXD */
+ <RZG2L_PORT_PINMUX(5, 1, 2)>, /* SCIF2_CTS# */
+ <RZG2L_PORT_PINMUX(5, 2, 2)>; /* SCIF2_RTS# */
+ };
+
+ sdhi0_4bit_pins: sdhi0-4bit {
+ sd0_ctrl_dat03 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <3300>;
+ };
+
+ /*
+ * Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
+ * with all pins sharing a single voltage domain.
+ *
+ * Configure as input without pull to avoid overvoltage,
+ * and accidental use e.g. as gpio (default pin-function).
+ */
+ sd0_dat47 {
+ bias-disable;
+ input-enable;
+ pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ power-source = <3300>;
+ };
+ };
+
+ sdhi0_4bit_uhs_pins: sdhi0-4bit-uhs {
+ sd0_ctrl_dat03 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ /*
+ * Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
+ * with all pins sharing a single voltage domain.
+ *
+ * Configure as input without pull to avoid accidental use,
+ * e.g. as gpio (default pin-function).
+ */
+ sd0_dat47 {
+ bias-disable;
+ input-enable;
+ pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ power-source = <1800>;
+ };
+ };
+
+ sdhi0_8bit_uhs_pins: sdhi0-8bit-uhs {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sdhi0_cd_pins: sdhi0-cd {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
+ };
+
+ /* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */
+ sdhi0_rst_pins: sdhi0-rst {
+ pins = "SD0_RST#";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sdhi1 {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3",
+ "SD1_CLK", "SD1_CMD";
+ power-source = <3300>;
+ };
+
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(44, 2, 1)>, /* RSPI1_MISO */
+ <RZG2L_PORT_PINMUX(44, 1, 1)>, /* RSPI1_MOSI# */
+ <RZG2L_PORT_PINMUX(44, 0, 1)>; /* RSPI1_CK# */
+ };
+
+ spi1_cs_pins: spi1-cs {
+ pinmux = <RZG2L_PORT_PINMUX(44, 3, 1)>; /* RSPI1_SSL */
+ };
+};
+
+&sbc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "winbond,w25q80bl", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* WiFi */
+&sdhi1 {
+ /* Murata 1YN max rate is 50MHz */
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ cap-sdio-irq;
+ mmc-pwrseq = <&sdhi1_pwrseq>;
+ non-removable;
+ no-1-8-v;
+ no-sd;
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_pmic_buck4>;
+ /*
+ * Host controller IO voltage is provided from reg_pmic_ldo2,
+ * WiFi module IO voltage from reg_pmic_buck4.
+ * Neither is configurable at run-time so either can be set here.
+ */
+ vqmmc-supply = <®_pmic_ldo2>;
+ status = "okay";
+};
+
+&usb2_phy0 {
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread