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* [PATCH i-g-t v1] tests/kms_vblank: Skip timing check in simulation to avoid false negatives
@ 2025-07-11 18:07 Naladala Ramanaidu
  2025-07-11 20:01 ` ✓ Xe.CI.BAT: success for " Patchwork
                   ` (4 more replies)
  0 siblings, 5 replies; 6+ messages in thread
From: Naladala Ramanaidu @ 2025-07-11 18:07 UTC (permalink / raw)
  To: igt-dev; +Cc: swati2.sharma, Naladala Ramanaidu

Simulation environments often do not reflect real hardware timing
accurately, which can result in false negatives during vblank
sequence testing. To prevent such issues, this patch conditionally
skips the timing  validation when the test run in simulation.

Signed-off-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
---
 tests/kms_vblank.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index b8044ad42..75cf9448f 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -460,8 +460,17 @@ static void vblank_ts_cont(data_t *data, int fd, int nchildren)
 
 	igt_assert_f(seq2 - seq1 >= 0, "elapsed %f(%d vblanks) unexpected vblank seq %u, should be > %u\n", time_elapsed,
 			estimated_vblanks, seq2, seq1);
-	igt_assert_f(seq2 - seq1 <= estimated_vblanks + VBLANK_ERR, "elapsed %f(%d vblanks) unexpected vblank seq %u, should be <= %u\n", time_elapsed,
-			estimated_vblanks, seq2, seq1 + estimated_vblanks);
+	/*
+	 * Timing behavior in simulation environments often differs from real hardware,
+	 * which can lead to false negatives during testing. To mitigate this, disable
+	 * timestamp and sequence validations when the INTEL_SIMULATION environment
+	 * variable is active.
+	 */
+	if (!igt_run_in_simulation())
+		igt_assert_f(seq2 - seq1 <= estimated_vblanks + VBLANK_ERR,
+			     "elapsed %f(%d vblanks) unexpected vblank seq %u, should be <= %u\n",
+			     time_elapsed, estimated_vblanks,
+			     seq2, seq1 + estimated_vblanks);
 }
 
 static void run_subtests(data_t *data)
-- 
2.43.0


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2025-07-11 18:07 [PATCH i-g-t v1] tests/kms_vblank: Skip timing check in simulation to avoid false negatives Naladala Ramanaidu
2025-07-11 20:01 ` ✓ Xe.CI.BAT: success for " Patchwork
2025-07-11 20:03 ` ✓ i915.CI.BAT: " Patchwork
2025-07-12  4:40 ` ✓ i915.CI.Full: " Patchwork
2025-07-12  5:35 ` ✓ Xe.CI.Full: " Patchwork
2025-07-21 18:06 ` [PATCH i-g-t v1] " Sharma, Swati2

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