* [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW
@ 2026-03-26 11:26 Robert Marko
2026-03-26 11:26 ` [PATCH 02/14] pinctrl: add Microchip LAN969x driver Robert Marko
` (13 more replies)
0 siblings, 14 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
USART driver is reused by a lot of Microchip platforms, in this case we
need it for LAN969x so allow selecting it when ARCH_MICROCHIPSW is used.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/serial/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b84cb9ec781..3848c3ca20e 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -665,7 +665,7 @@ config ARM_DCC
config ATMEL_USART
bool "Atmel USART support"
- depends on ARCH_AT91
+ depends on ARCH_AT91 || ARCH_MICROCHIPSW
help
Select this to enable USART support for Atmel SoCs. It can be
configured in the device tree, and input clock frequency can
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 02/14] pinctrl: add Microchip LAN969x driver
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 03/14] clk: add Microchip LAN966x and LAN969x support Robert Marko
` (12 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
Add pinctrl, pinconf and GPIO driver for Microchip LAN969x.
This is updated version of the vendor U-Boot driver to include all
pinmux functions supported in Linux as well as printing the current
pinmux as set in the SoC.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/pinctrl/Kconfig | 8 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-lan969x.c | 582 ++++++++++++++++++++++++++++++
3 files changed, 591 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-lan969x.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ea90713ec6c..b962c61c8ea 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -227,6 +227,14 @@ config PINCTRL_INTEL
driver which must be separately enabled. The driver supports setting
pins on start-up and changing the GPIO attributes.
+config PINCTRL_LAN969X
+ bool "Microchip LAN969X pinctrl driver"
+ depends on DM && TARGET_LAN969X
+ select PINCONF
+ select REGMAP
+ help
+ This option is to enable the LAN969X pinctrl driver.
+
config PINCTRL_PIC32
bool "Microchip PIC32 pin-control and pin-mux driver"
depends on DM && MACH_PIC32
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 33ff7b95ef2..d0c46268673 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(PHASE_)PINCTRL_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_ATH79) += ath79/
obj-$(CONFIG_PINCTRL_INTEL) += intel/
+obj-$(CONFIG_PINCTRL_LAN969X) += pinctrl-lan969x.o
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_PINCTRL_QCOM) += qcom/
diff --git a/drivers/pinctrl/pinctrl-lan969x.c b/drivers/pinctrl/pinctrl-lan969x.c
new file mode 100644
index 00000000000..70e66193ddd
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-lan969x.c
@@ -0,0 +1,582 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include <asm/gpio.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/devres.h>
+#include <dm/device-internal.h>
+#include <dm/pinctrl.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/bitfield.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <regmap.h>
+
+/* GPIO standard registers */
+#define LAN969X_FUNC_PER_PIN 8
+
+/* GPIO standard registers */
+#define LAN969X_GPIO_OUT_SET 0x0
+#define LAN969X_GPIO_OUT_CLR 0x4
+#define LAN969X_GPIO_OUT 0x8
+#define LAN969X_GPIO_IN 0xc
+#define LAN969X_GPIO_OE 0x10
+#define LAN969X_GPIO_INTR 0x14
+#define LAN969X_GPIO_INTR_ENA 0x18
+#define LAN969X_GPIO_INTR_IDENT 0x1c
+#define LAN969X_GPIO_ALT0 0x20
+#define LAN969X_GPIO_ALT1 0x24
+#define LAN969X_GPIO_ALT2 0x28
+#define LAN969X_GPIO_SD_MAP 0x2c
+
+enum {
+ FUNC_CAN0_a,
+ FUNC_CAN0_b,
+ FUNC_CAN1,
+ FUNC_CLKMON,
+ FUNC_NONE,
+ FUNC_FAN,
+ FUNC_FC,
+ FUNC_FC_SHRD,
+ FUNC_FUSA,
+ FUNC_GPIO,
+ FUNC_IRQ0,
+ FUNC_IRQ1,
+ FUNC_IRQ3,
+ FUNC_IRQ4,
+ FUNC_MIIM,
+ FUNC_MIIM_Sa,
+ FUNC_MIIM_IRQ,
+ FUNC_PCIE_PERST,
+ FUNC_PTPSYNC_0,
+ FUNC_PTPSYNC_1,
+ FUNC_PTPSYNC_2,
+ FUNC_PTPSYNC_3,
+ FUNC_PTPSYNC_4,
+ FUNC_PTPSYNC_5,
+ FUNC_PTPSYNC_6,
+ FUNC_PTPSYNC_7,
+ FUNC_QSPI1,
+ FUNC_R,
+ FUNC_SD,
+ FUNC_SFP_SD,
+ FUNC_SGPIO_a,
+ FUNC_SYNCE,
+ FUNC_TWI,
+ FUNC_USB_POWER,
+ FUNC_USB2PHY_RST,
+ FUNC_USB_OVER_DETECT,
+ FUNC_USB_ULPI,
+ FUNC_EMMC_SD,
+ FUNC_MAX
+};
+
+static const char *const lan969x_function_names[FUNC_MAX] = {
+ [FUNC_CAN0_a] = "can0_a",
+ [FUNC_CAN0_b] = "can0_b",
+ [FUNC_CAN1] = "can1",
+ [FUNC_CLKMON] = "clkmon",
+ [FUNC_NONE] = "none",
+ [FUNC_FAN] = "fan",
+ [FUNC_FC] = "fc",
+ [FUNC_FC_SHRD] = "fc_shrd",
+ [FUNC_FUSA] = "fusa",
+ [FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0] = "irq0",
+ [FUNC_IRQ1] = "irq1",
+ [FUNC_IRQ3] = "irq3",
+ [FUNC_IRQ4] = "irq4",
+ [FUNC_MIIM] = "miim",
+ [FUNC_MIIM_Sa] = "miim_slave_a",
+ [FUNC_MIIM_IRQ] = "miim_irq",
+ [FUNC_PCIE_PERST] = "pcie_perst",
+ [FUNC_PTPSYNC_0] = "ptpsync_0",
+ [FUNC_PTPSYNC_1] = "ptpsync_1",
+ [FUNC_PTPSYNC_2] = "ptpsync_2",
+ [FUNC_PTPSYNC_3] = "ptpsync_3",
+ [FUNC_PTPSYNC_4] = "ptpsync_4",
+ [FUNC_PTPSYNC_5] = "ptpsync_5",
+ [FUNC_PTPSYNC_6] = "ptpsync_6",
+ [FUNC_PTPSYNC_7] = "ptpsync_7",
+ [FUNC_QSPI1] = "qspi1",
+ [FUNC_R] = "reserved",
+ [FUNC_SD] = "sd",
+ [FUNC_SFP_SD] = "sfp_sd",
+ [FUNC_SGPIO_a] = "sgpio_a",
+ [FUNC_SYNCE] = "synce",
+ [FUNC_TWI] = "twi",
+ [FUNC_USB_POWER] = "usb_power",
+ [FUNC_USB2PHY_RST] = "usb2phy_rst",
+ [FUNC_USB_OVER_DETECT] = "usb_over_detect",
+ [FUNC_USB_ULPI] = "usb_ulpi",
+ [FUNC_EMMC_SD] = "emmc_sd",
+};
+
+struct lan969x_pin_caps {
+ unsigned int pin;
+ unsigned char functions[LAN969X_FUNC_PER_PIN];
+};
+
+struct lan969x_pin_data {
+ const char *name;
+ struct lan969x_pin_caps *drv_data;
+};
+
+#define LAN969X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \
+static struct lan969x_pin_caps lan969x_pin_##p = { \
+ .pin = p, \
+ .functions = { \
+ FUNC_##f0, FUNC_##f1, FUNC_##f2, \
+ FUNC_##f3, FUNC_##f4, FUNC_##f5, \
+ FUNC_##f6, FUNC_##f7 \
+ }, \
+}
+
+#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
+
+struct lan969x_pmx_func {
+ const char **groups;
+ unsigned int ngroups;
+};
+
+struct lan969x_pinctrl {
+ struct udevice *dev;
+ struct pinctrl_dev *pctl;
+ struct regmap *map;
+ void __iomem *pincfg;
+ struct lan969x_pmx_func *func;
+ int num_func;
+ const struct lan969x_pin_data *lan969x_pins;
+ int num_pins;
+ const char * const *function_names;
+ const unsigned long *lan969x_gpios;
+ u8 stride;
+};
+
+/* Pinmuxing table taken from data sheet */
+/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */
+LAN969X_P(0, GPIO, IRQ0, FC_SHRD, PCIE_PERST, NONE, NONE, NONE, R);
+LAN969X_P(1, GPIO, IRQ1, FC_SHRD, USB_POWER, NONE, NONE, NONE, R);
+LAN969X_P(2, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R);
+LAN969X_P(3, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R);
+LAN969X_P(4, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R);
+LAN969X_P(5, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);
+LAN969X_P(6, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);
+LAN969X_P(7, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);
+LAN969X_P(8, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);
+LAN969X_P(9, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R);
+LAN969X_P(10, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R);
+LAN969X_P(11, GPIO, MIIM_IRQ, MIIM_Sa, CLKMON, NONE, NONE, NONE, R);
+LAN969X_P(12, GPIO, IRQ3, FC_SHRD, USB2PHY_RST, NONE, NONE, NONE, R);
+LAN969X_P(13, GPIO, IRQ4, FC_SHRD, USB_OVER_DETECT, NONE, NONE, NONE, R);
+LAN969X_P(14, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R);
+LAN969X_P(15, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R);
+LAN969X_P(16, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R);
+LAN969X_P(17, GPIO, EMMC_SD, QSPI1, PTPSYNC_0, USB_POWER, NONE, NONE, R);
+LAN969X_P(18, GPIO, EMMC_SD, QSPI1, PTPSYNC_1, USB2PHY_RST, NONE, NONE, R);
+LAN969X_P(19, GPIO, EMMC_SD, QSPI1, PTPSYNC_2, USB_OVER_DETECT, NONE, NONE, R);
+LAN969X_P(20, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);
+LAN969X_P(21, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);
+LAN969X_P(22, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);
+LAN969X_P(23, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);
+LAN969X_P(24, GPIO, EMMC_SD, NONE, NONE, NONE, NONE, NONE, R);
+LAN969X_P(25, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R);
+LAN969X_P(26, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R);
+LAN969X_P(27, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R);
+LAN969X_P(28, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R);
+LAN969X_P(29, GPIO, SYNCE, FC, MIIM_IRQ, QSPI1, NONE, NONE, R);
+LAN969X_P(30, GPIO, PTPSYNC_0, USB_ULPI, FC_SHRD, QSPI1, NONE, NONE, R);
+LAN969X_P(31, GPIO, PTPSYNC_1, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R);
+LAN969X_P(32, GPIO, PTPSYNC_2, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R);
+LAN969X_P(33, GPIO, SD, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R);
+LAN969X_P(34, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R);
+LAN969X_P(35, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R);
+LAN969X_P(36, GPIO, SD, USB_ULPI, PCIE_PERST, FC_SHRD, NONE, NONE, R);
+LAN969X_P(37, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R);
+LAN969X_P(38, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R);
+LAN969X_P(39, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R);
+LAN969X_P(40, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R);
+LAN969X_P(41, GPIO, SD, USB_ULPI, MIIM_IRQ, NONE, NONE, NONE, R);
+LAN969X_P(42, GPIO, PTPSYNC_3, CAN1, NONE, NONE, NONE, NONE, R);
+LAN969X_P(43, GPIO, PTPSYNC_4, CAN1, NONE, NONE, NONE, NONE, R);
+LAN969X_P(44, GPIO, PTPSYNC_5, SFP_SD, NONE, NONE, NONE, NONE, R);
+LAN969X_P(45, GPIO, PTPSYNC_6, SFP_SD, NONE, NONE, NONE, NONE, R);
+LAN969X_P(46, GPIO, PTPSYNC_7, SFP_SD, NONE, NONE, NONE, NONE, R);
+LAN969X_P(47, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);
+LAN969X_P(48, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);
+LAN969X_P(49, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);
+LAN969X_P(50, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);
+LAN969X_P(51, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);
+LAN969X_P(52, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R);
+LAN969X_P(53, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R);
+LAN969X_P(54, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R);
+LAN969X_P(55, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R);
+LAN969X_P(56, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R);
+LAN969X_P(57, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_3, NONE, NONE, R);
+LAN969X_P(58, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_4, NONE, NONE, R);
+LAN969X_P(59, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_5, NONE, NONE, R);
+LAN969X_P(60, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_6, NONE, NONE, R);
+LAN969X_P(61, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R);
+LAN969X_P(62, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R);
+LAN969X_P(63, GPIO, MIIM_IRQ, FC_SHRD, TWI, NONE, NONE, NONE, R);
+LAN969X_P(64, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R);
+LAN969X_P(65, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R);
+LAN969X_P(66, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R);
+
+#define LAN969X_PIN(n) { \
+ .name = "GPIO_"#n, \
+ .drv_data = &lan969x_pin_##n \
+}
+
+static const struct lan969x_pin_data lan969x_pins[] = {
+ LAN969X_PIN(0),
+ LAN969X_PIN(1),
+ LAN969X_PIN(2),
+ LAN969X_PIN(3),
+ LAN969X_PIN(4),
+ LAN969X_PIN(5),
+ LAN969X_PIN(6),
+ LAN969X_PIN(7),
+ LAN969X_PIN(8),
+ LAN969X_PIN(9),
+ LAN969X_PIN(10),
+ LAN969X_PIN(11),
+ LAN969X_PIN(12),
+ LAN969X_PIN(13),
+ LAN969X_PIN(14),
+ LAN969X_PIN(15),
+ LAN969X_PIN(16),
+ LAN969X_PIN(17),
+ LAN969X_PIN(18),
+ LAN969X_PIN(19),
+ LAN969X_PIN(20),
+ LAN969X_PIN(21),
+ LAN969X_PIN(22),
+ LAN969X_PIN(23),
+ LAN969X_PIN(24),
+ LAN969X_PIN(25),
+ LAN969X_PIN(26),
+ LAN969X_PIN(27),
+ LAN969X_PIN(28),
+ LAN969X_PIN(29),
+ LAN969X_PIN(30),
+ LAN969X_PIN(31),
+ LAN969X_PIN(32),
+ LAN969X_PIN(33),
+ LAN969X_PIN(34),
+ LAN969X_PIN(35),
+ LAN969X_PIN(36),
+ LAN969X_PIN(37),
+ LAN969X_PIN(38),
+ LAN969X_PIN(39),
+ LAN969X_PIN(40),
+ LAN969X_PIN(41),
+ LAN969X_PIN(42),
+ LAN969X_PIN(43),
+ LAN969X_PIN(44),
+ LAN969X_PIN(45),
+ LAN969X_PIN(46),
+ LAN969X_PIN(47),
+ LAN969X_PIN(48),
+ LAN969X_PIN(49),
+ LAN969X_PIN(50),
+ LAN969X_PIN(51),
+ LAN969X_PIN(52),
+ LAN969X_PIN(53),
+ LAN969X_PIN(54),
+ LAN969X_PIN(55),
+ LAN969X_PIN(56),
+ LAN969X_PIN(57),
+ LAN969X_PIN(58),
+ LAN969X_PIN(59),
+ LAN969X_PIN(60),
+ LAN969X_PIN(61),
+ LAN969X_PIN(62),
+ LAN969X_PIN(63),
+ LAN969X_PIN(64),
+ LAN969X_PIN(65),
+ LAN969X_PIN(66),
+};
+
+static int lan969x_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "lan969x-gpio";
+ uc_priv->gpio_count = ARRAY_SIZE(lan969x_pins);
+
+ return 0;
+}
+
+static int lan969x_gpio_get(struct udevice *dev, unsigned int offset)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev->parent);
+ unsigned int val;
+
+ regmap_read(info->map, REG(LAN969X_GPIO_IN, info, offset), &val);
+
+ return !!(val & BIT(offset % 32));
+}
+
+static int lan969x_gpio_set(struct udevice *dev, unsigned int offset, int value)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev->parent);
+
+ if (value)
+ regmap_write(info->map, REG(LAN969X_GPIO_OUT_SET, info, offset),
+ BIT(offset % 32));
+ else
+ regmap_write(info->map, REG(LAN969X_GPIO_OUT_CLR, info, offset),
+ BIT(offset % 32));
+
+ return 0;
+}
+
+static int lan969x_gpio_get_direction(struct udevice *dev, unsigned int offset)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev->parent);
+ unsigned int val;
+
+ regmap_read(info->map, REG(LAN969X_GPIO_OE, info, offset), &val);
+
+ if (val & BIT(offset % 32))
+ return GPIOF_OUTPUT;
+
+ return GPIOF_INPUT;
+}
+
+static int lan969x_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev->parent);
+
+ regmap_write(info->map, REG(LAN969X_GPIO_OE, info, offset),
+ ~BIT(offset % 32));
+
+ return 0;
+}
+
+static int lan969x_gpio_direction_output(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev->parent);
+
+ regmap_write(info->map, REG(LAN969X_GPIO_OE, info, offset),
+ BIT(offset % 32));
+
+ return lan969x_gpio_set(dev, offset, value);
+}
+
+const struct dm_gpio_ops lan969x_gpio_ops = {
+ .set_value = lan969x_gpio_set,
+ .get_value = lan969x_gpio_get,
+ .get_function = lan969x_gpio_get_direction,
+ .direction_input = lan969x_gpio_direction_input,
+ .direction_output = lan969x_gpio_direction_output,
+};
+
+static int lan969x_pctl_get_groups_count(struct udevice *dev)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev);
+
+ return info->num_pins;
+}
+
+static const char *lan969x_pctl_get_group_name(struct udevice *dev,
+ unsigned int group)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev);
+
+ return info->lan969x_pins[group].name;
+}
+
+static int lan969x_get_functions_count(struct udevice *dev)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev);
+
+ return info->num_func;
+}
+
+static const char *lan969x_get_function_name(struct udevice *dev,
+ unsigned int function)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev);
+
+ return info->function_names[function];
+}
+
+static int lan969x_pin_function_idx(unsigned int pin, unsigned int function,
+ const struct lan969x_pin_data *lan969x_pins)
+{
+ struct lan969x_pin_caps *p = lan969x_pins[pin].drv_data;
+ int i;
+
+ for (i = 0; i < LAN969X_FUNC_PER_PIN; i++) {
+ if (function == p->functions[i])
+ return i;
+ }
+
+ return -1;
+}
+
+#define REG_ALT(msb, info, p) (LAN969X_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
+
+static int lan969x_pinmux_set_mux(struct udevice *dev,
+ unsigned int pin_selector, unsigned int selector)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev);
+ struct lan969x_pin_caps *pin = info->lan969x_pins[pin_selector].drv_data;
+ unsigned int p = pin->pin % 32;
+ int f;
+
+ f = lan969x_pin_function_idx(pin_selector, selector, info->lan969x_pins);
+ if (f < 0)
+ return -EINVAL;
+
+ /*
+ * f is encoded on two bits.
+ * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
+ * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2]
+ * This is racy because both registers can't be updated at the same time
+ * but it doesn't matter much for now.
+ * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets
+ */
+ regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
+ BIT(p), f << p);
+ regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
+ BIT(p), (f >> 1) << p);
+ regmap_update_bits(info->map, REG_ALT(2, info, pin->pin),
+ BIT(p), (f >> 2) << p);
+
+ return 0;
+}
+
+/* Non-constant mask variant of FIELD_GET */
+#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
+
+static int lan969x_get_pin_muxing(struct udevice *dev, unsigned int selector,
+ char *buf, int size)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev);
+ struct lan969x_pin_caps *pin = info->lan969x_pins[selector].drv_data;
+ unsigned int alt0, alt1, alt2, function = 0;
+
+ regmap_read(info->map, REG_ALT(0, info, pin->pin), &alt0);
+ regmap_read(info->map, REG_ALT(1, info, pin->pin), &alt1);
+ regmap_read(info->map, REG_ALT(2, info, pin->pin), &alt2);
+
+ function |= FIELD_PREP(BIT(0), field_get(BIT(pin->pin), alt0));
+ function |= FIELD_PREP(BIT(1), field_get(BIT(pin->pin), alt1));
+ function |= FIELD_PREP(BIT(2), field_get(BIT(pin->pin), alt2));
+
+ snprintf(buf, size, "%s", lan969x_get_function_name(dev, pin->functions[function]));
+ return 0;
+}
+
+#if CONFIG_IS_ENABLED(PINCONF)
+static const struct pinconf_param lan969x_pinconf_params[] = {
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 0 },
+ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
+};
+
+static int lan969x_pinconf_set(struct udevice *dev, unsigned int pin,
+ unsigned int param, unsigned int arg)
+{
+ struct lan969x_pinctrl *info = dev_get_priv(dev);
+ unsigned int val;
+ int err = 0;
+
+ if (info->pincfg == NULL)
+ return err;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ val = readl(info->pincfg + (pin * 4));
+ val &= ~(BIT(3) | BIT(2));
+ val |= (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
+ (param == PIN_CONFIG_BIAS_PULL_UP) ? BIT(3) : BIT(2);
+ writel(val, info->pincfg + (pin * 4));
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ if (arg <= 3) {
+ val = readl(info->pincfg + (pin * 4));
+ val &= ~GENMASK(1, 0);
+ val |= arg;
+ writel(val, info->pincfg + (pin * 4));
+ } else {
+ err = -EINVAL;
+ }
+ break;
+ default:
+ err = -ENOTSUPP;
+ }
+
+ return err;
+}
+#endif
+
+const struct pinctrl_ops lan969x_pinctrl_ops = {
+ .get_pins_count = lan969x_pctl_get_groups_count,
+ .get_pin_name = lan969x_pctl_get_group_name,
+ .get_pin_muxing = lan969x_get_pin_muxing,
+ .get_functions_count = lan969x_get_functions_count,
+ .get_function_name = lan969x_get_function_name,
+ .pinmux_set = lan969x_pinmux_set_mux,
+ .set_state = pinctrl_generic_set_state,
+#if CONFIG_IS_ENABLED(PINCONF)
+ .pinconf_num_params = ARRAY_SIZE(lan969x_pinconf_params),
+ .pinconf_params = lan969x_pinconf_params,
+ .pinconf_set = lan969x_pinconf_set,
+#endif
+};
+
+static struct driver lan969x_gpio_driver = {
+ .name = "lan969x-gpio",
+ .id = UCLASS_GPIO,
+ .probe = lan969x_gpio_probe,
+ .ops = &lan969x_gpio_ops,
+};
+
+int lan969x_pinctrl_probe(struct udevice *dev)
+{
+ struct lan969x_pinctrl *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
+ if (ret)
+ return -EINVAL;
+
+ priv->pincfg = dev_remap_addr_index(dev, 1);
+
+ priv->func = devm_kzalloc(dev, FUNC_MAX * sizeof(struct lan969x_pmx_func), GFP_KERNEL);
+ priv->num_func = FUNC_MAX;
+ priv->function_names = lan969x_function_names;
+
+ priv->lan969x_pins = lan969x_pins;
+ priv->num_pins = ARRAY_SIZE(lan969x_pins);
+ priv->stride = 1 + (priv->num_pins - 1) / 32;
+
+ ret = device_bind(dev, &lan969x_gpio_driver, "lan969x-gpio", NULL,
+ dev_ofnode(dev), NULL);
+
+ return ret;
+}
+
+static const struct udevice_id lan969x_pinctrl_of_match[] = {
+ {.compatible = "microchip,lan9691-pinctrl"},
+ {},
+};
+
+U_BOOT_DRIVER(lan969x_pinctrl) = {
+ .name = "lan969x-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(lan969x_pinctrl_of_match),
+ .probe = lan969x_pinctrl_probe,
+ .priv_auto = sizeof(struct lan969x_pinctrl),
+ .ops = &lan969x_pinctrl_ops,
+};
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 03/14] clk: add Microchip LAN966x and LAN969x support
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
2026-03-26 11:26 ` [PATCH 02/14] pinctrl: add Microchip LAN969x driver Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 04/14] mmc: atmel: remove duplicate depends on ARCH_AT91 Robert Marko
` (11 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
Import clock driver for Microchip LAN966x and LAN969x SoC-s from the vendor
U-Boot as it is based on the upstream Linux driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/clk/Makefile | 2 +-
drivers/clk/microchip/Kconfig | 7 +
drivers/clk/microchip/Makefile | 3 +-
drivers/clk/microchip/clk-lan966x.c | 198 ++++++++++++++++++++++++++++
4 files changed, 208 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/microchip/clk-lan966x.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5f0c0d8a5c2..88b76652378 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -39,7 +39,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_K210) += clk_k210.o
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
-obj-$(CONFIG_CLK_MPFS) += microchip/
+obj-y += microchip/
obj-$(CONFIG_CLK_MVEBU) += mvebu/
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
index 62072e100b1..275cd849fec 100644
--- a/drivers/clk/microchip/Kconfig
+++ b/drivers/clk/microchip/Kconfig
@@ -1,3 +1,10 @@
+config CLK_LAN966X
+ bool "Microchip LAN966X and LAN969X clock support"
+ depends on ARCH_MICROCHIPSW
+ depends on CLK
+ help
+ Clock driver for Microchip LAN969X platforms.
+
config CLK_MPFS
bool "Clock support for Microchip PolarFire SoC"
depends on CLK && CLK_CCF
diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
index 329b2c0c93f..bce4cbebd69 100644
--- a/drivers/clk/microchip/Makefile
+++ b/drivers/clk/microchip/Makefile
@@ -1 +1,2 @@
-obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o mpfs_clk_msspll.o
+obj-$(CONFIG_CLK_LAN966X) += clk-lan966x.o
+obj-$(CONFIG_CLK_MPFS) += += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o mpfs_clk_msspll.o
diff --git a/drivers/clk/microchip/clk-lan966x.c b/drivers/clk/microchip/clk-lan966x.c
new file mode 100644
index 00000000000..1d704af006c
--- /dev/null
+++ b/drivers/clk/microchip/clk-lan966x.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <linux/bitfield.h>
+
+#define GCK_ENA BIT(0)
+#define GCK_SRC_SEL GENMASK(9, 8)
+#define GCK_PRESCALER GENMASK(23, 16)
+
+struct lan966x_soc_clk_gate_desc {
+ const char *name;
+ int bit_idx;
+};
+
+static const struct lan966x_soc_clk_gate_desc lan966x_clk_gate_desc[] = {
+ { "uhphs", 11 },
+ { "udphs", 10 },
+ { "mcramc", 9 },
+ { "hmatrix", 8 },
+ { }
+};
+
+static const struct lan966x_soc_clk_gate_desc lan969x_clk_gate_desc[] = {
+ { "usb_drd", 10 },
+ { "mcramc", 9 },
+ { "hmatrix", 8 },
+ { }
+};
+
+struct lan966x_clk {
+ void *base;
+ void *gate;
+ int clk_cnt;
+ int clk_gate_cnt;
+ const struct lan966x_soc_clk_gate_desc *clk_gate_desc;
+ ulong parent_rate;
+};
+
+struct lan966x_driver_data {
+ int clk_cnt;
+ int clk_gate_cnt;
+ const struct lan966x_soc_clk_gate_desc *clk_gate_desc;
+ ulong parent_rate;
+};
+
+static struct lan966x_driver_data lan966x_data = {
+ .clk_cnt = 14,
+ .clk_gate_cnt = 4,
+ .clk_gate_desc = lan966x_clk_gate_desc,
+ .parent_rate = 600000000,
+};
+
+static struct lan966x_driver_data lan969x_data = {
+ .clk_cnt = 12,
+ .clk_gate_cnt = 3,
+ .clk_gate_desc = lan969x_clk_gate_desc,
+ .parent_rate = 1000000000,
+};
+
+static void* lan966x_clk_ctlreg(struct lan966x_clk *gck, u8 id)
+{
+ return gck->base + (id * sizeof(u32));
+}
+
+static ulong lan966x_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct lan966x_clk *gck = dev_get_priv(clk->dev);
+ unsigned long parent_rate = gck->parent_rate;
+ u32 div;
+
+ if (clk->id >= gck->clk_cnt)
+ return -ENODEV;
+
+ if (rate == 0)
+ return -EINVAL;
+
+ /* Calc divisor */
+ div = DIV_ROUND_CLOSEST(parent_rate, rate);
+
+ /* Set src, prescaler */
+ clrsetbits_le32(lan966x_clk_ctlreg(gck, clk->id),
+ GCK_SRC_SEL | GCK_PRESCALER,
+ /* Select CPU_CLK as source always */
+ FIELD_PREP(GCK_SRC_SEL, 0x0) |
+ /* Divisor - 1 */
+ FIELD_PREP(GCK_PRESCALER, (div - 1)));
+
+ return 0;
+}
+
+static ulong lan966x_clk_get_rate(struct clk *clk)
+{
+ struct lan966x_clk *gck = dev_get_priv(clk->dev);
+ unsigned long parent_rate = gck->parent_rate;
+ u32 div, val;
+
+ if (clk->id >= gck->clk_cnt)
+ return -ENODEV;
+
+ val = readl(lan966x_clk_ctlreg(gck, clk->id));
+
+ div = 1 + FIELD_GET(GCK_PRESCALER, val);
+
+ return parent_rate / div;
+}
+
+static int lan966x_clk_enable(struct clk *clk)
+{
+ struct lan966x_clk *gck = dev_get_priv(clk->dev);
+
+ if (clk->id >= gck->clk_cnt) {
+ /* If there are no gate clock then this is not allowed */
+ if (gck->gate == NULL)
+ return -ENODEV;
+
+ if (clk->id >= gck->clk_cnt + gck->clk_gate_cnt)
+ return -ENODEV;
+
+ setbits_le32(gck->gate,
+ BIT(gck->clk_gate_desc[clk->id - gck->clk_cnt].bit_idx));
+
+ return 0;
+ }
+
+ setbits_le32(lan966x_clk_ctlreg(gck, clk->id), GCK_ENA);
+
+ return 0;
+}
+
+static int lan966x_clk_disable(struct clk *clk)
+{
+ struct lan966x_clk *gck = dev_get_priv(clk->dev);
+
+ if (clk->id >= gck->clk_cnt) {
+ /* If there are no gate clock then this is not allowed */
+ if (gck->gate == NULL)
+ return -ENODEV;
+
+ if (clk->id >= gck->clk_cnt + gck->clk_gate_cnt)
+ return -ENODEV;
+
+ clrbits_le32(gck->gate, BIT(gck->clk_gate_desc[clk->id - gck->clk_cnt].bit_idx));
+
+ return 0;
+ }
+
+ clrbits_le32(lan966x_clk_ctlreg(gck, clk->id), GCK_ENA);
+
+ return 0;
+}
+
+static int lan966x_clk_probe(struct udevice *dev)
+{
+ struct lan966x_clk *priv = dev_get_priv(dev);
+ struct lan966x_driver_data *data;
+
+ priv->base = dev_remap_addr(dev);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->gate = dev_remap_addr_index(dev, 1);
+
+ /* Get clock count for target device */
+ data = (struct lan966x_driver_data*)dev_get_driver_data(dev);
+ priv->clk_cnt = data->clk_cnt;
+ priv->clk_gate_cnt = data->clk_gate_cnt;
+ priv->clk_gate_desc = data->clk_gate_desc;
+ priv->parent_rate = data->parent_rate;
+
+ return 0;
+}
+
+static struct clk_ops lan966x_clk_ops = {
+ .disable = lan966x_clk_disable,
+ .enable = lan966x_clk_enable,
+ .get_rate = lan966x_clk_get_rate,
+ .set_rate = lan966x_clk_set_rate,
+};
+
+static const struct udevice_id lan966x_clk_ids[] = {
+ { .compatible = "microchip,lan966x-gck", .data = (unsigned long)&lan966x_data },
+ { .compatible = "microchip,lan9691-gck", .data = (unsigned long)&lan969x_data },
+ { }
+};
+
+U_BOOT_DRIVER(lan966x_clk) = {
+ .name = "lan966x_clk",
+ .id = UCLASS_CLK,
+ .of_match = lan966x_clk_ids,
+ .priv_auto = sizeof(struct lan966x_clk),
+ .ops = &lan966x_clk_ops,
+ .probe = lan966x_clk_probe,
+};
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 04/14] mmc: atmel: remove duplicate depends on ARCH_AT91
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
2026-03-26 11:26 ` [PATCH 02/14] pinctrl: add Microchip LAN969x driver Robert Marko
2026-03-26 11:26 ` [PATCH 03/14] clk: add Microchip LAN966x and LAN969x support Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 05/14] mmc: atmel-sdhci: set GCK rate based on compatible Robert Marko
` (10 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
Dependency on ARCH_AT91 is duplicated, so drop the extra one.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/mmc/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 39caf2eff1b..9b77b8c619d 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -566,7 +566,6 @@ config MMC_SDHCI_ASPEED
config MMC_SDHCI_ATMEL
bool "Atmel SDHCI controller support"
depends on ARCH_AT91
- depends on ARCH_AT91
depends on MMC_SDHCI
help
This enables support for the Atmel SDHCI controller, which supports
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 05/14] mmc: atmel-sdhci: set GCK rate based on compatible
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (2 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 04/14] mmc: atmel: remove duplicate depends on ARCH_AT91 Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 06/14] mmc: atmel-sdhci: include arch specific clk.h only for AT91 Robert Marko
` (9 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
In order to add support for LAN969x we need to set the GCK rate based on
compatible instead of defaulting to 240000000 Hz as LAN969x uses only
100000000 Hz.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/mmc/atmel_sdhci.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index 0b265196f02..f3a030ffde5 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -96,6 +96,7 @@ static int atmel_sdhci_probe(struct udevice *dev)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct atmel_sdhci_plat *plat = dev_get_plat(dev);
struct sdhci_host *host = dev_get_priv(dev);
+ u32 gck_rate = dev_get_driver_data(dev);
u32 max_clk;
struct clk clk;
int ret;
@@ -119,7 +120,7 @@ static int atmel_sdhci_probe(struct udevice *dev)
if (ret)
return ret;
- clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
+ clk_set_rate(&clk, gck_rate);
max_clk = clk_get_rate(&clk);
if (!max_clk)
@@ -163,9 +164,9 @@ static int atmel_sdhci_bind(struct udevice *dev)
}
static const struct udevice_id atmel_sdhci_ids[] = {
- { .compatible = "atmel,sama5d2-sdhci" },
- { .compatible = "microchip,sam9x60-sdhci" },
- { .compatible = "microchip,sama7g5-sdhci" },
+ { .compatible = "atmel,sama5d2-sdhci", .data = ATMEL_SDHC_GCK_RATE },
+ { .compatible = "microchip,sam9x60-sdhci", .data = ATMEL_SDHC_GCK_RATE },
+ { .compatible = "microchip,sama7g5-sdhci", .data = ATMEL_SDHC_GCK_RATE },
{ }
};
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 06/14] mmc: atmel-sdhci: include arch specific clk.h only for AT91
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (3 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 05/14] mmc: atmel-sdhci: set GCK rate based on compatible Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 07/14] mmc: atmel-sdhci: add support for LAN969x Robert Marko
` (8 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
Microchip LAN969x will not include any arch specific clk.h, so in order to
support it only include <asm/arch/clk.h> when AT91 is selected.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/mmc/atmel_sdhci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index f3a030ffde5..2b6d64d1425 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -8,7 +8,9 @@
#include <dm.h>
#include <malloc.h>
#include <sdhci.h>
+#if IS_ENABLED(CONFIG_ARCH_AT91)
#include <asm/arch/clk.h>
+#endif
#include <asm/global_data.h>
#define ATMEL_SDHC_MIN_FREQ 400000
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 07/14] mmc: atmel-sdhci: add support for LAN969x
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (4 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 06/14] mmc: atmel-sdhci: include arch specific clk.h only for AT91 Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 08/14] i2c: at91-i2c: include arch specific clk.h only for AT91 Robert Marko
` (7 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
LAN969x is compatible with the existing driver, however it requires the
GCK clock rate to be set to 100000000 Hz instead.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/mmc/Kconfig | 2 +-
drivers/mmc/atmel_sdhci.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 9b77b8c619d..b238d5c2894 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -565,7 +565,7 @@ config MMC_SDHCI_ASPEED
config MMC_SDHCI_ATMEL
bool "Atmel SDHCI controller support"
- depends on ARCH_AT91
+ depends on ARCH_AT91 || ARCH_MICROCHIPSW
depends on MMC_SDHCI
help
This enables support for the Atmel SDHCI controller, which supports
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index 2b6d64d1425..712405e3262 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -15,6 +15,7 @@
#define ATMEL_SDHC_MIN_FREQ 400000
#define ATMEL_SDHC_GCK_RATE 240000000
+#define LAN969X_GCK_RATE 100000000
#define ATMEL_SDHC_MC1R 0x204
#define ATMEL_SDHC_MC1R_FCD 0x80
@@ -169,6 +170,7 @@ static const struct udevice_id atmel_sdhci_ids[] = {
{ .compatible = "atmel,sama5d2-sdhci", .data = ATMEL_SDHC_GCK_RATE },
{ .compatible = "microchip,sam9x60-sdhci", .data = ATMEL_SDHC_GCK_RATE },
{ .compatible = "microchip,sama7g5-sdhci", .data = ATMEL_SDHC_GCK_RATE },
+ { .compatible = "microchip,lan9691-sdhci", .data = LAN969X_GCK_RATE },
{ }
};
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 08/14] i2c: at91-i2c: include arch specific clk.h only for AT91
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (5 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 07/14] mmc: atmel-sdhci: add support for LAN969x Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 09/14] i2c: i2c-at91: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (6 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
Microchip LAN969x will not include any arch specific clk.h, so in order to
support it only include <asm/arch/clk.h> when AT91 is selected.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/i2c/at91_i2c.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/i2c/at91_i2c.c b/drivers/i2c/at91_i2c.c
index cfae36c74d1..6c002b21e6c 100644
--- a/drivers/i2c/at91_i2c.c
+++ b/drivers/i2c/at91_i2c.c
@@ -14,7 +14,9 @@
#include <fdtdec.h>
#include <i2c.h>
#include <linux/bitops.h>
+#if IS_ENABLED(CONFIG_ARCH_AT91)
#include <mach/clk.h>
+#endif
#include "at91_i2c.h"
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 09/14] i2c: i2c-at91: allow selecting from ARCH_MICROCHIPSW
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (6 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 08/14] i2c: at91-i2c: include arch specific clk.h only for AT91 Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 10/14] usb: dwc3-generic: add support for Microchip LAN969x Robert Marko
` (5 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
AT91 I2C driver is reused by a lot of Microchip platforms, in this case we
need it for LAN969x so allow selecting it when ARCH_MICROCHIPSW is used.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/i2c/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 55465dc1d46..d7d3b4d0484 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -163,7 +163,8 @@ config SYS_I2C_ADI
config SYS_I2C_AT91
bool "Atmel I2C driver"
- depends on DM_I2C && ARCH_AT91
+ depends on DM_I2C
+ depends on ARCH_AT91 || ARCH_MICROCHIPSW
help
Add support for the Atmel I2C driver. A serious problem is that there
is no documented way to issue repeated START conditions for more than
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 10/14] usb: dwc3-generic: add support for Microchip LAN969x
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (7 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 09/14] i2c: i2c-at91: allow selecting from ARCH_MICROCHIPSW Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 11/14] spi: atmel-quadspi: add Microchip LAN969x support Robert Marko
` (4 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
Add Microchip LAN969x support, by using rk_ops as LAN969x uses single
node to describe glue and ctrl.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/usb/dwc3/dwc3-generic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 22b9ef0b24e..f0506be46c0 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -731,6 +731,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "intel,tangier-dwc3" },
{ .compatible = "samsung,exynos7870-dwusb3" },
{ .compatible = "samsung,exynos850-dwusb3" },
+ { .compatible = "microchip,lan9691-dwc3", .data = (ulong)&rk_ops },
{ }
};
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 11/14] spi: atmel-quadspi: add Microchip LAN969x support
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (8 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 10/14] usb: dwc3-generic: add support for Microchip LAN969x Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 12/14] net: add Microchip SparX-5 and " Robert Marko
` (3 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
Add support for Microchip LAN969x SoC-s.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/spi/Kconfig | 3 ++-
drivers/spi/atmel-quadspi.c | 11 +++++++++++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8c6c095a8cf..f837568c482 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -102,7 +102,8 @@ config ATH79_SPI
config ATMEL_QSPI
bool "Atmel Quad SPI Controller"
- depends on ARCH_AT91 && SPI_MEM
+ depends on ARCH_AT91 || ARCH_MICROCHIPSW
+ depends on SPI_MEM
help
Enable the Atmel Quad SPI controller in master mode. This driver
does not support generic SPI. The implementation supports only the
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index b2b96e1c4b9..d830c2cd5bd 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -24,7 +24,9 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
+#if IS_ENABLED(CONFIG_ARCH_AT91)
#include <mach/clk.h>
+#endif
#include <spi.h>
#include <spi-mem.h>
@@ -1311,6 +1313,11 @@ static const struct atmel_qspi_caps atmel_sama7g5_qspi_caps = {
.has_gclk = true,
};
+static const struct atmel_qspi_caps microchip_lan9691_qspi_caps = {
+ .has_gclk = true,
+ .has_ricr = true,
+};
+
static const struct udevice_id atmel_qspi_ids[] = {
{
.compatible = "atmel,sama5d2-qspi",
@@ -1328,6 +1335,10 @@ static const struct udevice_id atmel_qspi_ids[] = {
.compatible = "microchip,sama7g5-qspi",
.data = (ulong)&atmel_sama7g5_qspi_caps,
},
+ {
+ .compatible = "microchip,lan9691-qspi",
+ .data = (ulong)µchip_lan9691_qspi_caps,
+ },
{ /* sentinel */ }
};
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 12/14] net: add Microchip SparX-5 and LAN969x support
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (9 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 11/14] spi: atmel-quadspi: add Microchip LAN969x support Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-03-26 11:26 ` [PATCH 13/14] net: phy: add Microchip LAN8841 support Robert Marko
` (2 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
Add support for Microchip SparX-5 and LAN969x networking.
Currently, only the "management" ports via RGMII are supported.
Driver is imported from Microchip BSP U-Boot[1] but updated to use
DM_MDIO, modernised parsing of DT properties, PHY connections etc.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/mscc_eswitch/Kconfig | 7 +
drivers/net/mscc_eswitch/Makefile | 1 +
drivers/net/mscc_eswitch/sparx5_reg_offset.c | 353 ++
drivers/net/mscc_eswitch/sparx5_reg_offset.h | 201 ++
drivers/net/mscc_eswitch/sparx5_regs.h | 701 ++++
drivers/net/mscc_eswitch/sparx5_serdes.c | 2703 +++++++++++++++
drivers/net/mscc_eswitch/sparx5_serdes.h | 69 +
drivers/net/mscc_eswitch/sparx5_serdes_priv.h | 130 +
drivers/net/mscc_eswitch/sparx5_serdes_regs.h | 3047 +++++++++++++++++
drivers/net/mscc_eswitch/sparx5_switch.c | 1181 +++++++
drivers/net/mscc_eswitch/sparx5_switch.h | 69 +
include/dt-bindings/mscc/sparx5_data.h | 19 +
12 files changed, 8481 insertions(+)
create mode 100644 drivers/net/mscc_eswitch/sparx5_reg_offset.c
create mode 100644 drivers/net/mscc_eswitch/sparx5_reg_offset.h
create mode 100644 drivers/net/mscc_eswitch/sparx5_regs.h
create mode 100644 drivers/net/mscc_eswitch/sparx5_serdes.c
create mode 100644 drivers/net/mscc_eswitch/sparx5_serdes.h
create mode 100644 drivers/net/mscc_eswitch/sparx5_serdes_priv.h
create mode 100644 drivers/net/mscc_eswitch/sparx5_serdes_regs.h
create mode 100644 drivers/net/mscc_eswitch/sparx5_switch.c
create mode 100644 drivers/net/mscc_eswitch/sparx5_switch.h
create mode 100644 include/dt-bindings/mscc/sparx5_data.h
diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig
index f9780661c80..ed07c95ab15 100644
--- a/drivers/net/mscc_eswitch/Kconfig
+++ b/drivers/net/mscc_eswitch/Kconfig
@@ -44,3 +44,10 @@ config MSCC_FELIX_SWITCH
help
This driver supports the Ethernet switch integrated in the
NXP LS1028A SoC.
+
+config MSCC_LAN969X_SWITCH
+ bool "Microchip LAN966X switch driver"
+ depends on DM_ETH && TARGET_LAN969X
+ select PHYLIB
+ help
+ This driver supports the LAN969X network switch device.
diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile
index 22342ed1141..ffc9b02b43e 100644
--- a/drivers/net/mscc_eswitch/Makefile
+++ b/drivers/net/mscc_eswitch/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o mscc_miim.o
obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o mscc_miim.o
obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o mscc_mac_table.o mscc_miim.o
obj-$(CONFIG_MSCC_FELIX_SWITCH) += felix_switch.o
+obj-$(CONFIG_MSCC_LAN969X_SWITCH) += sparx5_switch.o sparx5_serdes.o sparx5_reg_offset.o mscc_xfer.o
diff --git a/drivers/net/mscc_eswitch/sparx5_reg_offset.c b/drivers/net/mscc_eswitch/sparx5_reg_offset.c
new file mode 100644
index 00000000000..fbb8a0a4453
--- /dev/null
+++ b/drivers/net/mscc_eswitch/sparx5_reg_offset.c
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include "sparx5_reg_offset.h"
+#include <linux/bitops.h>
+
+const unsigned int sparx5_regfield_addr[FIELD_LAST] = {
+ [FIELD_CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE] = BIT(10),
+};
+
+const unsigned int sparx5_reg_addr[RA_LAST] = {
+ [RA_CPU_RESET_PROT_STAT] = 132,
+ [RA_CPU_PROC_CTRL] = 176,
+ [RA_GCB_SOFT_RST] = 8,
+ [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 24,
+ [RA_GCB_GPIO_OUT_CLR] = 8,
+ [RA_GCB_GPIO_OUT_CLR1] = 12,
+ [RA_GCB_GPIO_OUT] = 16,
+ [RA_GCB_GPIO_OUT1] = 20,
+ [RA_GCB_GPIO_IN] = 24,
+ [RA_GCB_GPIO_IN1] = 28,
+ [RA_GCB_GPIO_OE] = 32,
+ [RA_GCB_GPIO_OE1] = 36,
+ [RA_GCB_GPIO_INTR] = 40,
+ [RA_GCB_GPIO_INTR1] = 44,
+ [RA_GCB_GPIO_INTR_ENA] = 48,
+ [RA_GCB_GPIO_INTR_ENA1] = 52,
+ [RA_GCB_GPIO_INTR_IDENT] = 56,
+ [RA_GCB_GPIO_INTR_IDENT1] = 60,
+ [RA_GCB_GPIO_ALT] = 64,
+ [RA_GCB_GPIO_ALT1] = 72,
+};
+
+const unsigned int sparx5_reg_cnt[RC_LAST] = {
+ [RC_ANA_AC_OWN_UPSID] = 3,
+ [RC_ANA_ACL_VCAP_S2_CFG] = 70,
+ [RC_ANA_ACL_OWN_UPSID] = 3,
+ [RC_ANA_AC_POL_POL_ACL_RATE_CFG] = 64,
+ [RC_ANA_AC_POL_POL_ACL_THRES_CFG] = 64,
+ [RC_ANA_AC_POL_POL_ACL_CTRL] = 64,
+ [RC_ANA_AC_POL_POL_PORT_THRES_CFG_0] = 280,
+ [RC_ANA_AC_POL_POL_PORT_THRES_CFG_1] = 280,
+ [RC_ANA_AC_POL_POL_PORT_RATE_CFG] = 280,
+ [RC_ANA_CL_OWN_UPSID] = 3,
+ [RC_ANA_L2_OWN_UPSID] = 3,
+ [RC_ASM_PORT_CFG] = 67,
+ [RC_DSM_BUF_CFG] = 67,
+ [RC_DSM_IPG_SHRINK_CFG] = 67,
+ [RC_DSM_DEV_TX_STOP_WM_CFG] = 67,
+ [RC_DSM_RX_PAUSE_CFG] = 67,
+ [RC_DSM_MAC_CFG] = 67,
+ [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 65,
+ [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 65,
+ [RC_DSM_TAXI_CAL_CFG] = 9,
+ [RC_DSM_PREEMPT_CFG] = 67,
+ [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 65,
+ [RC_HSCH_PORT_MODE] = 70,
+ [RC_QFWD_SWITCH_PORT_MODE] = 70,
+ [RC_QSYS_PAUSE_CFG] = 70,
+ [RC_QSYS_ATOP] = 70,
+ [RC_QSYS_FWD_PRESSURE] = 70,
+ [RC_QSYS_CAL_AUTO] = 7,
+ [RC_REW_OWN_UPSID] = 3,
+ [RC_REW_RTAG_ETAG_CTRL] = 70,
+};
+
+const unsigned int sparx5_reggrp_addr[GA_LAST] = {
+ [GA_ANA_AC_RAM_CTRL] = 839108,
+ [GA_ANA_AC_PS_COMMON] = 894472,
+ [GA_ANA_AC_MIRROR_PROBE] = 893696,
+ [GA_ANA_AC_SRC] = 849920,
+ [GA_ANA_AC_PGID] = 786432,
+ [GA_ANA_AC_PS_STICKY] = 839128,
+ [GA_ANA_AC_PS_STICKY_MASK] = 894824,
+ [GA_ANA_AC_TSN_SF] = 839136,
+ [GA_ANA_AC_TSN_SF_CFG] = 839680,
+ [GA_ANA_AC_TSN_SF_STATUS] = 839072,
+ [GA_ANA_AC_SG_ACCESS] = 839140,
+ [GA_ANA_AC_SG_CONFIG] = 851584,
+ [GA_ANA_AC_SG_STATUS] = 839088,
+ [GA_ANA_AC_SG_STATUS_STICKY] = 839152,
+ [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 851552,
+ [GA_ANA_AC_STAT_CNT_CFG_PORT] = 843776,
+ [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 893792,
+ [GA_ANA_AC_STAT_CNT_CFG_ACL] = 848896,
+ [GA_ANA_ACL_COMMON] = 32768,
+ [GA_ANA_ACL_KEY_SEL] = 34200,
+ [GA_ANA_ACL_CNT_B] = 16384,
+ [GA_ANA_ACL_STICKY] = 36408,
+ [GA_ANA_AC_POL_POL_ALL_CFG] = 75968,
+ [GA_ANA_AC_POL_POL_PORT_CFG] = 65536,
+ [GA_ANA_AC_POL_POL_PORT_CTRL] = 73728,
+ [GA_ANA_AC_POL_COMMON_BDLB] = 79048,
+ [GA_ANA_AC_POL_COMMON_BUM_SLB] = 79056,
+ [GA_ANA_AC_SDLB_LBGRP_TBL] = 295468,
+ [GA_ANA_CL_PORT] = 131072,
+ [GA_ANA_CL_COMMON] = 166912,
+ [GA_ANA_L2_COMMON] = 566024,
+ [GA_ANA_L3_COMMON] = 493632,
+ [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 491460,
+ [GA_ASM_CFG] = 33280,
+ [GA_ASM_PFC_TIMER_CFG] = 34716,
+ [GA_ASM_LBK_WM_CFG] = 34744,
+ [GA_ASM_LBK_MISC_CFG] = 34756,
+ [GA_ASM_RAM_CTRL] = 34832,
+ [GA_DEV2G5_MM_CONFIG] = 216,
+ [GA_DEV2G5_MM_STATISTICS] = 224,
+ [GA_EACL_ES2_KEY_SELECT_PROFILE] = 149504,
+ [GA_EACL_CNT_TBL] = 122880,
+ [GA_EACL_POL_CFG] = 150608,
+ [GA_EACL_ES2_STICKY] = 118696,
+ [GA_EACL_RAM_CTRL] = 118736,
+ [GA_GCB_GPIO] = 480,
+ [GA_GCB_SIO_CTRL] = 876,
+ [GA_HSCH_HSCH_L0_CFG] = 163840,
+ [GA_HSCH_HSCH_DWRR] = 162816,
+ [GA_HSCH_HSCH_MISC] = 163104,
+ [GA_HSCH_HSCH_LEAK_LISTS] = 161664,
+ [GA_HSCH_SYSTEM] = 184000,
+ [GA_HSCH_MMGT] = 162368,
+ [GA_HSCH_TAS_CONFIG] = 162384,
+ [GA_HSCH_TAS_PROFILE_CFG] = 188416,
+ [GA_HSCH_TAS_LIST_CFG] = 161600,
+ [GA_HSCH_TAS_GCL_CFG] = 161584,
+ [GA_HSCH_HSCH_TAS_STATE] = 161580,
+ [GA_PTP_PTP_CFG] = 320,
+ [GA_PTP_PTP_TOD_DOMAINS] = 336,
+ [GA_PTP_PHASE_DETECTOR_CTRL] = 420,
+ [GA_QSYS_CALCFG] = 2304,
+ [GA_QSYS_RAM_CTRL] = 2344,
+ [GA_REW_COMMON] = 387264,
+ [GA_REW_PORT] = 360448,
+ [GA_REW_VOE_PORT_LM_CNT] = 393216,
+ [GA_REW_RAM_CTRL] = 378696,
+ [GA_VOP_RAM_CTRL] = 279176,
+ [GA_XQS_SYSTEM] = 6768,
+ [GA_XQS_QLIMIT_SHR] = 7936,
+};
+
+const unsigned int sparx5_reggrp_cnt[GC_LAST] = {
+ [GC_ANA_AC_SRC] = 102,
+ [GC_ANA_AC_PGID] = 3290,
+ [GC_ANA_AC_TSN_SF_CFG] = 1024,
+ [GC_ANA_AC_STAT_CNT_CFG_PORT] = 70,
+ [GC_ANA_AC_STAT_CNT_CFG_ACL] = 64,
+ [GC_ANA_ACL_KEY_SEL] = 134,
+ [GC_ANA_ACL_CNT_A] = 4096,
+ [GC_ANA_ACL_CNT_B] = 4096,
+ [GC_ANA_AC_POL_POL_PORT_CTRL] = 70,
+ [GC_ANA_AC_SDLB_LBGRP_TBL] = 10,
+ [GC_ANA_AC_SDLB_LBSET_TBL] = 4616,
+ [GC_ANA_CL_PORT] = 70,
+ [GC_ANA_L2_ISDX_LIMIT] = 1536,
+ [GC_ANA_L2_ISDX] = 4096,
+ [GC_ANA_L3_VLAN] = 5120,
+ [GC_ASM_DEV_STATISTICS] = 65,
+ [GC_EACL_ES2_KEY_SELECT_PROFILE] = 138,
+ [GC_EACL_CNT_TBL] = 2048,
+ [GC_GCB_SIO_CTRL] = 3,
+ [GC_HSCH_HSCH_L0_CFG] = 5040,
+ [GC_HSCH_HSCH_CFG] = 5040,
+ [GC_HSCH_HSCH_DWRR] = 72,
+ [GC_HSCH_TAS_PROFILE_CFG] = 100,
+ [GC_PTP_PTP_PINS] = 5,
+ [GC_PTP_PHASE_DETECTOR_CTRL] = 5,
+ [GC_REW_PORT] = 70,
+ [GC_REW_VOE_PORT_LM_CNT] = 520,
+};
+
+const unsigned int sparx5_reggrp_sz[GW_LAST] = {
+ [GW_ANA_AC_SRC] = 16, [GW_ANA_L2_COMMON] = 700,
+ [GW_ASM_CFG] = 1088, [GW_CPU_CPU_REGS] = 204,
+ [GW_FDMA_FDMA] = 428, [GW_GCB_CHIP_REGS] = 424,
+ [GW_HSCH_TAS_CONFIG] = 12, [GW_HSCH_TAS_PROFILE_CFG] = 64,
+ [GW_HSCH_TAS_GCL_CFG] = 8, [GW_PTP_PHASE_DETECTOR_CTRL] = 8,
+ [GW_QSYS_PAUSE_CFG] = 1128,
+ [GW_GCB_GPIO] = 208,
+};
+
+const unsigned int lan969x_regfield_addr[FIELD_LAST] = {
+ [FIELD_CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE] = BIT(5),
+};
+
+const unsigned int lan969x_reg_addr[RA_LAST] = {
+ [RA_CPU_RESET_PROT_STAT] = 136,
+ [RA_CPU_PROC_CTRL] = 160,
+ [RA_GCB_SOFT_RST] = 12,
+ [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20,
+ [RA_GCB_GPIO_OUT_CLR] = 12,
+ [RA_GCB_GPIO_OUT_CLR1] = 16,
+ [RA_GCB_GPIO_OUT] = 24,
+ [RA_GCB_GPIO_OUT1] = 28,
+ [RA_GCB_GPIO_IN] = 36,
+ [RA_GCB_GPIO_IN1] = 40,
+ [RA_GCB_GPIO_OE] = 48,
+ [RA_GCB_GPIO_OE1] = 52,
+ [RA_GCB_GPIO_INTR] = 60,
+ [RA_GCB_GPIO_INTR1] = 64,
+ [RA_GCB_GPIO_INTR_ENA] = 72,
+ [RA_GCB_GPIO_INTR_ENA1] = 76,
+ [RA_GCB_GPIO_INTR_IDENT] = 84,
+ [RA_GCB_GPIO_INTR_IDENT1] = 88,
+ [RA_GCB_GPIO_ALT] = 96,
+ [RA_GCB_GPIO_ALT1] = 108,
+};
+
+const unsigned int lan969x_reg_cnt[RC_LAST] = {
+ [RC_ANA_AC_OWN_UPSID] = 1,
+ [RC_ANA_ACL_VCAP_S2_CFG] = 35,
+ [RC_ANA_ACL_OWN_UPSID] = 1,
+ [RC_ANA_AC_POL_POL_ACL_RATE_CFG] = 32,
+ [RC_ANA_AC_POL_POL_ACL_THRES_CFG] = 32,
+ [RC_ANA_AC_POL_POL_ACL_CTRL] = 32,
+ [RC_ANA_AC_POL_POL_PORT_THRES_CFG_0] = 140,
+ [RC_ANA_AC_POL_POL_PORT_THRES_CFG_1] = 140,
+ [RC_ANA_AC_POL_POL_PORT_RATE_CFG] = 140,
+ [RC_ANA_CL_OWN_UPSID] = 1,
+ [RC_ANA_L2_OWN_UPSID] = 1,
+ [RC_ASM_PORT_CFG] = 32,
+ [RC_DSM_BUF_CFG] = 32,
+ [RC_DSM_IPG_SHRINK_CFG] = 32,
+ [RC_DSM_DEV_TX_STOP_WM_CFG] = 32,
+ [RC_DSM_RX_PAUSE_CFG] = 32,
+ [RC_DSM_MAC_CFG] = 32,
+ [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30,
+ [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30,
+ [RC_DSM_TAXI_CAL_CFG] = 6,
+ [RC_DSM_PREEMPT_CFG] = 32,
+ [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30,
+ [RC_HSCH_PORT_MODE] = 35,
+ [RC_QFWD_SWITCH_PORT_MODE] = 35,
+ [RC_QSYS_PAUSE_CFG] = 35,
+ [RC_QSYS_ATOP] = 35,
+ [RC_QSYS_FWD_PRESSURE] = 35,
+ [RC_QSYS_CAL_AUTO] = 4,
+ [RC_REW_OWN_UPSID] = 1,
+ [RC_REW_RTAG_ETAG_CTRL] = 35,
+};
+
+const unsigned int lan969x_reggrp_addr[GA_LAST] = {
+ [GA_ANA_AC_RAM_CTRL] = 202000,
+ [GA_ANA_AC_PS_COMMON] = 202880,
+ [GA_ANA_AC_MIRROR_PROBE] = 203232,
+ [GA_ANA_AC_SRC] = 201728,
+ [GA_ANA_AC_PGID] = 131072,
+ [GA_ANA_AC_PS_STICKY] = 202020,
+ [GA_ANA_AC_PS_STICKY_MASK] = 203328,
+ [GA_ANA_AC_TSN_SF] = 202028,
+ [GA_ANA_AC_TSN_SF_CFG] = 148480,
+ [GA_ANA_AC_TSN_SF_STATUS] = 147936,
+ [GA_ANA_AC_SG_ACCESS] = 202032,
+ [GA_ANA_AC_SG_CONFIG] = 202752,
+ [GA_ANA_AC_SG_STATUS] = 147952,
+ [GA_ANA_AC_SG_STATUS_STICKY] = 202044,
+ [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048,
+ [GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800,
+ [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068,
+ [GA_ANA_AC_STAT_CNT_CFG_ACL] = 201216,
+ [GA_ANA_ACL_COMMON] = 8192,
+ [GA_ANA_ACL_KEY_SEL] = 9204,
+ [GA_ANA_ACL_CNT_B] = 4096,
+ [GA_ANA_ACL_STICKY] = 10852,
+ [GA_ANA_AC_POL_POL_ALL_CFG] = 17504,
+ [GA_ANA_AC_POL_POL_PORT_CFG] = 0,
+ [GA_ANA_AC_POL_POL_PORT_CTRL] = 16384,
+ [GA_ANA_AC_POL_COMMON_BDLB] = 19464,
+ [GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472,
+ [GA_ANA_AC_SDLB_LBGRP_TBL] = 31788,
+ [GA_ANA_CL_PORT] = 65536,
+ [GA_ANA_CL_COMMON] = 87040,
+ [GA_ANA_L2_COMMON] = 561928,
+ [GA_ANA_L3_COMMON] = 370752,
+ [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580,
+ [GA_ASM_CFG] = 18304,
+ [GA_ASM_PFC_TIMER_CFG] = 15568,
+ [GA_ASM_LBK_WM_CFG] = 15596,
+ [GA_ASM_LBK_MISC_CFG] = 15608,
+ [GA_ASM_RAM_CTRL] = 15684,
+ [GA_DEV2G5_MM_CONFIG] = 224,
+ [GA_DEV2G5_MM_STATISTICS] = 232,
+ [GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864,
+ [GA_EACL_CNT_TBL] = 30720,
+ [GA_EACL_POL_CFG] = 38400,
+ [GA_EACL_ES2_STICKY] = 29072,
+ [GA_EACL_RAM_CTRL] = 29112,
+ [GA_GCB_GPIO] = 212,
+ [GA_GCB_SIO_CTRL] = 560,
+ [GA_HSCH_HSCH_L0_CFG] = 40960,
+ [GA_HSCH_HSCH_DWRR] = 36480,
+ [GA_HSCH_HSCH_MISC] = 36608,
+ [GA_HSCH_HSCH_LEAK_LISTS] = 37256,
+ [GA_HSCH_SYSTEM] = 37384,
+ [GA_HSCH_MMGT] = 36260,
+ [GA_HSCH_TAS_CONFIG] = 37696,
+ [GA_HSCH_TAS_PROFILE_CFG] = 37712,
+ [GA_HSCH_TAS_LIST_CFG] = 36288,
+ [GA_HSCH_TAS_GCL_CFG] = 36240,
+ [GA_HSCH_HSCH_TAS_STATE] = 36256,
+ [GA_PTP_PTP_CFG] = 512,
+ [GA_PTP_PTP_TOD_DOMAINS] = 528,
+ [GA_PTP_PHASE_DETECTOR_CTRL] = 628,
+ [GA_QSYS_CALCFG] = 2164,
+ [GA_QSYS_RAM_CTRL] = 2204,
+ [GA_REW_COMMON] = 98304,
+ [GA_REW_PORT] = 49152,
+ [GA_REW_VOE_PORT_LM_CNT] = 90112,
+ [GA_REW_RAM_CTRL] = 93992,
+ [GA_VOP_RAM_CTRL] = 16368,
+ [GA_XQS_SYSTEM] = 5744,
+ [GA_XQS_QLIMIT_SHR] = 6912,
+};
+
+const unsigned int lan969x_reggrp_cnt[GC_LAST] = {
+ [GC_ANA_AC_SRC] = 67,
+ [GC_ANA_AC_PGID] = 1054,
+ [GC_ANA_AC_TSN_SF_CFG] = 256,
+ [GC_ANA_AC_STAT_CNT_CFG_PORT] = 35,
+ [GC_ANA_AC_STAT_CNT_CFG_ACL] = 32,
+ [GC_ANA_ACL_KEY_SEL] = 99,
+ [GC_ANA_ACL_CNT_A] = 1024,
+ [GC_ANA_ACL_CNT_B] = 1024,
+ [GC_ANA_AC_POL_POL_PORT_CTRL] = 35,
+ [GC_ANA_AC_SDLB_LBGRP_TBL] = 5,
+ [GC_ANA_AC_SDLB_LBSET_TBL] = 496,
+ [GC_ANA_CL_PORT] = 35,
+ [GC_ANA_L2_ISDX_LIMIT] = 256,
+ [GC_ANA_L2_ISDX] = 1024,
+ [GC_ANA_L3_VLAN] = 4608,
+ [GC_ASM_DEV_STATISTICS] = 30,
+ [GC_EACL_ES2_KEY_SELECT_PROFILE] = 68,
+ [GC_EACL_CNT_TBL] = 512,
+ [GC_GCB_SIO_CTRL] = 1,
+ [GC_HSCH_HSCH_L0_CFG] = 1120,
+ [GC_HSCH_HSCH_CFG] = 1120,
+ [GC_HSCH_HSCH_DWRR] = 32,
+ [GC_HSCH_TAS_PROFILE_CFG] = 30,
+ [GC_PTP_PTP_PINS] = 8,
+ [GC_PTP_PHASE_DETECTOR_CTRL] = 8,
+ [GC_REW_PORT] = 35,
+ [GC_REW_VOE_PORT_LM_CNT] = 240,
+};
+
+const unsigned int lan969x_reggrp_sz[GW_LAST] = {
+ [GW_ANA_AC_SRC] = 4, [GW_ANA_L2_COMMON] = 712,
+ [GW_ASM_CFG] = 1092, [GW_CPU_CPU_REGS] = 180,
+ [GW_FDMA_FDMA] = 448, [GW_GCB_CHIP_REGS] = 180,
+ [GW_HSCH_TAS_CONFIG] = 16, [GW_HSCH_TAS_PROFILE_CFG] = 68,
+ [GW_HSCH_TAS_GCL_CFG] = 16, [GW_PTP_PHASE_DETECTOR_CTRL] = 12,
+ [GW_QSYS_PAUSE_CFG] = 988,
+ [GW_GCB_GPIO] = 212,
+};
diff --git a/drivers/net/mscc_eswitch/sparx5_reg_offset.h b/drivers/net/mscc_eswitch/sparx5_reg_offset.h
new file mode 100644
index 00000000000..519b06b813d
--- /dev/null
+++ b/drivers/net/mscc_eswitch/sparx5_reg_offset.h
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+enum sparx5_field {
+ FIELD_CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE,
+ FIELD_LAST,
+};
+
+enum sparx5_ra {
+ RA_CPU_RESET_PROT_STAT,
+ RA_CPU_PROC_CTRL,
+ RA_GCB_SOFT_RST,
+ RA_GCB_HW_SGPIO_TO_SD_MAP_CFG,
+ RA_GCB_GPIO_OUT_CLR,
+ RA_GCB_GPIO_OUT_CLR1,
+ RA_GCB_GPIO_OUT,
+ RA_GCB_GPIO_OUT1,
+ RA_GCB_GPIO_IN,
+ RA_GCB_GPIO_IN1,
+ RA_GCB_GPIO_OE,
+ RA_GCB_GPIO_OE1,
+ RA_GCB_GPIO_INTR,
+ RA_GCB_GPIO_INTR1,
+ RA_GCB_GPIO_INTR_ENA,
+ RA_GCB_GPIO_INTR_ENA1,
+ RA_GCB_GPIO_INTR_IDENT,
+ RA_GCB_GPIO_INTR_IDENT1,
+ RA_GCB_GPIO_ALT,
+ RA_GCB_GPIO_ALT1,
+ RA_LAST,
+};
+
+enum sparx5_rc {
+ RC_ANA_AC_OWN_UPSID,
+ RC_ANA_ACL_VCAP_S2_CFG,
+ RC_ANA_ACL_OWN_UPSID,
+ RC_ANA_AC_POL_POL_ACL_RATE_CFG,
+ RC_ANA_AC_POL_POL_ACL_THRES_CFG,
+ RC_ANA_AC_POL_POL_ACL_CTRL,
+ RC_ANA_AC_POL_POL_PORT_THRES_CFG_0,
+ RC_ANA_AC_POL_POL_PORT_THRES_CFG_1,
+ RC_ANA_AC_POL_POL_PORT_RATE_CFG,
+ RC_ANA_CL_OWN_UPSID,
+ RC_ANA_L2_OWN_UPSID,
+ RC_ASM_PORT_CFG,
+ RC_DSM_BUF_CFG,
+ RC_DSM_IPG_SHRINK_CFG,
+ RC_DSM_DEV_TX_STOP_WM_CFG,
+ RC_DSM_RX_PAUSE_CFG,
+ RC_DSM_MAC_CFG,
+ RC_DSM_MAC_ADDR_BASE_HIGH_CFG,
+ RC_DSM_MAC_ADDR_BASE_LOW_CFG,
+ RC_DSM_TAXI_CAL_CFG,
+ RC_DSM_PREEMPT_CFG,
+ RC_GCB_HW_SGPIO_TO_SD_MAP_CFG,
+ RC_HSCH_PORT_MODE,
+ RC_QFWD_SWITCH_PORT_MODE,
+ RC_QSYS_PAUSE_CFG,
+ RC_QSYS_ATOP,
+ RC_QSYS_FWD_PRESSURE,
+ RC_QSYS_CAL_AUTO,
+ RC_REW_OWN_UPSID,
+ RC_REW_RTAG_ETAG_CTRL,
+ RC_LAST,
+};
+
+enum sparx5_ga {
+ GA_ANA_AC_RAM_CTRL,
+ GA_ANA_AC_PS_COMMON,
+ GA_ANA_AC_MIRROR_PROBE,
+ GA_ANA_AC_SRC,
+ GA_ANA_AC_PGID,
+ GA_ANA_AC_PS_STICKY,
+ GA_ANA_AC_PS_STICKY_MASK,
+ GA_ANA_AC_TSN_SF,
+ GA_ANA_AC_TSN_SF_CFG,
+ GA_ANA_AC_TSN_SF_STATUS,
+ GA_ANA_AC_SG_ACCESS,
+ GA_ANA_AC_SG_CONFIG,
+ GA_ANA_AC_SG_STATUS,
+ GA_ANA_AC_SG_STATUS_STICKY,
+ GA_ANA_AC_STAT_GLOBAL_CFG_PORT,
+ GA_ANA_AC_STAT_CNT_CFG_PORT,
+ GA_ANA_AC_STAT_GLOBAL_CFG_ACL,
+ GA_ANA_AC_STAT_CNT_CFG_ACL,
+ GA_ANA_ACL_COMMON,
+ GA_ANA_ACL_KEY_SEL,
+ GA_ANA_ACL_CNT_B,
+ GA_ANA_ACL_STICKY,
+ GA_ANA_AC_POL_POL_ALL_CFG,
+ GA_ANA_AC_POL_POL_PORT_CFG,
+ GA_ANA_AC_POL_POL_PORT_CTRL,
+ GA_ANA_AC_POL_COMMON_BDLB,
+ GA_ANA_AC_POL_COMMON_BUM_SLB,
+ GA_ANA_AC_SDLB_LBGRP_TBL,
+ GA_ANA_CL_PORT,
+ GA_ANA_CL_COMMON,
+ GA_ANA_L2_COMMON,
+ GA_ANA_L3_COMMON,
+ GA_ANA_L3_VLAN_ARP_L3MC_STICKY,
+ GA_ASM_CFG,
+ GA_ASM_PFC_TIMER_CFG,
+ GA_ASM_LBK_WM_CFG,
+ GA_ASM_LBK_MISC_CFG,
+ GA_ASM_RAM_CTRL,
+ GA_DEV2G5_MM_CONFIG,
+ GA_DEV2G5_MM_STATISTICS,
+ GA_EACL_ES2_KEY_SELECT_PROFILE,
+ GA_EACL_CNT_TBL,
+ GA_EACL_POL_CFG,
+ GA_EACL_ES2_STICKY,
+ GA_EACL_RAM_CTRL,
+ GA_GCB_GPIO,
+ GA_GCB_SIO_CTRL,
+ GA_HSCH_HSCH_L0_CFG,
+ GA_HSCH_HSCH_DWRR,
+ GA_HSCH_HSCH_MISC,
+ GA_HSCH_HSCH_LEAK_LISTS,
+ GA_HSCH_SYSTEM,
+ GA_HSCH_MMGT,
+ GA_HSCH_TAS_CONFIG,
+ GA_HSCH_TAS_PROFILE_CFG,
+ GA_HSCH_TAS_LIST_CFG,
+ GA_HSCH_TAS_GCL_CFG,
+ GA_HSCH_HSCH_TAS_STATE,
+ GA_PTP_PTP_CFG,
+ GA_PTP_PTP_TOD_DOMAINS,
+ GA_PTP_PHASE_DETECTOR_CTRL,
+ GA_QSYS_CALCFG,
+ GA_QSYS_RAM_CTRL,
+ GA_REW_COMMON,
+ GA_REW_PORT,
+ GA_REW_VOE_PORT_LM_CNT,
+ GA_REW_RAM_CTRL,
+ GA_VOP_RAM_CTRL,
+ GA_XQS_SYSTEM,
+ GA_XQS_QLIMIT_SHR,
+ GA_LAST,
+};
+
+enum sparx5_gc {
+ GC_ANA_AC_SRC,
+ GC_ANA_AC_PGID,
+ GC_ANA_AC_TSN_SF_CFG,
+ GC_ANA_AC_STAT_CNT_CFG_PORT,
+ GC_ANA_AC_STAT_CNT_CFG_ACL,
+ GC_ANA_ACL_KEY_SEL,
+ GC_ANA_ACL_CNT_A,
+ GC_ANA_ACL_CNT_B,
+ GC_ANA_AC_POL_POL_PORT_CTRL,
+ GC_ANA_AC_SDLB_LBGRP_TBL,
+ GC_ANA_AC_SDLB_LBSET_TBL,
+ GC_ANA_CL_PORT,
+ GC_ANA_L2_ISDX_LIMIT,
+ GC_ANA_L2_ISDX,
+ GC_ANA_L3_VLAN,
+ GC_ASM_DEV_STATISTICS,
+ GC_EACL_ES2_KEY_SELECT_PROFILE,
+ GC_EACL_CNT_TBL,
+ GC_GCB_SIO_CTRL,
+ GC_HSCH_HSCH_L0_CFG,
+ GC_HSCH_HSCH_CFG,
+ GC_HSCH_HSCH_DWRR,
+ GC_HSCH_TAS_PROFILE_CFG,
+ GC_PTP_PTP_PINS,
+ GC_PTP_PHASE_DETECTOR_CTRL,
+ GC_REW_PORT,
+ GC_REW_VOE_PORT_LM_CNT,
+ GC_LAST,
+};
+
+enum sparx5_gw {
+ GW_ANA_AC_SRC,
+ GW_ANA_L2_COMMON,
+ GW_ASM_CFG,
+ GW_CPU_CPU_REGS,
+ GW_FDMA_FDMA,
+ GW_GCB_CHIP_REGS,
+ GW_HSCH_TAS_CONFIG,
+ GW_HSCH_TAS_PROFILE_CFG,
+ GW_HSCH_TAS_GCL_CFG,
+ GW_PTP_PHASE_DETECTOR_CTRL,
+ GW_QSYS_PAUSE_CFG,
+ GW_GCB_GPIO,
+ GW_LAST,
+};
+
+extern const unsigned int sparx5_reg_addr[RA_LAST];
+extern const unsigned int sparx5_reg_cnt[RC_LAST];
+extern const unsigned int sparx5_reggrp_addr[GA_LAST];
+extern const unsigned int sparx5_reggrp_cnt[GC_LAST];
+extern const unsigned int sparx5_reggrp_sz[GW_LAST];
+extern const unsigned int sparx5_regfield_addr[FIELD_LAST];
+extern const unsigned int lan969x_reg_addr[RA_LAST];
+extern const unsigned int lan969x_reg_cnt[RC_LAST];
+extern const unsigned int lan969x_reggrp_addr[GA_LAST];
+extern const unsigned int lan969x_reggrp_cnt[GC_LAST];
+extern const unsigned int lan969x_reggrp_sz[GW_LAST];
+extern const unsigned int lan969x_regfield_addr[FIELD_LAST];
diff --git a/drivers/net/mscc_eswitch/sparx5_regs.h b/drivers/net/mscc_eswitch/sparx5_regs.h
new file mode 100644
index 00000000000..df6ea270e39
--- /dev/null
+++ b/drivers/net/mscc_eswitch/sparx5_regs.h
@@ -0,0 +1,701 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <linux/bitfield.h>
+
+#define GRP_ADDR(o) priv->data->regs.reggrp_addr[o]
+#define GRP_CNT(o) priv->data->regs.reggrp_cnt[o]
+#define GRP_SIZE(o) priv->data->regs.reggrp_size[o]
+#define REG_ADDR(o) priv->data->regs.reg_addr[o]
+#define REG_CNT(o) priv->data->regs.reg_cnt[o]
+#define FIELD_ADDR(o) priv->data->regs.regfield_addr[o]
+
+#define __REG(...) __VA_ARGS__
+
+/* RAM init regs */
+#define ANA_AC_RAM_INIT \
+ __REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_RAM_CTRL), 0, 1, 4, 0, \
+ 0, 1, 4)
+#define QSYS_RAM_INIT \
+ __REG(TARGET_QSYS, 0, 1, GRP_ADDR(GA_QSYS_RAM_CTRL), 0, 1, 4, 0, 0, 1, \
+ 4)
+#define ASM_RAM_INIT \
+ __REG(TARGET_ASM, 0, 1, GRP_ADDR(GA_ASM_RAM_CTRL), 0, 1, 4, 0, 0, 1, 4)
+#define REW_RAM_INIT \
+ __REG(TARGET_REW, 0, 1, GRP_ADDR(GA_REW_RAM_CTRL), 0, 1, 4, 0, 0, 1, 4)
+#define DSM_RAM_INIT __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
+#define EACL_RAM_INIT \
+ __REG(TARGET_EACL, 0, 1, GRP_ADDR(GA_EACL_RAM_CTRL), 0, 1, 4, 0, 0, 1, \
+ 4)
+#define VCAP_SUPER_RAM_INIT \
+ __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4)
+#define VOP_RAM_INIT \
+ __REG(TARGET_VOP, 0, 1, GRP_ADDR(GA_VOP_RAM_CTRL), 0, 1, 4, 0, 0, 1, 4)
+
+/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */
+#define ANA_AC_STAT_RESET \
+ __REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_STAT_GLOBAL_CFG_PORT), \
+ 0, 1, 20, 16, 0, 1, 4)
+
+/* ASM:CFG:STAT_CFG */
+#define ASM_STAT_CFG \
+ __REG(TARGET_ASM, 0, 1, GRP_ADDR(GA_ASM_CFG), 0, 1, \
+ GRP_SIZE(GW_ASM_CFG), 0, 0, 1, 4)
+
+/* QSYS:CALCFG:CAL_AUTO */
+#define QSYS_CAL_AUTO(r) \
+ __REG(TARGET_QSYS, 0, 1, GRP_ADDR(GA_QSYS_CALCFG), 0, 1, 40, 0, r, \
+ REG_CNT(RC_QSYS_CAL_AUTO), 4)
+
+/* QSYS:CALCFG:CAL_CTRL */
+#define QSYS_CAL_CTRL \
+ __REG(TARGET_QSYS, 0, 1, GRP_ADDR(GA_QSYS_CALCFG), 0, 1, 40, 36, 0, 1, \
+ 4)
+
+#define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11)
+#define QSYS_CAL_CTRL_CAL_MODE_SET(x) FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x)
+#define QSYS_CAL_CTRL_CAL_MODE_GET(x) FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x)
+
+/* PORT_CONF:HW_CFG:DEV5G_MODES */
+#define PORT_CONF_DEV5G_MODES \
+ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4)
+
+#define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12)
+#define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x) \
+ FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
+#define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x) \
+ FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
+
+/* PORT_CONF:HW_CFG:DEV10G_MODES */
+#define PORT_CONF_DEV10G_MODES \
+ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4)
+
+/* SPARX5 ONLY */
+/* PORT_CONF:HW_CFG:DEV25G_MODES */
+#define PORT_CONF_DEV25G_MODES \
+ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4)
+
+/* DSM:CFG:DEV_TX_STOP_WM_CFG */
+#define DSM_DEV_TX_STOP_WM_CFG(r) \
+ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, \
+ REG_CNT(RC_DSM_DEV_TX_STOP_WM_CFG), 4)
+
+#define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8)
+#define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x) \
+ FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
+#define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x) \
+ FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
+
+/* PORT_CONF:HW_CFG:QSGMII_ENA */
+#define PORT_CONF_QSGMII_ENA \
+ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4)
+
+/* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */
+#define PORT_CONF_USGMII_CFG(g) \
+ __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4)
+
+/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */
+#define DEV2G5_DEV_RST_CTRL(t) \
+ __REG(TARGET_DEV2G5, t, 65, 0, 0, 1, 36, 0, 0, 1, 4)
+
+#define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
+#define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x) \
+ FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
+#define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x) \
+ FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
+
+#define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST BIT(17)
+#define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x) \
+ FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
+#define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x) \
+ FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
+
+#define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST BIT(16)
+#define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x) \
+ FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
+#define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x) \
+ FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
+
+#define DEV2G5_DEV_RST_CTRL_PCS_TX_RST BIT(12)
+#define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x) \
+ FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
+#define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x) \
+ FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
+
+/* ANA_AC:PGID:PGID_CFG */
+#define ANA_AC_PGID_CFG(g) \
+ __REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_PGID), g, \
+ GRP_CNT(GC_ANA_AC_PGID), 16, 0, 0, 1, 4)
+
+/* SPARX5 ONLY */
+/* ANA_AC:PGID:PGID_CFG1 */
+#define ANA_AC_PGID_CFG1(g) \
+ __REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_PGID), g, \
+ GRP_CNT(GC_ANA_AC_PGID), 16, 4, 0, 1, 4)
+
+/* SPARX5 ONLY */
+/* ANA_AC:PGID:PGID_CFG2 */
+#define ANA_AC_PGID_CFG2(g) \
+ __REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_PGID), g, \
+ GRP_CNT(GC_ANA_AC_PGID), 16, 8, 0, 1, 4)
+
+/* ANA_AC:SRC:SRC_CFG */
+#define ANA_AC_SRC_CFG(g) \
+ __REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_SRC), g, \
+ GRP_CNT(GC_ANA_AC_SRC), GRP_SIZE(GW_ANA_AC_SRC), 0, 0, 1, 4)
+
+/* SPARX5 ONLY */
+/* ANA_AC:SRC:SRC_CFG1 */
+#define ANA_AC_SRC_CFG1(g) \
+ __REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_SRC), g, \
+ GRP_CNT(GC_ANA_AC_SRC), GRP_SIZE(GW_ANA_AC_SRC), 4, 0, 1, 4)
+
+/* SPARX5 ONLY */
+/* ANA_AC:SRC:SRC_CFG2 */
+#define ANA_AC_SRC_CFG2(g) \
+ __REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_SRC), g, \
+ GRP_CNT(GC_ANA_AC_SRC), GRP_SIZE(GW_ANA_AC_SRC), 8, 0, 1, 4)
+
+/* XQS:SYSTEM:STAT_CFG */
+#define XQS_STAT_CFG \
+ __REG(TARGET_XQS, 0, 1, GRP_ADDR(GA_XQS_SYSTEM), 0, 1, 872, 860, 0, 1, \
+ 4)
+
+/* ANA_CL:PORT:VLAN_CTRL */
+#define ANA_CL_VLAN_CTRL(g) \
+ __REG(TARGET_ANA_CL, 0, 1, GRP_ADDR(GA_ANA_CL_PORT), g, \
+ GRP_CNT(GC_ANA_CL_PORT), 512, 32, 0, 1, 4)
+
+#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA BIT(19)
+#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x) \
+ FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
+#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x) \
+ FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
+
+#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17)
+#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x) \
+ FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
+#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x) \
+ FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
+
+#define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0)
+#define ANA_CL_VLAN_CTRL_PORT_VID_SET(x) \
+ FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)
+#define ANA_CL_VLAN_CTRL_PORT_VID_GET(x) FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)
+
+/* ANA_L3:VLAN:VLAN_CFG */
+#define ANA_L3_VLAN_CFG(g) \
+ __REG(TARGET_ANA_L3, 0, 1, 0, g, GRP_CNT(GC_ANA_L3_VLAN), 64, 8, 0, 1, \
+ 4)
+
+#define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8)
+#define ANA_L3_VLAN_CFG_VLAN_FID_SET(x) FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x)
+#define ANA_L3_VLAN_CFG_VLAN_FID_GET(x) FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x)
+
+#define ANA_L3_VLAN_CFG_VLAN_LRN_DIS BIT(3)
+#define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x) \
+ FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
+#define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x) \
+ FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
+
+/* ANA_L3:COMMON:VLAN_CTRL */
+#define ANA_L3_VLAN_CTRL \
+ __REG(TARGET_ANA_L3, 0, 1, GRP_ADDR(GA_ANA_L3_COMMON), 0, 1, 184, 4, \
+ 0, 1, 4)
+
+#define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0)
+#define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x) \
+ FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
+#define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x) FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
+
+/* HSCH:MMGT:RESET_CFG */
+#define HSCH_RESET_CFG \
+ __REG(TARGET_HSCH, 0, 1, GRP_ADDR(GA_HSCH_MMGT), 0, 1, 16, 8, 0, 1, 4)
+
+#define HSCH_RESET_CFG_CORE_ENA BIT(0)
+#define HSCH_RESET_CFG_CORE_ENA_SET(x) FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x)
+#define HSCH_RESET_CFG_CORE_ENA_GET(x) FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x)
+
+/* ASM:CFG:PORT_CFG */
+#define ASM_PORT_CFG(r) \
+ __REG(TARGET_ASM, 0, 1, GRP_ADDR(GA_ASM_CFG), 0, 1, \
+ GRP_SIZE(GW_ASM_CFG), 540, r, REG_CNT(RC_ASM_PORT_CFG), 4)
+
+#define ASM_PORT_CFG_NO_PREAMBLE_ENA BIT(9)
+#define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x) \
+ FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
+#define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x) \
+ FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
+
+#define ASM_PORT_CFG_PAD_ENA BIT(6)
+#define ASM_PORT_CFG_PAD_ENA_SET(x) FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x)
+#define ASM_PORT_CFG_PAD_ENA_GET(x) FIELD_GET(ASM_PORT_CFG_PAD_ENA, x)
+
+#define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2)
+#define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x) \
+ FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
+#define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x) \
+ FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
+
+/* DEVCPU_QS:INJ:INJ_GRP_CFG */
+#define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
+
+#define QS_INJ_GRP_CFG_MODE GENMASK(3, 2)
+#define QS_INJ_GRP_CFG_MODE_SET(x) FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
+#define QS_INJ_GRP_CFG_MODE_GET(x) FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
+
+#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
+#define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x) FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
+#define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x) FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
+
+/* DEVCPU_QS:XTR:XTR_GRP_CFG */
+#define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
+
+#define QS_XTR_GRP_CFG_MODE GENMASK(3, 2)
+#define QS_XTR_GRP_CFG_MODE_SET(x) FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
+#define QS_XTR_GRP_CFG_MODE_GET(x) FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
+
+#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
+#define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x) \
+ FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
+#define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x) \
+ FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
+
+#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
+#define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x) FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
+#define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x) FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
+
+/* QFWD:SYSTEM:SWITCH_PORT_MODE */
+#define QFWD_SWITCH_PORT_MODE(r) \
+ __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \
+ REG_CNT(RC_QFWD_SWITCH_PORT_MODE), 4)
+
+#define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19)
+#define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x) \
+ FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
+#define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x) \
+ FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
+
+/* ANA_CL:PORT:FILTER_CTRL */
+#define ANA_CL_FILTER_CTRL(g) \
+ __REG(TARGET_ANA_CL, 0, 1, GRP_ADDR(GA_ANA_CL_PORT), g, \
+ GRP_CNT(GC_ANA_CL_PORT), 512, 4, 0, 1, 4)
+
+#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA BIT(0)
+#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x) \
+ FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
+#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x) \
+ FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
+
+/* ANA_L2:COMMON:FWD_CFG */
+#define ANA_L2_FWD_CFG \
+ __REG(TARGET_ANA_L2, 0, 1, GRP_ADDR(GA_ANA_L2_COMMON), 0, 1, \
+ GRP_SIZE(GW_ANA_L2_COMMON), 0, 0, 1, 4)
+
+#define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6)
+#define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x) \
+ FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)
+#define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x) \
+ FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)
+
+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */
+#define DEV2G5_PCS1G_CFG(t) \
+ __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 0, 0, 1, 4)
+
+#define DEV2G5_PCS1G_CFG_PCS_ENA BIT(0)
+#define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x) FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x)
+#define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x) FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x)
+
+/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */
+#define DEV2G5_MAC_ENA_CFG(t) \
+ __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 0, 0, 1, 4)
+
+#define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4)
+#define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x) \
+ FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
+#define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x) FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
+
+#define DEV2G5_MAC_ENA_CFG_TX_ENA BIT(0)
+#define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x) \
+ FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
+#define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x) FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
+
+/*DEV1G:USXGMII_ANEG_CFG_STATUS:USXGMII_PCS_SD_CFG */
+#define DEV2G5_USXGMII_PCS_SD_CFG(t) \
+ __REG(TARGET_DEV2G5, t, 65, 36, 0, 1, 16, 8, 0, 1, 4)
+
+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */
+#define DEV2G5_PCS1G_MODE_CFG(t) \
+ __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 4, 0, 1, 4)
+
+#define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
+#define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x) \
+ FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
+#define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x) \
+ FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
+
+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */
+#define DEV2G5_PCS1G_ANEG_CFG(t) \
+ __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 12, 0, 1, 4)
+
+#define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16)
+#define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x) \
+ FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
+#define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x) \
+ FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
+
+#define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
+#define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x) \
+ FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
+#define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x) \
+ FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
+
+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x) \
+ FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x) \
+ FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
+
+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA BIT(0)
+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x) \
+ FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x) \
+ FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
+
+/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */
+#define DEV2G5_MAC_IFG_CFG(t) \
+ __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 24, 0, 1, 4)
+
+#define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
+#define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x) \
+ FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
+#define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x) \
+ FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
+
+#define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)
+#define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x) \
+ FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
+#define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x) FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
+
+#define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)
+#define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x) \
+ FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
+#define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x) \
+ FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
+
+#define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)
+#define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x) \
+ FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
+#define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x) \
+ FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
+
+/* LRN:COMMON:COMMON_ACCESS_CTRL */
+#define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
+
+#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1)
+#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x) \
+ FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
+#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x) \
+ FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
+
+#define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0)
+#define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x) \
+ FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
+#define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x) \
+ FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
+
+/* LRN:COMMON:MAC_ACCESS_CFG_0 */
+#define LRN_MAC_ACCESS_CFG_0 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)
+
+/* LRN:COMMON:MAC_ACCESS_CFG_1 */
+#define LRN_MAC_ACCESS_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)
+
+/* LRN:COMMON:MAC_ACCESS_CFG_2 */
+#define LRN_MAC_ACCESS_CFG_2 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4)
+
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU GENMASK(26, 24)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x) \
+ FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x) \
+ FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
+
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY BIT(23)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x) \
+ FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x) \
+ FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
+
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED BIT(16)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x) \
+ FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x) \
+ FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
+
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD BIT(15)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x) \
+ FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x) \
+ FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
+
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x) \
+ FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x) \
+ FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
+
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR GENMASK(11, 0)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x) \
+ FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x) \
+ FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
+
+#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0)
+#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x) \
+ FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
+#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x) \
+ FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
+
+/* LRN:COMMON:SCAN_NEXT_CFG */
+#define LRN_SCAN_NEXT_CFG __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4)
+
+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10)
+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x) \
+ FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x) \
+ FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
+
+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7)
+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x) \
+ FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x) \
+ FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
+
+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */
+#define DEV2G5_PCS1G_LINK_STATUS(t) \
+ __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 40, 0, 1, 4)
+
+#define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
+#define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x) \
+ FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
+#define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x) \
+ FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
+
+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */
+#define DEV2G5_PCS1G_ANEG_STATUS(t) \
+ __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 32, 0, 1, 4)
+
+#define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
+#define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x) \
+ FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
+#define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x) \
+ FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
+
+/* CPU:CPU_REGS:RESET_PROT_STAT */
+#define CPU_RESET_PROT_STAT __REG(TARGET_CPU, 0, 1, 0, 0, 1, 204, \
+ REG_ADDR(RA_CPU_RESET_PROT_STAT), 0, 1, 4)
+
+#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE FIELD_ADDR(FIELD_CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE)
+#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_SET(x)\
+ FIELD_PREP(CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE, x)
+#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_GET(x)\
+ FIELD_GET(CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE, x)
+
+/* DEVCPU_GCB:CHIP_REGS:SOFT_RST */
+#define GCB_SOFT_RST __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, \
+ REG_ADDR(RA_GCB_SOFT_RST), 0, 1, 4)
+
+#define GCB_SOFT_RST_SOFT_CHIP_RST BIT(0)
+#define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\
+ FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x)
+#define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\
+ FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x)
+
+/* HSIOWRAP:XMII_CFG: */
+#define HSIO_WRAP_XMII_CFG(g) __REG(TARGET_HSIO, 0, 1, 116, g, 2, 20, 0, 0, 1, 4)
+
+#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG GENMASK(2, 1)
+#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(x)\
+ FIELD_PREP(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x)
+#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_GET(x)\
+ FIELD_GET(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x)
+
+/* HSIOWRAP:XMII_CFG: */
+#define HSIO_WRAP_RGMII_CFG(g) __REG(TARGET_HSIO, 0, 1, 116, g, 2, 20, 4, 0, 1, 4)
+
+#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2)
+#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(x)\
+ FIELD_PREP(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x)
+#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_GET(x)\
+ FIELD_GET(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x)
+
+/* HSIOWRAP:XMII_CFG: */
+#define HSIO_WRAP_DLL_CFG(g, r) __REG(TARGET_HSIO, 0, 1, 116, g, 2, 20, 12, r, 2, 4)
+
+#define HSIO_WRAP_DLL_CFG_DLL_ENA BIT(19)
+#define HSIO_WRAP_DLL_CFG_DLL_ENA_SET(x)\
+ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_ENA, x)
+#define HSIO_WRAP_DLL_CFG_DLL_ENA_GET(x)\
+ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_ENA, x)
+
+#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA BIT(18)
+#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(x)\
+ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x)
+#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_GET(x)\
+ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x)
+
+#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL GENMASK(17, 15)
+#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(x)\
+ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x)
+#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_GET(x)\
+ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x)
+
+#define HSIO_WRAP_DLL_CFG_DLL_RST BIT(0)
+#define HSIO_WRAP_DLL_CFG_DLL_RST_SET(x)\
+ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_RST, x)
+#define HSIO_WRAP_DLL_CFG_DLL_RST_GET(x)\
+ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_RST, x)
+
+/* DEV1G:DEV_CFG_STATUS: */
+#define DEVRGMII_DEV_RST_CTRL(t) __REG(TARGET_DEV2G5, t, 2, 0, 0, 1, 36, 0, 0, 1, 4)
+
+#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
+#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(x)\
+ FIELD_PREP(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x)
+#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_GET(x)\
+ FIELD_GET(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x)
+
+/* DEV1G:MAC_CFG_STATUS: */
+#define DEVRGMII_MAC_IFG_CFG(t) __REG(TARGET_DEV2G5, t, 2, 36, 0, 1, 36, 24, 0, 1, 4)
+
+#define DEVRGMII_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)
+#define DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(x)\
+ FIELD_PREP(DEVRGMII_MAC_IFG_CFG_TX_IFG, x)
+#define DEVRGMII_MAC_IFG_CFG_TX_IFG_GET(x)\
+ FIELD_GET(DEVRGMII_MAC_IFG_CFG_TX_IFG, x)
+
+#define DEVRGMII_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)
+#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(x)\
+ FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x)
+#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_GET(x)\
+ FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x)
+
+#define DEVRGMII_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)
+#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(x)\
+ FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x)
+#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_GET(x)\
+ FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x)
+
+/* DEV1G:MAC_CFG_STATUS: */
+#define DEVRGMII_MAC_ENA_CFG(t) __REG(TARGET_DEV2G5, t, 2, 36, 0, 1, 36, 0, 0, 1, 4)
+
+#define DEVRGMII_MAC_ENA_CFG_RX_ENA BIT(4)
+#define DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(x)\
+ FIELD_PREP(DEVRGMII_MAC_ENA_CFG_RX_ENA, x)
+#define DEVRGMII_MAC_ENA_CFG_RX_ENA_GET(x)\
+ FIELD_GET(DEVRGMII_MAC_ENA_CFG_RX_ENA, x)
+
+#define DEVRGMII_MAC_ENA_CFG_TX_ENA BIT(0)
+#define DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(x)\
+ FIELD_PREP(DEVRGMII_MAC_ENA_CFG_TX_ENA, x)
+#define DEVRGMII_MAC_ENA_CFG_TX_ENA_GET(x)\
+ FIELD_GET(DEVRGMII_MAC_ENA_CFG_TX_ENA, x)
+
+/* DEVCPU_GCB:SIO_CTRL:SIO_CFG */
+#define GCB_SIO_CFG(g) \
+ __REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_SIO_CTRL), g, GRP_CNT(GC_GCB_SIO_CTRL), 280, 16, 0, 1, 4)
+
+/* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */
+#define GCB_SIO_CLOCK(g) \
+ __REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_SIO_CTRL), g, GRP_CNT(GC_GCB_SIO_CTRL), 280, 20, 0, 1, 4)
+
+/* DEVCPU_GCB:SIO_CTRL:SIO_PORT_ENA */
+#define GCB_SIO_PORT_ENA(g) \
+ __REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_SIO_CTRL), g, GRP_CNT(GC_GCB_SIO_CTRL), 280, 152, 0, 1, 4)
+
+/* DEVCPU_GCB:SIO_CTRL:SIO_INTR_POL */
+#define GCB_SIO_INTR_POL(g, r) \
+ __REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_SIO_CTRL), g, GRP_CNT(GC_GCB_SIO_CTRL), 280, 168, r, 4, 4)
+
+/* DEVCPU_GCB:SIO_CTRL:SIO_PORT_CFG */
+#define GCB_SIO_PORT_CFG(g, r) \
+ __REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_SIO_CTRL), g, GRP_CNT(GC_GCB_SIO_CTRL), 280, 24, r, 32, 4)
+
+/* DEVCPU_GCB:GPIO:GPIO_OE */
+#define GCB_GPIO_OE \
+ __REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_GPIO), 0, 1, GRP_SIZE(GW_GCB_GPIO), REG_ADDR(RA_GCB_GPIO_OE), 0, 1, 4)
+
+/* DEVCPU_GCB:GPIO:GPIO_OUT_CLR */
+#define GCB_GPIO_OUT_CLR \
+ __REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_GPIO), 0, 1, GRP_SIZE(GW_GCB_GPIO), REG_ADDR(RA_GCB_GPIO_OUT_CLR), 0, 1, 4)
+
+/* DEVCPU_GCB:GPIO:GPIO_OUT_SET */
+#define GCB_GPIO_OUT_SET \
+ __REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_GPIO), 0, 1, GRP_SIZE(GW_GCB_GPIO), 0, 0, 1, 4)
+
+/* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */
+#define PTP_PTP_DOM_CFG \
+ __REG(TARGET_PTP, 0, 1, GRP_ADDR(GA_PTP_PTP_CFG), 0, 1, 16, 12, 0, 1, 4)
+
+#define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9)
+#define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\
+ FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x)
+#define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\
+ FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x)
+
+/* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */
+#define PTP_CLK_PER_CFG(g, r) \
+ __REG(TARGET_PTP, 0, 1, GRP_ADDR(GA_PTP_PTP_TOD_DOMAINS), g, 3, 28, 0, r, 2, 4)
+
+/* DSM:CFG:TAXI_CAL_CFG */
+#define DSM_TAXI_CAL_CFG(r) \
+ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4)
+
+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT BIT(23)
+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)
+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)
+
+#define DSM_TAXI_CAL_CFG_CAL_SWITCH BIT(22)
+#define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)
+#define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)
+
+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL BIT(21)
+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)
+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)
+
+#define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15)
+#define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x)
+#define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x)
+
+#define DSM_TAXI_CAL_CFG_CAL_CUR_LEN GENMASK(14, 9)
+#define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
+#define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
+
+#define DSM_TAXI_CAL_CFG_CAL_CUR_VAL GENMASK(8, 5)
+#define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
+#define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
+
+#define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1)
+#define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
+#define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
+
+#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA BIT(0)
+#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
+#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
diff --git a/drivers/net/mscc_eswitch/sparx5_serdes.c b/drivers/net/mscc_eswitch/sparx5_serdes.c
new file mode 100644
index 00000000000..9ea959fde8c
--- /dev/null
+++ b/drivers/net/mscc_eswitch/sparx5_serdes.c
@@ -0,0 +1,2703 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* Microchip Sparx5 Switch SerDes driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ * and the datasheet is available here:
+ * https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_00003822B.pdf
+ */
+
+#include <clk.h>
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#include <linux/io.h>
+#include <linux/netdevice.h>
+#include <linux/printk.h>
+#include <dm/devres.h>
+#include <dm/device_compat.h>
+#include <dm/device.h>
+#include <dm/read.h>
+
+#include <dt-bindings/mscc/sparx5_data.h>
+
+#include "sparx5_switch.h"
+#include "sparx5_serdes.h"
+#include "sparx5_serdes_priv.h"
+
+/**
+ * phy_modes - map phy_interface_t enum to device tree binding of phy-mode
+ * @interface: enum phy_interface_t value
+ *
+ * Description: maps enum &phy_interface_t defined in this file
+ * into the device tree binding of 'phy-mode', so that Ethernet
+ * device driver can get PHY interface from device tree.
+ */
+static inline const char *phy_modes(phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_NA:
+ return "";
+ case PHY_INTERFACE_MODE_INTERNAL:
+ return "internal";
+ case PHY_INTERFACE_MODE_MII:
+ return "mii";
+ case PHY_INTERFACE_MODE_GMII:
+ return "gmii";
+ case PHY_INTERFACE_MODE_SGMII:
+ return "sgmii";
+ case PHY_INTERFACE_MODE_TBI:
+ return "tbi";
+ case PHY_INTERFACE_MODE_REVMII:
+ return "rev-mii";
+ case PHY_INTERFACE_MODE_RMII:
+ return "rmii";
+ case PHY_INTERFACE_MODE_REVRMII:
+ return "rev-rmii";
+ case PHY_INTERFACE_MODE_RGMII:
+ return "rgmii";
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ return "rgmii-id";
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ return "rgmii-rxid";
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ return "rgmii-txid";
+ case PHY_INTERFACE_MODE_RTBI:
+ return "rtbi";
+ case PHY_INTERFACE_MODE_SMII:
+ return "smii";
+ case PHY_INTERFACE_MODE_XGMII:
+ return "xgmii";
+ case PHY_INTERFACE_MODE_XLGMII:
+ return "xlgmii";
+ case PHY_INTERFACE_MODE_MOCA:
+ return "moca";
+ case PHY_INTERFACE_MODE_QSGMII:
+ return "qsgmii";
+ case PHY_INTERFACE_MODE_TRGMII:
+ return "trgmii";
+ case PHY_INTERFACE_MODE_1000BASEX:
+ return "1000base-x";
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return "2500base-x";
+ case PHY_INTERFACE_MODE_5GBASER:
+ return "5gbase-r";
+ case PHY_INTERFACE_MODE_RXAUI:
+ return "rxaui";
+ case PHY_INTERFACE_MODE_XAUI:
+ return "xaui";
+ case PHY_INTERFACE_MODE_10GBASER:
+ return "10gbase-r";
+ case PHY_INTERFACE_MODE_25GBASER:
+ return "25gbase-r";
+ case PHY_INTERFACE_MODE_USXGMII:
+ return "usxgmii";
+ case PHY_INTERFACE_MODE_10GKR:
+ return "10gbase-kr";
+ case PHY_INTERFACE_MODE_100BASEX:
+ return "100base-x";
+ case PHY_INTERFACE_MODE_QUSGMII:
+ return "qusgmii";
+ default:
+ return "unknown";
+ }
+}
+
+// It is not clear why the SPEED_5000 is not seen inside <linux/ethtool.h> but
+// all the other macros as seen
+#define SPEED_5000 5000
+
+#define SPX5_SERDES_10G_START 13
+#define SPX5_SERDES_25G_START 25
+#define SPX5_SERDES_25G_CNT 8
+
+/* Optimal power settings from GUC */
+#define SPX5_SERDES_QUIET_MODE_VAL 0x1EF4E0C
+
+const unsigned int sparx5_serdes_tsize[TSIZE_LAST] = {
+ [TC_SD10G_LANE] = 12,
+ [TC_SD_CMU] = 14,
+ [TC_SD_CMU_CFG] = 14,
+ [TC_SD_LANE] = 25,
+};
+
+const unsigned int lan969x_serdes_tsize[TSIZE_LAST] = {
+ [TC_SD10G_LANE] = 10,
+ [TC_SD_CMU] = 6,
+ [TC_SD_CMU_CFG] = 6,
+ [TC_SD_LANE] = 10,
+};
+
+enum sparx5_sd25g28_mode_preset_type {
+ SPX5_SD25G28_MODE_PRESET_25000,
+ SPX5_SD25G28_MODE_PRESET_10000,
+ SPX5_SD25G28_MODE_PRESET_5000,
+ SPX5_SD25G28_MODE_PRESET_SD_2G5,
+ SPX5_SD25G28_MODE_PRESET_1000BASEX,
+};
+
+enum sparx5_sd10g28_mode_preset_type {
+ SPX5_SD10G28_MODE_PRESET_10000,
+ SPX5_SD10G28_MODE_PRESET_SFI_5000_6G,
+ SPX5_SD10G28_MODE_PRESET_SFI_5000_10G,
+ SPX5_SD10G28_MODE_PRESET_QSGMII,
+ SPX5_SD10G28_MODE_PRESET_SD_2G5,
+ SPX5_SD10G28_MODE_PRESET_1000BASEX,
+};
+
+struct sparx5_sd25g28_mode_preset {
+ u8 bitwidth;
+ u8 tx_pre_div;
+ u8 fifo_ck_div;
+ u8 pre_divsel;
+ u8 vco_div_mode;
+ u8 sel_div;
+ u8 ck_bitwidth;
+ u8 subrate;
+ u8 com_txcal_en;
+ u8 com_tx_reserve_msb;
+ u8 com_tx_reserve_lsb;
+ u8 cfg_itx_ipcml_base;
+ u8 tx_reserve_lsb;
+ u8 tx_reserve_msb;
+ u8 bw;
+ u8 rxterm;
+ u8 dfe_tap;
+ u8 dfe_enable;
+ bool txmargin;
+ u8 cfg_ctle_rstn;
+ u8 r_dfe_rstn;
+ u8 cfg_pi_bw_3_0;
+ u8 tx_tap_dly;
+ u8 tx_tap_adv;
+};
+
+struct sparx5_sd25g28_media_preset {
+ u8 cfg_eq_c_force_3_0;
+ u8 cfg_vga_ctrl_byp_4_0;
+ u8 cfg_eq_r_force_3_0;
+ u8 cfg_en_adv;
+ u8 cfg_en_main;
+ u8 cfg_en_dly;
+ u8 cfg_tap_adv_3_0;
+ u8 cfg_tap_main;
+ u8 cfg_tap_dly_4_0;
+ u8 cfg_alos_thr_2_0;
+};
+
+struct sparx5_sd25g28_args {
+ u8 if_width; /* UDL if-width: 10/16/20/32/64 */
+ bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */
+ enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
+ bool no_pwrcycle:1; /* Omit initial power-cycle */
+ bool txinvert:1; /* Enable inversion of output data */
+ bool rxinvert:1; /* Enable inversion of input data */
+ u16 txswing; /* Set output level */
+ u8 rate; /* Rate of network interface */
+ u8 pi_bw_gen1;
+ u8 duty_cycle; /* Set output level to half/full */
+ bool mute:1; /* Mute Output Buffer */
+ bool reg_rst:1;
+ u8 com_pll_reserve;
+};
+
+struct sparx5_sd25g28_params {
+ u8 reg_rst;
+ u8 cfg_jc_byp;
+ u8 cfg_common_reserve_7_0;
+ u8 r_reg_manual;
+ u8 r_d_width_ctrl_from_hwt;
+ u8 r_d_width_ctrl_2_0;
+ u8 r_txfifo_ck_div_pmad_2_0;
+ u8 r_rxfifo_ck_div_pmad_2_0;
+ u8 cfg_pll_lol_set;
+ u8 cfg_vco_div_mode_1_0;
+ u8 cfg_pre_divsel_1_0;
+ u8 cfg_sel_div_3_0;
+ u8 cfg_vco_start_code_3_0;
+ u8 cfg_pma_tx_ck_bitwidth_2_0;
+ u8 cfg_tx_prediv_1_0;
+ u8 cfg_rxdiv_sel_2_0;
+ u8 cfg_tx_subrate_2_0;
+ u8 cfg_rx_subrate_2_0;
+ u8 r_multi_lane_mode;
+ u8 cfg_cdrck_en;
+ u8 cfg_dfeck_en;
+ u8 cfg_dfe_pd;
+ u8 cfg_dfedmx_pd;
+ u8 cfg_dfetap_en_5_1;
+ u8 cfg_dmux_pd;
+ u8 cfg_dmux_clk_pd;
+ u8 cfg_erramp_pd;
+ u8 cfg_pi_dfe_en;
+ u8 cfg_pi_en;
+ u8 cfg_pd_ctle;
+ u8 cfg_summer_en;
+ u8 cfg_pmad_ck_pd;
+ u8 cfg_pd_clk;
+ u8 cfg_pd_cml;
+ u8 cfg_pd_driver;
+ u8 cfg_rx_reg_pu;
+ u8 cfg_pd_rms_det;
+ u8 cfg_dcdr_pd;
+ u8 cfg_ecdr_pd;
+ u8 cfg_pd_sq;
+ u8 cfg_itx_ipdriver_base_2_0;
+ u8 cfg_tap_dly_4_0;
+ u8 cfg_tap_main;
+ u8 cfg_en_main;
+ u8 cfg_tap_adv_3_0;
+ u8 cfg_en_adv;
+ u8 cfg_en_dly;
+ u8 cfg_iscan_en;
+ u8 l1_pcs_en_fast_iscan;
+ u8 l0_cfg_bw_1_0;
+ u8 l0_cfg_txcal_en;
+ u8 cfg_en_dummy;
+ u8 cfg_pll_reserve_3_0;
+ u8 l0_cfg_tx_reserve_15_8;
+ u8 l0_cfg_tx_reserve_7_0;
+ u8 cfg_tx_reserve_15_8;
+ u8 cfg_tx_reserve_7_0;
+ u8 cfg_bw_1_0;
+ u8 cfg_txcal_man_en;
+ u8 cfg_phase_man_4_0;
+ u8 cfg_quad_man_1_0;
+ u8 cfg_txcal_shift_code_5_0;
+ u8 cfg_txcal_valid_sel_3_0;
+ u8 cfg_txcal_en;
+ u8 cfg_cdr_kf_2_0;
+ u8 cfg_cdr_m_7_0;
+ u8 cfg_pi_bw_3_0;
+ u8 cfg_pi_steps_1_0;
+ u8 cfg_dis_2ndorder;
+ u8 cfg_ctle_rstn;
+ u8 r_dfe_rstn;
+ u8 cfg_alos_thr_2_0;
+ u8 cfg_itx_ipcml_base_1_0;
+ u8 cfg_rx_reserve_7_0;
+ u8 cfg_rx_reserve_15_8;
+ u8 cfg_rxterm_2_0;
+ u8 cfg_fom_selm;
+ u8 cfg_rx_sp_ctle_1_0;
+ u8 cfg_isel_ctle_1_0;
+ u8 cfg_vga_ctrl_byp_4_0;
+ u8 cfg_vga_byp;
+ u8 cfg_agc_adpt_byp;
+ u8 cfg_eqr_byp;
+ u8 cfg_eqr_force_3_0;
+ u8 cfg_eqc_force_3_0;
+ u8 cfg_sum_setcm_en;
+ u8 cfg_init_pos_iscan_6_0;
+ u8 cfg_init_pos_ipi_6_0;
+ u8 cfg_dfedig_m_2_0;
+ u8 cfg_en_dfedig;
+ u8 cfg_pi_DFE_en;
+ u8 cfg_tx2rx_lp_en;
+ u8 cfg_txlb_en;
+ u8 cfg_rx2tx_lp_en;
+ u8 cfg_rxlb_en;
+ u8 r_tx_pol_inv;
+ u8 r_rx_pol_inv;
+};
+
+struct sparx5_sd10g28_media_preset {
+ u8 cfg_en_adv;
+ u8 cfg_en_main;
+ u8 cfg_en_dly;
+ u8 cfg_tap_adv_3_0;
+ u8 cfg_tap_main;
+ u8 cfg_tap_dly_4_0;
+ u8 cfg_vga_ctrl_3_0;
+ u8 cfg_vga_cp_2_0;
+ u8 cfg_eq_res_3_0;
+ u8 cfg_eq_r_byp;
+ u8 cfg_eq_c_force_3_0;
+ u8 cfg_alos_thr_3_0;
+};
+
+struct sparx5_sd10g28_mode_preset {
+ u8 bwidth; /* interface width: 10/16/20/32/64 */
+ enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
+ u8 rate; /* Rate of network interface */
+ u8 dfe_tap;
+ u8 dfe_enable;
+ u8 pi_bw_gen1;
+ u8 duty_cycle; /* Set output level to half/full */
+};
+
+struct sparx5_sd10g28_args {
+ bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */
+ bool no_pwrcycle:1; /* Omit initial power-cycle */
+ bool txinvert:1; /* Enable inversion of output data */
+ bool rxinvert:1; /* Enable inversion of input data */
+ bool txmargin:1; /* Set output level to half/full */
+ u16 txswing; /* Set output level */
+ bool mute:1; /* Mute Output Buffer */
+ bool is_6g:1;
+ bool reg_rst:1;
+};
+
+struct sparx5_sd10g28_params {
+ u8 cmu_sel;
+ u8 is_6g;
+ u8 skip_cmu_cfg;
+ u8 cfg_lane_reserve_7_0;
+ u8 cfg_ssc_rtl_clk_sel;
+ u8 cfg_lane_reserve_15_8;
+ u8 cfg_txrate_1_0;
+ u8 cfg_rxrate_1_0;
+ u8 r_d_width_ctrl_2_0;
+ u8 cfg_pma_tx_ck_bitwidth_2_0;
+ u8 cfg_rxdiv_sel_2_0;
+ u8 r_pcs2pma_phymode_4_0;
+ u8 cfg_lane_id_2_0;
+ u8 cfg_cdrck_en;
+ u8 cfg_dfeck_en;
+ u8 cfg_dfe_pd;
+ u8 cfg_dfetap_en_5_1;
+ u8 cfg_erramp_pd;
+ u8 cfg_pi_DFE_en;
+ u8 cfg_pi_en;
+ u8 cfg_pd_ctle;
+ u8 cfg_summer_en;
+ u8 cfg_pd_rx_cktree;
+ u8 cfg_pd_clk;
+ u8 cfg_pd_cml;
+ u8 cfg_pd_driver;
+ u8 cfg_rx_reg_pu;
+ u8 cfg_d_cdr_pd;
+ u8 cfg_pd_sq;
+ u8 cfg_rxdet_en;
+ u8 cfg_rxdet_str;
+ u8 r_multi_lane_mode;
+ u8 cfg_en_adv;
+ u8 cfg_en_main;
+ u8 cfg_en_dly;
+ u8 cfg_tap_adv_3_0;
+ u8 cfg_tap_main;
+ u8 cfg_tap_dly_4_0;
+ u8 cfg_vga_ctrl_3_0;
+ u8 cfg_vga_cp_2_0;
+ u8 cfg_eq_res_3_0;
+ u8 cfg_eq_r_byp;
+ u8 cfg_eq_c_force_3_0;
+ u8 cfg_en_dfedig;
+ u8 cfg_sum_setcm_en;
+ u8 cfg_en_preemph;
+ u8 cfg_itx_ippreemp_base_1_0;
+ u8 cfg_itx_ipdriver_base_2_0;
+ u8 cfg_ibias_tune_reserve_5_0;
+ u8 cfg_txswing_half;
+ u8 cfg_dis_2nd_order;
+ u8 cfg_rx_ssc_lh;
+ u8 cfg_pi_floop_steps_1_0;
+ u8 cfg_pi_ext_dac_23_16;
+ u8 cfg_pi_ext_dac_15_8;
+ u8 cfg_iscan_ext_dac_7_0;
+ u8 cfg_cdr_kf_gen1_2_0;
+ u8 cfg_cdr_kf_gen2_2_0;
+ u8 cfg_cdr_kf_gen3_2_0;
+ u8 cfg_cdr_kf_gen4_2_0;
+ u8 r_cdr_m_gen1_7_0;
+ u8 cfg_pi_bw_gen1_3_0;
+ u8 cfg_pi_bw_gen2;
+ u8 cfg_pi_bw_gen3;
+ u8 cfg_pi_bw_gen4;
+ u8 cfg_pi_ext_dac_7_0;
+ u8 cfg_pi_steps;
+ u8 cfg_mp_max_3_0;
+ u8 cfg_rstn_dfedig;
+ u8 cfg_alos_thr_3_0;
+ u8 cfg_predrv_slewrate_1_0;
+ u8 cfg_itx_ipcml_base_1_0;
+ u8 cfg_ip_pre_base_1_0;
+ u8 r_cdr_m_gen2_7_0;
+ u8 r_cdr_m_gen3_7_0;
+ u8 r_cdr_m_gen4_7_0;
+ u8 r_en_auto_cdr_rstn;
+ u8 cfg_oscal_afe;
+ u8 cfg_pd_osdac_afe;
+ u8 cfg_resetb_oscal_afe[2];
+ u8 cfg_center_spreading;
+ u8 cfg_m_cnt_maxval_4_0;
+ u8 cfg_ncnt_maxval_7_0;
+ u8 cfg_ncnt_maxval_10_8;
+ u8 cfg_ssc_en;
+ u8 cfg_tx2rx_lp_en;
+ u8 cfg_txlb_en;
+ u8 cfg_rx2tx_lp_en;
+ u8 cfg_rxlb_en;
+ u8 r_tx_pol_inv;
+ u8 r_rx_pol_inv;
+ u8 fx_100;
+};
+
+static struct sparx5_sd25g28_media_preset media_presets_25g[] = {
+ { /* ETH_MEDIA_DEFAULT */
+ .cfg_en_adv = 0,
+ .cfg_en_main = 1,
+ .cfg_en_dly = 0,
+ .cfg_tap_adv_3_0 = 0,
+ .cfg_tap_main = 1,
+ .cfg_tap_dly_4_0 = 0,
+ .cfg_eq_c_force_3_0 = 0xf,
+ .cfg_vga_ctrl_byp_4_0 = 4,
+ .cfg_eq_r_force_3_0 = 12,
+ .cfg_alos_thr_2_0 = 7,
+ },
+ { /* ETH_MEDIA_SR */
+ .cfg_en_adv = 1,
+ .cfg_en_main = 1,
+ .cfg_en_dly = 1,
+ .cfg_tap_adv_3_0 = 0,
+ .cfg_tap_main = 1,
+ .cfg_tap_dly_4_0 = 0x10,
+ .cfg_eq_c_force_3_0 = 0xf,
+ .cfg_vga_ctrl_byp_4_0 = 8,
+ .cfg_eq_r_force_3_0 = 4,
+ .cfg_alos_thr_2_0 = 0,
+ },
+ { /* ETH_MEDIA_DAC */
+ .cfg_en_adv = 0,
+ .cfg_en_main = 1,
+ .cfg_en_dly = 0,
+ .cfg_tap_adv_3_0 = 0,
+ .cfg_tap_main = 1,
+ .cfg_tap_dly_4_0 = 0,
+ .cfg_eq_c_force_3_0 = 0xf,
+ .cfg_vga_ctrl_byp_4_0 = 8,
+ .cfg_eq_r_force_3_0 = 0xc,
+ .cfg_alos_thr_2_0 = 0,
+ },
+};
+
+static struct sparx5_sd25g28_mode_preset mode_presets_25g[] = {
+ { /* SPX5_SD25G28_MODE_PRESET_25000 */
+ .bitwidth = 40,
+ .tx_pre_div = 0,
+ .fifo_ck_div = 0,
+ .pre_divsel = 1,
+ .vco_div_mode = 0,
+ .sel_div = 15,
+ .ck_bitwidth = 3,
+ .subrate = 0,
+ .com_txcal_en = 0,
+ .com_tx_reserve_msb = (0x26 << 1),
+ .com_tx_reserve_lsb = 0xf0,
+ .cfg_itx_ipcml_base = 0,
+ .tx_reserve_msb = 0xcc,
+ .tx_reserve_lsb = 0xfe,
+ .bw = 3,
+ .rxterm = 0,
+ .dfe_enable = 1,
+ .dfe_tap = 0x1f,
+ .txmargin = 1,
+ .cfg_ctle_rstn = 1,
+ .r_dfe_rstn = 1,
+ .cfg_pi_bw_3_0 = 0,
+ .tx_tap_dly = 8,
+ .tx_tap_adv = 0xc,
+ },
+ { /* SPX5_SD25G28_MODE_PRESET_10000 */
+ .bitwidth = 64,
+ .tx_pre_div = 0,
+ .fifo_ck_div = 2,
+ .pre_divsel = 0,
+ .vco_div_mode = 1,
+ .sel_div = 9,
+ .ck_bitwidth = 0,
+ .subrate = 0,
+ .com_txcal_en = 1,
+ .com_tx_reserve_msb = (0x20 << 1),
+ .com_tx_reserve_lsb = 0x40,
+ .cfg_itx_ipcml_base = 0,
+ .tx_reserve_msb = 0x4c,
+ .tx_reserve_lsb = 0x44,
+ .bw = 3,
+ .cfg_pi_bw_3_0 = 0,
+ .rxterm = 3,
+ .dfe_enable = 1,
+ .dfe_tap = 0x1f,
+ .txmargin = 0,
+ .cfg_ctle_rstn = 1,
+ .r_dfe_rstn = 1,
+ .tx_tap_dly = 0,
+ .tx_tap_adv = 0,
+ },
+ { /* SPX5_SD25G28_MODE_PRESET_5000 */
+ .bitwidth = 64,
+ .tx_pre_div = 0,
+ .fifo_ck_div = 2,
+ .pre_divsel = 0,
+ .vco_div_mode = 2,
+ .sel_div = 9,
+ .ck_bitwidth = 0,
+ .subrate = 0,
+ .com_txcal_en = 1,
+ .com_tx_reserve_msb = (0x20 << 1),
+ .com_tx_reserve_lsb = 0,
+ .cfg_itx_ipcml_base = 0,
+ .tx_reserve_msb = 0xe,
+ .tx_reserve_lsb = 0x80,
+ .bw = 0,
+ .rxterm = 0,
+ .cfg_pi_bw_3_0 = 6,
+ .dfe_enable = 0,
+ .dfe_tap = 0,
+ .tx_tap_dly = 0,
+ .tx_tap_adv = 0,
+ },
+ { /* SPX5_SD25G28_MODE_PRESET_SD_2G5 */
+ .bitwidth = 10,
+ .tx_pre_div = 0,
+ .fifo_ck_div = 0,
+ .pre_divsel = 0,
+ .vco_div_mode = 1,
+ .sel_div = 6,
+ .ck_bitwidth = 3,
+ .subrate = 2,
+ .com_txcal_en = 1,
+ .com_tx_reserve_msb = (0x26 << 1),
+ .com_tx_reserve_lsb = (0xf << 4),
+ .cfg_itx_ipcml_base = 2,
+ .tx_reserve_msb = 0x8,
+ .tx_reserve_lsb = 0x8a,
+ .bw = 0,
+ .cfg_pi_bw_3_0 = 0,
+ .rxterm = (1 << 2),
+ .dfe_enable = 0,
+ .dfe_tap = 0,
+ .tx_tap_dly = 0,
+ .tx_tap_adv = 0,
+ },
+ { /* SPX5_SD25G28_MODE_PRESET_1000BASEX */
+ .bitwidth = 10,
+ .tx_pre_div = 0,
+ .fifo_ck_div = 1,
+ .pre_divsel = 0,
+ .vco_div_mode = 1,
+ .sel_div = 8,
+ .ck_bitwidth = 3,
+ .subrate = 3,
+ .com_txcal_en = 1,
+ .com_tx_reserve_msb = (0x26 << 1),
+ .com_tx_reserve_lsb = 0xf0,
+ .cfg_itx_ipcml_base = 0,
+ .tx_reserve_msb = 0x8,
+ .tx_reserve_lsb = 0xce,
+ .bw = 0,
+ .rxterm = 0,
+ .cfg_pi_bw_3_0 = 0,
+ .dfe_enable = 0,
+ .dfe_tap = 0,
+ .tx_tap_dly = 0,
+ .tx_tap_adv = 0,
+ },
+};
+
+static struct sparx5_sd10g28_media_preset media_presets_10g[] = {
+ { /* ETH_MEDIA_DEFAULT */
+ .cfg_en_adv = 0,
+ .cfg_en_main = 1,
+ .cfg_en_dly = 0,
+ .cfg_tap_adv_3_0 = 0,
+ .cfg_tap_main = 1,
+ .cfg_tap_dly_4_0 = 0,
+ .cfg_vga_ctrl_3_0 = 5,
+ .cfg_vga_cp_2_0 = 0,
+ .cfg_eq_res_3_0 = 0xa,
+ .cfg_eq_r_byp = 1,
+ .cfg_eq_c_force_3_0 = 0x8,
+ .cfg_alos_thr_3_0 = 0x3,
+ },
+ { /* ETH_MEDIA_SR */
+ .cfg_en_adv = 1,
+ .cfg_en_main = 1,
+ .cfg_en_dly = 1,
+ .cfg_tap_adv_3_0 = 0,
+ .cfg_tap_main = 1,
+ .cfg_tap_dly_4_0 = 0xc,
+ .cfg_vga_ctrl_3_0 = 0xa,
+ .cfg_vga_cp_2_0 = 0x4,
+ .cfg_eq_res_3_0 = 0xa,
+ .cfg_eq_r_byp = 1,
+ .cfg_eq_c_force_3_0 = 0xF,
+ .cfg_alos_thr_3_0 = 0x3,
+ },
+ { /* ETH_MEDIA_DAC */
+ .cfg_en_adv = 1,
+ .cfg_en_main = 1,
+ .cfg_en_dly = 1,
+ .cfg_tap_adv_3_0 = 12,
+ .cfg_tap_main = 1,
+ .cfg_tap_dly_4_0 = 8,
+ .cfg_vga_ctrl_3_0 = 0xa,
+ .cfg_vga_cp_2_0 = 4,
+ .cfg_eq_res_3_0 = 0xa,
+ .cfg_eq_r_byp = 1,
+ .cfg_eq_c_force_3_0 = 0xf,
+ .cfg_alos_thr_3_0 = 0x0,
+ }
+};
+
+static struct sparx5_sd10g28_mode_preset mode_presets_10g[] = {
+ { /* SPX5_SD10G28_MODE_PRESET_10000 */
+ .bwidth = 64,
+ .cmu_sel = SPX5_SD10G28_CMU_MAIN,
+ .rate = 0x0,
+ .dfe_enable = 1,
+ .dfe_tap = 0x1f,
+ .pi_bw_gen1 = 0x0,
+ .duty_cycle = 0x2,
+ },
+ { /* SPX5_SD10G28_MODE_PRESET_SFI_5000_6G */
+ .bwidth = 16,
+ .cmu_sel = SPX5_SD10G28_CMU_MAIN,
+ .rate = 0x1,
+ .dfe_enable = 0,
+ .dfe_tap = 0,
+ .pi_bw_gen1 = 0x5,
+ .duty_cycle = 0x0,
+ },
+ { /* SPX5_SD10G28_MODE_PRESET_SFI_5000_10G */
+ .bwidth = 64,
+ .cmu_sel = SPX5_SD10G28_CMU_MAIN,
+ .rate = 0x1,
+ .dfe_enable = 0,
+ .dfe_tap = 0,
+ .pi_bw_gen1 = 0x5,
+ .duty_cycle = 0x0,
+ },
+ { /* SPX5_SD10G28_MODE_PRESET_QSGMII */
+ .bwidth = 20,
+ .cmu_sel = SPX5_SD10G28_CMU_AUX1,
+ .rate = 0x1,
+ .dfe_enable = 0,
+ .dfe_tap = 0,
+ .pi_bw_gen1 = 0x5,
+ .duty_cycle = 0x0,
+ },
+ { /* SPX5_SD10G28_MODE_PRESET_SD_2G5 */
+ .bwidth = 10,
+ .cmu_sel = SPX5_SD10G28_CMU_AUX2,
+ .rate = 0x2,
+ .dfe_enable = 0,
+ .dfe_tap = 0,
+ .pi_bw_gen1 = 0x7,
+ .duty_cycle = 0x0,
+ },
+ { /* SPX5_SD10G28_MODE_PRESET_1000BASEX */
+ .bwidth = 10,
+ .cmu_sel = SPX5_SD10G28_CMU_AUX1,
+ .rate = 0x3,
+ .dfe_enable = 0,
+ .dfe_tap = 0,
+ .pi_bw_gen1 = 0x7,
+ .duty_cycle = 0x0,
+ },
+};
+
+/* map from SD25G28 interface width to configuration value */
+static u8 sd25g28_get_iw_setting(struct udevice *dev, const u8 interface_width)
+{
+ switch (interface_width) {
+ case 10: return 0;
+ case 16: return 1;
+ case 32: return 3;
+ case 40: return 4;
+ case 64: return 5;
+ default:
+ dev_err(dev, "%s: Illegal value %d for interface width\n",
+ __func__, interface_width);
+ }
+ return 0;
+}
+
+/* map from SD10G28 interface width to configuration value */
+static u8 sd10g28_get_iw_setting(struct udevice *dev, const u8 interface_width)
+{
+ switch (interface_width) {
+ case 10: return 0;
+ case 16: return 1;
+ case 20: return 2;
+ case 32: return 3;
+ case 40: return 4;
+ case 64: return 7;
+ default:
+ dev_err(dev, "%s: Illegal value %d for interface width\n", __func__,
+ interface_width);
+ return 0;
+ }
+}
+
+static int sparx5_sd10g25_get_mode_preset(struct sparx5_serdes_macro *macro,
+ struct sparx5_sd25g28_mode_preset *mode)
+{
+ switch (macro->serdesmode) {
+ case SPX5_SD_MODE_SFI:
+ if (macro->speed == SPEED_25000)
+ *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000];
+ else if (macro->speed == SPEED_10000)
+ *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_10000];
+ else if (macro->speed == SPEED_5000)
+ *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_5000];
+ break;
+ case SPX5_SD_MODE_2G5:
+ *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_SD_2G5];
+ break;
+ case SPX5_SD_MODE_1000BASEX:
+ *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_1000BASEX];
+ break;
+ case SPX5_SD_MODE_100FX:
+ /* Not supported */
+ return -EINVAL;
+ default:
+ *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000];
+ break;
+ }
+ return 0;
+}
+
+static int sparx5_sd10g28_get_mode_preset(struct sparx5_serdes_macro *macro,
+ struct sparx5_sd10g28_mode_preset *mode,
+ struct sparx5_sd10g28_args *args)
+{
+ switch (macro->serdesmode) {
+ case SPX5_SD_MODE_SFI:
+ if (macro->speed == SPEED_10000) {
+ *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000];
+ } else if (macro->speed == SPEED_5000) {
+ if (args->is_6g)
+ *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_6G];
+ else
+ *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_10G];
+ } else {
+ dev_err(macro->priv->dev, "%s: Illegal speed: %02u, sidx: %02u, mode (%u)",
+ __func__, macro->speed, macro->sidx,
+ macro->serdesmode);
+ return -EINVAL;
+ }
+ break;
+ case SPX5_SD_MODE_QSGMII:
+ *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_QSGMII];
+ break;
+ case SPX5_SD_MODE_2G5:
+ *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SD_2G5];
+ break;
+ case SPX5_SD_MODE_100FX:
+ case SPX5_SD_MODE_1000BASEX:
+ *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_1000BASEX];
+ break;
+ default:
+ *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000];
+ break;
+ }
+ return 0;
+}
+
+static void sparx5_sd25g28_get_params(struct sparx5_serdes_macro *macro,
+ struct sparx5_sd25g28_media_preset *media,
+ struct sparx5_sd25g28_mode_preset *mode,
+ struct sparx5_sd25g28_args *args,
+ struct sparx5_sd25g28_params *params)
+{
+ u8 iw = sd25g28_get_iw_setting(macro->priv->dev, mode->bitwidth);
+ struct sparx5_sd25g28_params init = {
+ .r_d_width_ctrl_2_0 = iw,
+ .r_txfifo_ck_div_pmad_2_0 = mode->fifo_ck_div,
+ .r_rxfifo_ck_div_pmad_2_0 = mode->fifo_ck_div,
+ .cfg_vco_div_mode_1_0 = mode->vco_div_mode,
+ .cfg_pre_divsel_1_0 = mode->pre_divsel,
+ .cfg_sel_div_3_0 = mode->sel_div,
+ .cfg_vco_start_code_3_0 = 0,
+ .cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth,
+ .cfg_tx_prediv_1_0 = mode->tx_pre_div,
+ .cfg_rxdiv_sel_2_0 = mode->ck_bitwidth,
+ .cfg_tx_subrate_2_0 = mode->subrate,
+ .cfg_rx_subrate_2_0 = mode->subrate,
+ .r_multi_lane_mode = 0,
+ .cfg_cdrck_en = 1,
+ .cfg_dfeck_en = mode->dfe_enable,
+ .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1,
+ .cfg_dfedmx_pd = 1,
+ .cfg_dfetap_en_5_1 = mode->dfe_tap,
+ .cfg_dmux_pd = 0,
+ .cfg_dmux_clk_pd = 1,
+ .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1,
+ .cfg_pi_DFE_en = mode->dfe_enable,
+ .cfg_pi_en = 1,
+ .cfg_pd_ctle = 0,
+ .cfg_summer_en = 1,
+ .cfg_pmad_ck_pd = 0,
+ .cfg_pd_clk = 0,
+ .cfg_pd_cml = 0,
+ .cfg_pd_driver = 0,
+ .cfg_rx_reg_pu = 1,
+ .cfg_pd_rms_det = 1,
+ .cfg_dcdr_pd = 0,
+ .cfg_ecdr_pd = 1,
+ .cfg_pd_sq = 1,
+ .cfg_itx_ipdriver_base_2_0 = mode->txmargin,
+ .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0,
+ .cfg_tap_main = media->cfg_tap_main,
+ .cfg_en_main = media->cfg_en_main,
+ .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0,
+ .cfg_en_adv = media->cfg_en_adv,
+ .cfg_en_dly = media->cfg_en_dly,
+ .cfg_iscan_en = 0,
+ .l1_pcs_en_fast_iscan = 0,
+ .l0_cfg_bw_1_0 = 0,
+ .cfg_en_dummy = 0,
+ .cfg_pll_reserve_3_0 = args->com_pll_reserve,
+ .l0_cfg_txcal_en = mode->com_txcal_en,
+ .l0_cfg_tx_reserve_15_8 = mode->com_tx_reserve_msb,
+ .l0_cfg_tx_reserve_7_0 = mode->com_tx_reserve_lsb,
+ .cfg_tx_reserve_15_8 = mode->tx_reserve_msb,
+ .cfg_tx_reserve_7_0 = mode->tx_reserve_lsb,
+ .cfg_bw_1_0 = mode->bw,
+ .cfg_txcal_man_en = 1,
+ .cfg_phase_man_4_0 = 0,
+ .cfg_quad_man_1_0 = 0,
+ .cfg_txcal_shift_code_5_0 = 2,
+ .cfg_txcal_valid_sel_3_0 = 4,
+ .cfg_txcal_en = 0,
+ .cfg_cdr_kf_2_0 = 1,
+ .cfg_cdr_m_7_0 = 6,
+ .cfg_pi_bw_3_0 = mode->cfg_pi_bw_3_0,
+ .cfg_pi_steps_1_0 = 0,
+ .cfg_dis_2ndorder = 1,
+ .cfg_ctle_rstn = mode->cfg_ctle_rstn,
+ .r_dfe_rstn = mode->r_dfe_rstn,
+ .cfg_alos_thr_2_0 = media->cfg_alos_thr_2_0,
+ .cfg_itx_ipcml_base_1_0 = mode->cfg_itx_ipcml_base,
+ .cfg_rx_reserve_7_0 = 0xbf,
+ .cfg_rx_reserve_15_8 = 0x61,
+ .cfg_rxterm_2_0 = mode->rxterm,
+ .cfg_fom_selm = 0,
+ .cfg_rx_sp_ctle_1_0 = 0,
+ .cfg_isel_ctle_1_0 = 0,
+ .cfg_vga_ctrl_byp_4_0 = media->cfg_vga_ctrl_byp_4_0,
+ .cfg_vga_byp = 1,
+ .cfg_agc_adpt_byp = 1,
+ .cfg_eqr_byp = 1,
+ .cfg_eqr_force_3_0 = media->cfg_eq_r_force_3_0,
+ .cfg_eqc_force_3_0 = media->cfg_eq_c_force_3_0,
+ .cfg_sum_setcm_en = 1,
+ .cfg_pi_dfe_en = 1,
+ .cfg_init_pos_iscan_6_0 = 6,
+ .cfg_init_pos_ipi_6_0 = 9,
+ .cfg_dfedig_m_2_0 = 6,
+ .cfg_en_dfedig = mode->dfe_enable,
+ .r_d_width_ctrl_from_hwt = 0,
+ .r_reg_manual = 1,
+ .reg_rst = args->reg_rst,
+ .cfg_jc_byp = 1,
+ .cfg_common_reserve_7_0 = 1,
+ .cfg_pll_lol_set = 1,
+ .cfg_tx2rx_lp_en = 0,
+ .cfg_txlb_en = 0,
+ .cfg_rx2tx_lp_en = 0,
+ .cfg_rxlb_en = 0,
+ .r_tx_pol_inv = args->txinvert,
+ .r_rx_pol_inv = args->rxinvert,
+ };
+
+ *params = init;
+}
+
+static void sparx5_sd10g28_get_params(struct sparx5_serdes_macro *macro,
+ struct sparx5_sd10g28_media_preset *media,
+ struct sparx5_sd10g28_mode_preset *mode,
+ struct sparx5_sd10g28_args *args,
+ struct sparx5_sd10g28_params *params)
+{
+ u8 iw = sd10g28_get_iw_setting(macro->priv->dev, mode->bwidth);
+ struct sparx5_sd10g28_params init = {
+ .skip_cmu_cfg = args->skip_cmu_cfg,
+ .is_6g = args->is_6g,
+ .cmu_sel = mode->cmu_sel,
+ .cfg_lane_reserve_7_0 = (mode->cmu_sel % 2) << 6,
+ .cfg_ssc_rtl_clk_sel = (mode->cmu_sel / 2),
+ .cfg_lane_reserve_15_8 = mode->duty_cycle,
+ .cfg_txrate_1_0 = mode->rate,
+ .cfg_rxrate_1_0 = mode->rate,
+ .fx_100 = macro->serdesmode == SPX5_SD_MODE_100FX,
+ .r_d_width_ctrl_2_0 = iw,
+ .cfg_pma_tx_ck_bitwidth_2_0 = iw,
+ .cfg_rxdiv_sel_2_0 = iw,
+ .r_pcs2pma_phymode_4_0 = 0,
+ .cfg_lane_id_2_0 = 0,
+ .cfg_cdrck_en = 1,
+ .cfg_dfeck_en = mode->dfe_enable,
+ .cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1,
+ .cfg_dfetap_en_5_1 = mode->dfe_tap,
+ .cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1,
+ .cfg_pi_DFE_en = mode->dfe_enable,
+ .cfg_pi_en = 1,
+ .cfg_pd_ctle = 0,
+ .cfg_summer_en = 1,
+ .cfg_pd_rx_cktree = 0,
+ .cfg_pd_clk = 0,
+ .cfg_pd_cml = 0,
+ .cfg_pd_driver = 0,
+ .cfg_rx_reg_pu = 1,
+ .cfg_d_cdr_pd = 0,
+ .cfg_pd_sq = mode->dfe_enable,
+ .cfg_rxdet_en = 0,
+ .cfg_rxdet_str = 0,
+ .r_multi_lane_mode = 0,
+ .cfg_en_adv = media->cfg_en_adv,
+ .cfg_en_main = 1,
+ .cfg_en_dly = media->cfg_en_dly,
+ .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0,
+ .cfg_tap_main = media->cfg_tap_main,
+ .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0,
+ .cfg_vga_ctrl_3_0 = media->cfg_vga_ctrl_3_0,
+ .cfg_vga_cp_2_0 = media->cfg_vga_cp_2_0,
+ .cfg_eq_res_3_0 = media->cfg_eq_res_3_0,
+ .cfg_eq_r_byp = media->cfg_eq_r_byp,
+ .cfg_eq_c_force_3_0 = media->cfg_eq_c_force_3_0,
+ .cfg_en_dfedig = mode->dfe_enable,
+ .cfg_sum_setcm_en = 1,
+ .cfg_en_preemph = 0,
+ .cfg_itx_ippreemp_base_1_0 = 0,
+ .cfg_itx_ipdriver_base_2_0 = (args->txswing >> 6),
+ .cfg_ibias_tune_reserve_5_0 = (args->txswing & 63),
+ .cfg_txswing_half = (args->txmargin),
+ .cfg_dis_2nd_order = 0x1,
+ .cfg_rx_ssc_lh = 0x0,
+ .cfg_pi_floop_steps_1_0 = 0x0,
+ .cfg_pi_ext_dac_23_16 = (1 << 5),
+ .cfg_pi_ext_dac_15_8 = (0 << 6),
+ .cfg_iscan_ext_dac_7_0 = (1 << 7) + 9,
+ .cfg_cdr_kf_gen1_2_0 = 1,
+ .cfg_cdr_kf_gen2_2_0 = 1,
+ .cfg_cdr_kf_gen3_2_0 = 1,
+ .cfg_cdr_kf_gen4_2_0 = 1,
+ .r_cdr_m_gen1_7_0 = 4,
+ .cfg_pi_bw_gen1_3_0 = mode->pi_bw_gen1,
+ .cfg_pi_bw_gen2 = mode->pi_bw_gen1,
+ .cfg_pi_bw_gen3 = mode->pi_bw_gen1,
+ .cfg_pi_bw_gen4 = mode->pi_bw_gen1,
+ .cfg_pi_ext_dac_7_0 = 3,
+ .cfg_pi_steps = 0,
+ .cfg_mp_max_3_0 = 1,
+ .cfg_rstn_dfedig = mode->dfe_enable,
+ .cfg_alos_thr_3_0 = media->cfg_alos_thr_3_0,
+ .cfg_predrv_slewrate_1_0 = 3,
+ .cfg_itx_ipcml_base_1_0 = 0,
+ .cfg_ip_pre_base_1_0 = 0,
+ .r_cdr_m_gen2_7_0 = 2,
+ .r_cdr_m_gen3_7_0 = 2,
+ .r_cdr_m_gen4_7_0 = 2,
+ .r_en_auto_cdr_rstn = 0,
+ .cfg_oscal_afe = 1,
+ .cfg_pd_osdac_afe = 0,
+ .cfg_resetb_oscal_afe[0] = 0,
+ .cfg_resetb_oscal_afe[1] = 1,
+ .cfg_center_spreading = 0,
+ .cfg_m_cnt_maxval_4_0 = 15,
+ .cfg_ncnt_maxval_7_0 = 32,
+ .cfg_ncnt_maxval_10_8 = 6,
+ .cfg_ssc_en = 1,
+ .cfg_tx2rx_lp_en = 0,
+ .cfg_txlb_en = 0,
+ .cfg_rx2tx_lp_en = 0,
+ .cfg_rxlb_en = 0,
+ .r_tx_pol_inv = args->txinvert,
+ .r_rx_pol_inv = args->rxinvert,
+ };
+
+ *params = init;
+}
+
+static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv,
+ u32 cmu_idx,
+ void __iomem *cmu_tgt,
+ void __iomem *cmu_cfg_tgt,
+ u32 spd10g)
+{
+ void __iomem **regs = priv->regs;
+ struct udevice *dev = priv->dev;
+ int value;
+
+ cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);
+ cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);
+
+ if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||
+ cmu_idx == 10 || cmu_idx == 13) {
+ spd10g = 0;
+ }
+
+ sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1),
+ SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,
+ cmu_cfg_tgt,
+ SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),
+ SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,
+ cmu_cfg_tgt,
+ SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1),
+ SD_CMU_CFG_SD_CMU_CFG_CMU_RST,
+ cmu_cfg_tgt,
+ SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) |
+ SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) |
+ SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) |
+ SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) |
+ SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0),
+ SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT |
+ SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT |
+ SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT |
+ SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT |
+ SD_CMU_CMU_45_R_EN_RATECHG_CTRL,
+ cmu_tgt,
+ SD_CMU_CMU_45(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0),
+ SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0,
+ cmu_tgt,
+ SD_CMU_CMU_47(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0),
+ SD_CMU_CMU_1B_CFG_RESERVE_7_0,
+ cmu_tgt,
+ SD_CMU_CMU_1B(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1),
+ SD_CMU_CMU_0D_CFG_JC_BYP,
+ cmu_tgt,
+ SD_CMU_CMU_0D(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1),
+ SD_CMU_CMU_1F_CFG_VTUNE_SEL,
+ cmu_tgt,
+ SD_CMU_CMU_1F(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3),
+ SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0,
+ cmu_tgt,
+ SD_CMU_CMU_00(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(3),
+ SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0,
+ cmu_tgt,
+ SD_CMU_CMU_05(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(1),
+ SD_CMU_CMU_30_R_PLL_DLOL_EN,
+ cmu_tgt,
+ SD_CMU_CMU_30(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CMU_09_CFG_SW_10G_SET(spd10g),
+ SD_CMU_CMU_09_CFG_SW_10G,
+ cmu_tgt,
+ SD_CMU_CMU_09(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0),
+ SD_CMU_CFG_SD_CMU_CFG_CMU_RST,
+ cmu_cfg_tgt,
+ SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
+
+ udelay(20 * 1000);
+
+ sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0),
+ SD_CMU_CMU_44_R_PLL_RSTN,
+ cmu_tgt,
+ SD_CMU_CMU_44(cmu_idx));
+
+ sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(1),
+ SD_CMU_CMU_44_R_PLL_RSTN,
+ cmu_tgt,
+ SD_CMU_CMU_44(cmu_idx));
+
+ udelay(20 * 1000);
+
+ value = readl(sdx5_addr(regs, SD_CMU_CMU_E0(cmu_idx)));
+ value = SD_CMU_CMU_E0_PLL_LOL_UDL_GET(value);
+
+ if (value) {
+ dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value);
+ return -EINVAL;
+ }
+ sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0),
+ SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD,
+ cmu_tgt,
+ SD_CMU_CMU_0D(cmu_idx));
+ return 0;
+}
+
+static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx)
+{
+ void __iomem *cmu_tgt, *cmu_cfg_tgt;
+ u32 spd10g = 1;
+
+ if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||
+ cmu_idx == 10 || cmu_idx == 13) {
+ spd10g = 0;
+ }
+
+ cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);
+ cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);
+
+ return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g);
+}
+
+/* Map of 6G/10G serdes mode and index to CMU index. */
+static const int
+sparx5_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][SPX5_SERDES_25G_START] = {
+ [SPX5_SD10G28_CMU_MAIN] = { 2, 2, 2, 2, 2,
+ 2, 2, 2, 5, 5,
+ 5, 5, 5, 5, 5,
+ 5, 8, 11, 11, 11,
+ 11, 11, 11, 11, 11 },
+ [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3,
+ 3, 3, 3, 3, 3,
+ 6, 6, 6, 6, 6,
+ 6, 6, 9, 9, 12,
+ 12, 12, 12, 12, 12 },
+ [SPX5_SD10G28_CMU_AUX2] = { 1, 1, 1, 1, 4,
+ 4, 4, 4, 4, 4,
+ 4, 4, 7, 7, 7,
+ 7, 7, 10, 10, 10,
+ 10, 13, 13, 13, 13 },
+ [SPX5_SD10G28_CMU_NONE] = { 1, 1, 1, 1, 4,
+ 4, 4, 4, 4, 4,
+ 4, 4, 7, 7, 7,
+ 7, 7, 10, 10, 10,
+ 10, 13, 13, 13, 13 },
+};
+
+/* Sparx5 - Get the index of the CMU which provides the clock for the specified
+ * serdes mode and index.
+ */
+static int sparx5_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index)
+{
+ return sparx5_serdes_cmu_map[mode][sd_index];
+}
+
+/* Map of 10G serdes mode and index to CMU index. */
+static const int
+lan969x_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][10] = {
+ [SPX5_SD10G28_CMU_MAIN] = { 2, 2, 2, 2, 2,
+ 2, 2, 2, 5, 5 },
+ [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3,
+ 3, 3, 3, 3, 3 },
+ [SPX5_SD10G28_CMU_AUX2] = { 1, 1, 1, 1, 4,
+ 4, 4, 4, 4, 4 },
+ [SPX5_SD10G28_CMU_NONE] = { 1, 1, 1, 1, 4,
+ 4, 4, 4, 4, 4 },
+};
+
+/* lan969x - Get the index of the CMU which provides the clock for the specified
+ * serdes mode and index.
+ */
+static int lan969x_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index)
+{
+ return lan969x_serdes_cmu_map[mode][sd_index];
+}
+
+static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv)
+{
+ void __iomem *cmu_inst, *cmu_cfg_inst;
+ int i;
+
+ /* Power down each CMU */
+ for (i = 0; i < priv->data->consts.cmu_max; i++) {
+ cmu_inst = sdx5_inst_get(priv, TARGET_SD_CMU, i);
+ cmu_cfg_inst = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, i);
+
+ sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),
+ SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, cmu_cfg_inst,
+ SD_CMU_CFG_SD_CMU_CFG(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(0),
+ SD_CMU_CMU_05_CFG_REFCK_TERM_EN, cmu_inst,
+ SD_CMU_CMU_05(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(0),
+ SD_CMU_CMU_09_CFG_EN_TX_CK_DN, cmu_inst,
+ SD_CMU_CMU_09(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_06_CFG_VCO_PD_SET(1),
+ SD_CMU_CMU_06_CFG_VCO_PD, cmu_inst,
+ SD_CMU_CMU_06(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(0),
+ SD_CMU_CMU_09_CFG_EN_TX_CK_UP, cmu_inst,
+ SD_CMU_CMU_09(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(1),
+ SD_CMU_CMU_08_CFG_CK_TREE_PD, cmu_inst,
+ SD_CMU_CMU_08(0));
+
+ sdx5_inst_rmw(
+ SD_CMU_CMU_0D_CFG_REFCK_PD_SET(1) |
+ SD_CMU_CMU_0D_CFG_PD_DIV64_SET(1) |
+ SD_CMU_CMU_0D_CFG_PD_DIV66_SET(1),
+ SD_CMU_CMU_0D_CFG_REFCK_PD |
+ SD_CMU_CMU_0D_CFG_PD_DIV64 |
+ SD_CMU_CMU_0D_CFG_PD_DIV66,
+ cmu_inst, SD_CMU_CMU_0D(0));
+
+ sdx5_inst_rmw(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(1),
+ SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, cmu_inst,
+ SD_CMU_CMU_06(0));
+ }
+
+ for (i = 0; i < SPX5_SERDES_25G_CNT; i++) {
+ sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(1),
+ SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,
+ priv, SD_LANE_25G_SD_LANE_CFG(i));
+
+ sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0),
+ SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,
+ priv, SD_LANE_25G_SD_LANE_CFG(i));
+
+ sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff),
+ SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
+ priv, SD25G_LANE_CMU_FF(i));
+
+ sdx5_rmw(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(1),
+ SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0,
+ priv, SD25G_LANE_CMU_31(i));
+
+ sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0),
+ SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
+ priv, SD25G_LANE_CMU_FF(i));
+ }
+}
+
+static void sparx5_sd25g28_reset(void __iomem *regs[],
+ struct sparx5_sd25g28_params *params,
+ u32 sd_index)
+{
+ if (params->reg_rst == 1) {
+ sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(1),
+ SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,
+ sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index)));
+
+ udelay(2000);
+
+ sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0),
+ SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,
+ sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index)));
+ }
+}
+
+static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro,
+ struct sparx5_sd25g28_params *params)
+{
+ struct sparx5_serdes_private *priv = macro->priv;
+ void __iomem **regs = priv->regs;
+ struct udevice *dev = priv->dev;
+ u32 sd_index = macro->stpidx;
+ u32 value;
+
+ sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(1),
+ SD_LANE_25G_SD_LANE_CFG_MACRO_RST,
+ priv,
+ SD_LANE_25G_SD_LANE_CFG(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF),
+ SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
+ priv,
+ SD25G_LANE_CMU_FF(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET
+ (params->r_d_width_ctrl_from_hwt) |
+ SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual),
+ SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT |
+ SD25G_LANE_CMU_1A_R_REG_MANUAL,
+ priv,
+ SD25G_LANE_CMU_1A(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET
+ (params->cfg_common_reserve_7_0),
+ SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0,
+ priv,
+ SD25G_LANE_CMU_31(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy),
+ SD25G_LANE_CMU_09_CFG_EN_DUMMY,
+ priv,
+ SD25G_LANE_CMU_09(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET
+ (params->cfg_pll_reserve_3_0),
+ SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0,
+ priv,
+ SD25G_LANE_CMU_13(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en),
+ SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN,
+ priv,
+ SD25G_LANE_CMU_40(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET
+ (params->l0_cfg_tx_reserve_15_8),
+ SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8,
+ priv,
+ SD25G_LANE_CMU_46(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET
+ (params->l0_cfg_tx_reserve_7_0),
+ SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0,
+ priv,
+ SD25G_LANE_CMU_45(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0),
+ SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
+ priv,
+ SD25G_LANE_CMU_0B(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(1),
+ SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
+ priv,
+ SD25G_LANE_CMU_0B(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(0),
+ SD25G_LANE_CMU_19_R_CK_RESETB,
+ priv,
+ SD25G_LANE_CMU_19(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(1),
+ SD25G_LANE_CMU_19_R_CK_RESETB,
+ priv,
+ SD25G_LANE_CMU_19(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0),
+ SD25G_LANE_CMU_18_R_PLL_RSTN,
+ priv,
+ SD25G_LANE_CMU_18(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(1),
+ SD25G_LANE_CMU_18_R_PLL_RSTN,
+ priv,
+ SD25G_LANE_CMU_18(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0),
+ SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0,
+ priv,
+ SD25G_LANE_CMU_1A(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET
+ (params->r_txfifo_ck_div_pmad_2_0) |
+ SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET
+ (params->r_rxfifo_ck_div_pmad_2_0),
+ SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 |
+ SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0,
+ priv,
+ SD25G_LANE_CMU_30(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) |
+ SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET
+ (params->cfg_vco_div_mode_1_0),
+ SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET |
+ SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0,
+ priv,
+ SD25G_LANE_CMU_0C(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET
+ (params->cfg_pre_divsel_1_0),
+ SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0,
+ priv,
+ SD25G_LANE_CMU_0D(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0),
+ SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0,
+ priv,
+ SD25G_LANE_CMU_0E(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0x00),
+ SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
+ priv,
+ SD25G_LANE_CMU_FF(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET
+ (params->cfg_pma_tx_ck_bitwidth_2_0),
+ SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0,
+ priv,
+ SD25G_LANE_LANE_0C(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET
+ (params->cfg_tx_prediv_1_0),
+ SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0,
+ priv,
+ SD25G_LANE_LANE_01(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET
+ (params->cfg_rxdiv_sel_2_0),
+ SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0,
+ priv,
+ SD25G_LANE_LANE_18(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET
+ (params->cfg_tx_subrate_2_0),
+ SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0,
+ priv,
+ SD25G_LANE_LANE_2C(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET
+ (params->cfg_rx_subrate_2_0),
+ SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0,
+ priv,
+ SD25G_LANE_LANE_28(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),
+ SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN,
+ priv,
+ SD25G_LANE_LANE_18(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET
+ (params->cfg_dfetap_en_5_1),
+ SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1,
+ priv,
+ SD25G_LANE_LANE_0F(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd),
+ SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD,
+ priv,
+ SD25G_LANE_LANE_18(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en),
+ SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN,
+ priv,
+ SD25G_LANE_LANE_1D(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd),
+ SD25G_LANE_LANE_19_LN_CFG_ECDR_PD,
+ priv,
+ SD25G_LANE_LANE_19(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET
+ (params->cfg_itx_ipdriver_base_2_0),
+ SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0,
+ priv,
+ SD25G_LANE_LANE_01(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0),
+ SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0,
+ priv,
+ SD25G_LANE_LANE_03(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0),
+ SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0,
+ priv,
+ SD25G_LANE_LANE_06(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) |
+ SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(params->cfg_en_dly),
+ SD25G_LANE_LANE_07_LN_CFG_EN_ADV |
+ SD25G_LANE_LANE_07_LN_CFG_EN_DLY,
+ priv,
+ SD25G_LANE_LANE_07(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET
+ (params->cfg_tx_reserve_15_8),
+ SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8,
+ priv,
+ SD25G_LANE_LANE_43(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET
+ (params->cfg_tx_reserve_7_0),
+ SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0,
+ priv,
+ SD25G_LANE_LANE_42(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0),
+ SD25G_LANE_LANE_05_LN_CFG_BW_1_0,
+ priv,
+ SD25G_LANE_LANE_05(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET
+ (params->cfg_txcal_man_en),
+ SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN,
+ priv,
+ SD25G_LANE_LANE_0B(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET
+ (params->cfg_txcal_shift_code_5_0),
+ SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0,
+ priv,
+ SD25G_LANE_LANE_0A(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET
+ (params->cfg_txcal_valid_sel_3_0),
+ SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0,
+ priv,
+ SD25G_LANE_LANE_09(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0),
+ SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0,
+ priv,
+ SD25G_LANE_LANE_1A(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0),
+ SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0,
+ priv,
+ SD25G_LANE_LANE_1B(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0),
+ SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0,
+ priv,
+ SD25G_LANE_LANE_2B(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET
+ (params->cfg_dis_2ndorder),
+ SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER,
+ priv,
+ SD25G_LANE_LANE_2C(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn),
+ SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN,
+ priv,
+ SD25G_LANE_LANE_2E(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET
+ (params->cfg_itx_ipcml_base_1_0),
+ SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0,
+ priv,
+ SD25G_LANE_LANE_00(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET
+ (params->cfg_rx_reserve_7_0),
+ SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0,
+ priv,
+ SD25G_LANE_LANE_44(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET
+ (params->cfg_rx_reserve_15_8),
+ SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8,
+ priv,
+ SD25G_LANE_LANE_45(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) |
+ SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(params->cfg_rxterm_2_0),
+ SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN |
+ SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0,
+ priv,
+ SD25G_LANE_LANE_0D(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET
+ (params->cfg_vga_ctrl_byp_4_0),
+ SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0,
+ priv,
+ SD25G_LANE_LANE_21(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET
+ (params->cfg_eqr_force_3_0),
+ SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0,
+ priv,
+ SD25G_LANE_LANE_22(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET
+ (params->cfg_eqc_force_3_0) |
+ SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(params->cfg_dfe_pd),
+ SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 |
+ SD25G_LANE_LANE_1C_LN_CFG_DFE_PD,
+ priv,
+ SD25G_LANE_LANE_1C(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET
+ (params->cfg_sum_setcm_en),
+ SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN,
+ priv,
+ SD25G_LANE_LANE_1E(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET
+ (params->cfg_init_pos_iscan_6_0),
+ SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0,
+ priv,
+ SD25G_LANE_LANE_25(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET
+ (params->cfg_init_pos_ipi_6_0),
+ SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0,
+ priv,
+ SD25G_LANE_LANE_26(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd),
+ SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD,
+ priv,
+ SD25G_LANE_LANE_18(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET
+ (params->cfg_dfedig_m_2_0),
+ SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0,
+ priv,
+ SD25G_LANE_LANE_0E(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig),
+ SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG,
+ priv,
+ SD25G_LANE_LANE_0E(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) |
+ SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(params->r_rx_pol_inv),
+ SD25G_LANE_LANE_40_LN_R_TX_POL_INV |
+ SD25G_LANE_LANE_40_LN_R_RX_POL_INV,
+ priv,
+ SD25G_LANE_LANE_40(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) |
+ SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(params->cfg_tx2rx_lp_en),
+ SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN |
+ SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN,
+ priv,
+ SD25G_LANE_LANE_04(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en),
+ SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN,
+ priv,
+ SD25G_LANE_LANE_1E(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en),
+ SD25G_LANE_LANE_19_LN_CFG_TXLB_EN,
+ priv,
+ SD25G_LANE_LANE_19(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(0),
+ SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG,
+ priv,
+ SD25G_LANE_LANE_2E(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(1),
+ SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG,
+ priv,
+ SD25G_LANE_LANE_2E(sd_index));
+
+ sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(0),
+ SD_LANE_25G_SD_LANE_CFG_MACRO_RST,
+ priv,
+ SD_LANE_25G_SD_LANE_CFG(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(0),
+ SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN,
+ priv,
+ SD25G_LANE_LANE_1C(sd_index));
+
+ udelay(2000);
+
+ sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(1),
+ SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN,
+ priv,
+ SD25G_LANE_LANE_1C(sd_index));
+
+ udelay(20000);
+
+ sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff),
+ SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
+ priv,
+ SD25G_LANE_CMU_FF(sd_index));
+
+ value = readl(sdx5_addr(regs, SD25G_LANE_CMU_C0(sd_index)));
+ value = SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(value);
+
+ if (value) {
+ dev_err(dev, "25G PLL Loss of Lock: 0x%x\n", value);
+ return -EINVAL;
+ }
+
+ value = readl(sdx5_addr(regs, SD_LANE_25G_SD_LANE_STAT(sd_index)));
+ value = SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(value);
+
+ if (value != 0x1) {
+ dev_err(dev, "25G PMA Reset failed: 0x%x\n", value);
+ return -EINVAL;
+ }
+ sdx5_rmw(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(0x1),
+ SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS,
+ priv,
+ SD25G_LANE_CMU_2A(sd_index));
+
+ sdx5_rmw(SD_LANE_25G_SD_SER_RST_SER_RST_SET(0x0),
+ SD_LANE_25G_SD_SER_RST_SER_RST,
+ priv,
+ SD_LANE_25G_SD_SER_RST(sd_index));
+
+ sdx5_rmw(SD_LANE_25G_SD_DES_RST_DES_RST_SET(0x0),
+ SD_LANE_25G_SD_DES_RST_DES_RST,
+ priv,
+ SD_LANE_25G_SD_DES_RST(sd_index));
+
+ sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0),
+ SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
+ priv,
+ SD25G_LANE_CMU_FF(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET
+ (params->cfg_alos_thr_2_0),
+ SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0,
+ priv,
+ SD25G_LANE_LANE_2D(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(0),
+ SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ,
+ priv,
+ SD25G_LANE_LANE_2E(sd_index));
+
+ sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(0),
+ SD25G_LANE_LANE_2E_LN_CFG_PD_SQ,
+ priv,
+ SD25G_LANE_LANE_2E(sd_index));
+
+ return 0;
+}
+
+static void sparx5_sd10g28_reset(void __iomem *regs[], u32 lane_index)
+{
+ /* Note: SerDes SD10G_LANE_1 is configured in 10G_LAN mode */
+ sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(1),
+ SD_LANE_SD_LANE_CFG_EXT_CFG_RST,
+ sdx5_addr(regs, SD_LANE_SD_LANE_CFG(lane_index)));
+
+ udelay(2000);
+
+ sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0),
+ SD_LANE_SD_LANE_CFG_EXT_CFG_RST,
+ sdx5_addr(regs, SD_LANE_SD_LANE_CFG(lane_index)));
+}
+
+static int sparx5_sd10g28_apply_params(struct sparx5_serdes_macro *macro,
+ struct sparx5_sd10g28_params *params)
+{
+ struct sparx5_serdes_private *priv = macro->priv;
+ void __iomem **regs = priv->regs;
+ struct udevice *dev = priv->dev;
+ u32 lane_index = macro->sidx;
+ u32 sd_index = macro->stpidx;
+ void __iomem *sd_inst;
+ u32 value, cmu_idx;
+ int err;
+
+ cmu_idx = priv->data->ops.serdes_cmu_get(params->cmu_sel, macro->sidx);
+ err = sparx5_cmu_cfg(priv, cmu_idx);
+ if (err)
+ return err;
+
+ if (params->is_6g)
+ sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, sd_index);
+ else
+ sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, sd_index);
+
+ sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(1),
+ SD_LANE_SD_LANE_CFG_MACRO_RST,
+ priv,
+ SD_LANE_SD_LANE_CFG(lane_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(0x0) |
+ SD10G_LANE_LANE_93_R_REG_MANUAL_SET(0x1) |
+ SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(0x1) |
+ SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(0x1) |
+ SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(0x0),
+ SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT |
+ SD10G_LANE_LANE_93_R_REG_MANUAL |
+ SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT |
+ SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT |
+ SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL,
+ sd_inst,
+ SD10G_LANE_LANE_93(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_94_R_ISCAN_REG_SET(0x1) |
+ SD10G_LANE_LANE_94_R_TXEQ_REG_SET(0x1) |
+ SD10G_LANE_LANE_94_R_MISC_REG_SET(0x1) |
+ SD10G_LANE_LANE_94_R_SWING_REG_SET(0x1),
+ SD10G_LANE_LANE_94_R_ISCAN_REG |
+ SD10G_LANE_LANE_94_R_TXEQ_REG |
+ SD10G_LANE_LANE_94_R_MISC_REG |
+ SD10G_LANE_LANE_94_R_SWING_REG,
+ sd_inst,
+ SD10G_LANE_LANE_94(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(0x1),
+ SD10G_LANE_LANE_9E_R_RXEQ_REG,
+ sd_inst,
+ SD10G_LANE_LANE_9E(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(0x0) |
+ SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(0x0) |
+ SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(0x1),
+ SD10G_LANE_LANE_A1_R_SSC_FROM_HWT |
+ SD10G_LANE_LANE_A1_R_CDR_FROM_HWT |
+ SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT,
+ sd_inst,
+ SD10G_LANE_LANE_A1(sd_index));
+
+ sdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) |
+ SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(params->cmu_sel),
+ SD_LANE_SD_LANE_CFG_RX_REF_SEL |
+ SD_LANE_SD_LANE_CFG_TX_REF_SEL,
+ priv,
+ SD_LANE_SD_LANE_CFG(lane_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET
+ (params->cfg_lane_reserve_7_0),
+ SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0,
+ sd_inst,
+ SD10G_LANE_LANE_40(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET
+ (params->cfg_ssc_rtl_clk_sel),
+ SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL,
+ sd_inst,
+ SD10G_LANE_LANE_50(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET
+ (params->cfg_txrate_1_0) |
+ SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET
+ (params->cfg_rxrate_1_0),
+ SD10G_LANE_LANE_35_CFG_TXRATE_1_0 |
+ SD10G_LANE_LANE_35_CFG_RXRATE_1_0,
+ sd_inst,
+ SD10G_LANE_LANE_35(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET
+ (params->r_d_width_ctrl_2_0),
+ SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0,
+ sd_inst,
+ SD10G_LANE_LANE_94(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET
+ (params->cfg_pma_tx_ck_bitwidth_2_0),
+ SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0,
+ sd_inst,
+ SD10G_LANE_LANE_01(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET
+ (params->cfg_rxdiv_sel_2_0),
+ SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0,
+ sd_inst,
+ SD10G_LANE_LANE_30(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET
+ (params->r_pcs2pma_phymode_4_0),
+ SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0,
+ sd_inst,
+ SD10G_LANE_LANE_A2(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),
+ SD10G_LANE_LANE_13_CFG_CDRCK_EN,
+ sd_inst,
+ SD10G_LANE_LANE_13(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_DFECK_EN_SET
+ (params->cfg_dfeck_en) |
+ SD10G_LANE_LANE_23_CFG_DFE_PD_SET(params->cfg_dfe_pd) |
+ SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET
+ (params->cfg_erramp_pd),
+ SD10G_LANE_LANE_23_CFG_DFECK_EN |
+ SD10G_LANE_LANE_23_CFG_DFE_PD |
+ SD10G_LANE_LANE_23_CFG_ERRAMP_PD,
+ sd_inst,
+ SD10G_LANE_LANE_23(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET
+ (params->cfg_dfetap_en_5_1),
+ SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1,
+ sd_inst,
+ SD10G_LANE_LANE_22(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET
+ (params->cfg_pi_DFE_en),
+ SD10G_LANE_LANE_1A_CFG_PI_DFE_EN,
+ sd_inst,
+ SD10G_LANE_LANE_1A(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) |
+ SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(params->cfg_en_main) |
+ SD10G_LANE_LANE_02_CFG_EN_DLY_SET(params->cfg_en_dly) |
+ SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET
+ (params->cfg_tap_adv_3_0),
+ SD10G_LANE_LANE_02_CFG_EN_ADV |
+ SD10G_LANE_LANE_02_CFG_EN_MAIN |
+ SD10G_LANE_LANE_02_CFG_EN_DLY |
+ SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0,
+ sd_inst,
+ SD10G_LANE_LANE_02(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main),
+ SD10G_LANE_LANE_03_CFG_TAP_MAIN,
+ sd_inst,
+ SD10G_LANE_LANE_03(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET
+ (params->cfg_tap_dly_4_0),
+ SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0,
+ sd_inst,
+ SD10G_LANE_LANE_04(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET
+ (params->cfg_vga_ctrl_3_0),
+ SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0,
+ sd_inst,
+ SD10G_LANE_LANE_2F(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET
+ (params->cfg_vga_cp_2_0),
+ SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0,
+ sd_inst,
+ SD10G_LANE_LANE_2F(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET
+ (params->cfg_eq_res_3_0),
+ SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0,
+ sd_inst,
+ SD10G_LANE_LANE_0B(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp),
+ SD10G_LANE_LANE_0D_CFG_EQR_BYP,
+ sd_inst,
+ SD10G_LANE_LANE_0D(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET
+ (params->cfg_eq_c_force_3_0) |
+ SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET
+ (params->cfg_sum_setcm_en),
+ SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 |
+ SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN,
+ sd_inst,
+ SD10G_LANE_LANE_0E(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET
+ (params->cfg_en_dfedig),
+ SD10G_LANE_LANE_23_CFG_EN_DFEDIG,
+ sd_inst,
+ SD10G_LANE_LANE_23(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET
+ (params->cfg_en_preemph),
+ SD10G_LANE_LANE_06_CFG_EN_PREEMPH,
+ sd_inst,
+ SD10G_LANE_LANE_06(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET
+ (params->cfg_itx_ippreemp_base_1_0) |
+ SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET
+ (params->cfg_itx_ipdriver_base_2_0),
+ SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 |
+ SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0,
+ sd_inst,
+ SD10G_LANE_LANE_33(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET
+ (params->cfg_ibias_tune_reserve_5_0),
+ SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0,
+ sd_inst,
+ SD10G_LANE_LANE_52(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET
+ (params->cfg_txswing_half),
+ SD10G_LANE_LANE_37_CFG_TXSWING_HALF,
+ sd_inst,
+ SD10G_LANE_LANE_37(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET
+ (params->cfg_dis_2nd_order),
+ SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER,
+ sd_inst,
+ SD10G_LANE_LANE_3C(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET
+ (params->cfg_rx_ssc_lh),
+ SD10G_LANE_LANE_39_CFG_RX_SSC_LH,
+ sd_inst,
+ SD10G_LANE_LANE_39(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET
+ (params->cfg_pi_floop_steps_1_0),
+ SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0,
+ sd_inst,
+ SD10G_LANE_LANE_1A(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET
+ (params->cfg_pi_ext_dac_23_16),
+ SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16,
+ sd_inst,
+ SD10G_LANE_LANE_16(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET
+ (params->cfg_pi_ext_dac_15_8),
+ SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8,
+ sd_inst,
+ SD10G_LANE_LANE_15(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET
+ (params->cfg_iscan_ext_dac_7_0),
+ SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0,
+ sd_inst,
+ SD10G_LANE_LANE_26(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET
+ (params->cfg_cdr_kf_gen1_2_0),
+ SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0,
+ sd_inst,
+ SD10G_LANE_LANE_42(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET
+ (params->r_cdr_m_gen1_7_0),
+ SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0,
+ sd_inst,
+ SD10G_LANE_LANE_0F(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET
+ (params->cfg_pi_bw_gen1_3_0),
+ SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0,
+ sd_inst,
+ SD10G_LANE_LANE_24(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET
+ (params->cfg_pi_ext_dac_7_0),
+ SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0,
+ sd_inst,
+ SD10G_LANE_LANE_14(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps),
+ SD10G_LANE_LANE_1A_CFG_PI_STEPS,
+ sd_inst,
+ SD10G_LANE_LANE_1A(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET
+ (params->cfg_mp_max_3_0),
+ SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0,
+ sd_inst,
+ SD10G_LANE_LANE_3A(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET
+ (params->cfg_rstn_dfedig),
+ SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG,
+ sd_inst,
+ SD10G_LANE_LANE_31(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET
+ (params->cfg_alos_thr_3_0),
+ SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0,
+ sd_inst,
+ SD10G_LANE_LANE_48(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET
+ (params->cfg_predrv_slewrate_1_0),
+ SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0,
+ sd_inst,
+ SD10G_LANE_LANE_36(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET
+ (params->cfg_itx_ipcml_base_1_0),
+ SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0,
+ sd_inst,
+ SD10G_LANE_LANE_32(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET
+ (params->cfg_ip_pre_base_1_0),
+ SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0,
+ sd_inst,
+ SD10G_LANE_LANE_37(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET
+ (params->cfg_lane_reserve_15_8),
+ SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8,
+ sd_inst,
+ SD10G_LANE_LANE_41(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET
+ (params->r_en_auto_cdr_rstn),
+ SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN,
+ sd_inst,
+ SD10G_LANE_LANE_9E(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET
+ (params->cfg_oscal_afe) |
+ SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET
+ (params->cfg_pd_osdac_afe),
+ SD10G_LANE_LANE_0C_CFG_OSCAL_AFE |
+ SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE,
+ sd_inst,
+ SD10G_LANE_LANE_0C(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET
+ (params->cfg_resetb_oscal_afe[0]),
+ SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE,
+ sd_inst,
+ SD10G_LANE_LANE_0B(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET
+ (params->cfg_resetb_oscal_afe[1]),
+ SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE,
+ sd_inst,
+ SD10G_LANE_LANE_0B(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_83_R_TX_POL_INV_SET
+ (params->r_tx_pol_inv) |
+ SD10G_LANE_LANE_83_R_RX_POL_INV_SET
+ (params->r_rx_pol_inv),
+ SD10G_LANE_LANE_83_R_TX_POL_INV |
+ SD10G_LANE_LANE_83_R_RX_POL_INV,
+ sd_inst,
+ SD10G_LANE_LANE_83(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET
+ (params->cfg_rx2tx_lp_en) |
+ SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET
+ (params->cfg_tx2rx_lp_en),
+ SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN |
+ SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN,
+ sd_inst,
+ SD10G_LANE_LANE_06(sd_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) |
+ SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(params->cfg_txlb_en),
+ SD10G_LANE_LANE_0E_CFG_RXLB_EN |
+ SD10G_LANE_LANE_0E_CFG_TXLB_EN,
+ sd_inst,
+ SD10G_LANE_LANE_0E(sd_index));
+
+ sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(0),
+ SD_LANE_SD_LANE_CFG_MACRO_RST,
+ priv,
+ SD_LANE_SD_LANE_CFG(lane_index));
+
+ sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1),
+ SD10G_LANE_LANE_50_CFG_SSC_RESETB,
+ sd_inst,
+ SD10G_LANE_LANE_50(sd_index));
+
+ sdx5_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1),
+ SD10G_LANE_LANE_50_CFG_SSC_RESETB,
+ priv,
+ SD10G_LANE_LANE_50(sd_index));
+
+ sdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100),
+ SD_LANE_MISC_SD_125_RST_DIS,
+ priv,
+ SD_LANE_MISC(lane_index));
+
+ sdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100),
+ SD_LANE_MISC_RX_ENA,
+ priv,
+ SD_LANE_MISC(lane_index));
+
+ sdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100),
+ SD_LANE_MISC_MUX_ENA,
+ priv,
+ SD_LANE_MISC(lane_index));
+
+ udelay(6000);
+
+ value = readl(sdx5_addr(regs, SD_LANE_SD_LANE_STAT(lane_index)));
+ value = SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(value);
+ if (value != 1) {
+ dev_err(dev, "10G PMA Reset failed: 0x%x\n", value);
+ return -EINVAL;
+ }
+
+ sdx5_rmw(SD_LANE_SD_SER_RST_SER_RST_SET(0x0),
+ SD_LANE_SD_SER_RST_SER_RST,
+ priv,
+ SD_LANE_SD_SER_RST(lane_index));
+
+ sdx5_rmw(SD_LANE_SD_DES_RST_DES_RST_SET(0x0),
+ SD_LANE_SD_DES_RST_DES_RST,
+ priv,
+ SD_LANE_SD_DES_RST(lane_index));
+
+ return 0;
+}
+
+static int sparx5_sd25g28_config(struct sparx5_serdes_macro *macro, bool reset)
+{
+ struct sparx5_sd25g28_media_preset media = media_presets_25g[macro->media];
+ struct sparx5_sd25g28_mode_preset mode;
+ struct sparx5_sd25g28_args args = {
+ .rxinvert = 1,
+ .txinvert = 0,
+ .txswing = 240,
+ .com_pll_reserve = 0xf,
+ .reg_rst = reset,
+ };
+ struct sparx5_sd25g28_params params;
+ int err;
+
+ err = sparx5_sd10g25_get_mode_preset(macro, &mode);
+ if (err)
+ return err;
+ sparx5_sd25g28_get_params(macro, &media, &mode, &args, ¶ms);
+ sparx5_sd25g28_reset(macro->priv->regs, ¶ms, macro->stpidx);
+ return sparx5_sd25g28_apply_params(macro, ¶ms);
+}
+
+static int sparx5_sd10g28_config(struct sparx5_serdes_macro *macro, bool reset)
+{
+ struct sparx5_sd10g28_media_preset media = media_presets_10g[macro->media];
+ struct sparx5_sd10g28_mode_preset mode;
+ struct sparx5_sd10g28_params params;
+ struct sparx5_sd10g28_args args = {
+ .is_6g = (macro->serdestype == SPX5_SDT_6G),
+ .txinvert = 0,
+ .rxinvert = 1,
+ .txswing = 240,
+ .reg_rst = reset,
+ };
+ int err;
+
+ err = sparx5_sd10g28_get_mode_preset(macro, &mode, &args);
+ if (err)
+ return err;
+ sparx5_sd10g28_get_params(macro, &media, &mode, &args, ¶ms);
+ sparx5_sd10g28_reset(macro->priv->regs, macro->sidx);
+ return sparx5_sd10g28_apply_params(macro, ¶ms);
+}
+
+/* Power down serdes TX driver */
+static int sparx5_serdes_power_save(struct sparx5_serdes_macro *macro, u32 pwdn)
+{
+ struct sparx5_serdes_private *priv = macro->priv;
+ void __iomem *sd_lane_inst;
+
+ if (macro->serdestype == SPX5_SDT_6G ||
+ macro->serdestype == SPX5_SDT_10G)
+ sd_lane_inst = sdx5_inst_get(priv, TARGET_SD_LANE,
+ macro->sidx);
+ else
+ sd_lane_inst = sdx5_inst_get(priv, TARGET_SD_LANE_25G,
+ macro->stpidx);
+
+ if (macro->serdestype == SPX5_SDT_25G) { /* 25G */
+ /* Take serdes out of reset */
+ sdx5_inst_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0),
+ SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,
+ sd_lane_inst, SD_LANE_25G_SD_LANE_CFG(0));
+
+ /* Set power down settings for quiet mode */
+ sdx5_inst_rmw(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(SPX5_SERDES_QUIET_MODE_VAL),
+ SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE,
+ sd_lane_inst, SD_LANE_25G_QUIET_MODE_6G(0));
+ } else { /* 6G and 10G */
+ /* Take serdes out of reset */
+ sdx5_inst_rmw(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0),
+ SD_LANE_SD_LANE_CFG_EXT_CFG_RST,
+ sd_lane_inst, SD_LANE_SD_LANE_CFG(0));
+
+ /* Set power down settings for quiet mode */
+ sdx5_inst_rmw(SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(SPX5_SERDES_QUIET_MODE_VAL),
+ SD_LANE_QUIET_MODE_6G_QUIET_MODE,
+ sd_lane_inst, SD_LANE_QUIET_MODE_6G(0));
+ }
+ return 0;
+}
+
+static int sparx5_serdes_clock_config(struct sparx5_serdes_macro *macro)
+{
+ struct sparx5_serdes_private *priv = macro->priv;
+
+ /* Clock is auto-detected in 100Base-FX mode on lan969x */
+ if (priv->data->type == SPX5_TARGET_LAN969X)
+ return 0;
+
+ if (macro->serdesmode == SPX5_SD_MODE_100FX) {
+ u32 freq = priv->coreclock == 250000000 ? 2 :
+ priv->coreclock == 500000000 ? 1 : 0;
+
+ sdx5_rmw(SD_LANE_MISC_CORE_CLK_FREQ_SET(freq),
+ SD_LANE_MISC_CORE_CLK_FREQ,
+ priv,
+ SD_LANE_MISC(macro->sidx));
+ }
+ return 0;
+}
+
+static int sparx5_serdes_get_serdesmode(phy_interface_t portmode, int speed)
+{
+ switch (portmode) {
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ if (speed == SPEED_2500)
+ return SPX5_SD_MODE_2G5;
+ if (speed == SPEED_100)
+ return SPX5_SD_MODE_100FX;
+ return SPX5_SD_MODE_1000BASEX;
+ case PHY_INTERFACE_MODE_SGMII:
+ /* The same Serdes mode is used for both SGMII and 1000BaseX */
+ return SPX5_SD_MODE_1000BASEX;
+ case PHY_INTERFACE_MODE_QSGMII:
+ return SPX5_SD_MODE_QSGMII;
+ case PHY_INTERFACE_MODE_10GBASER:
+ return SPX5_SD_MODE_SFI;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int sparx5_serdes_config(struct sparx5_serdes_macro *macro)
+{
+ struct udevice *dev = macro->priv->dev;
+ int serdesmode;
+ int err;
+
+ serdesmode = sparx5_serdes_get_serdesmode(macro->portmode, macro->speed);
+ if (serdesmode < 0) {
+ dev_err(dev, "SerDes %u, interface not supported: %s\n",
+ macro->sidx,
+ phy_modes(macro->portmode));
+ return serdesmode;
+ }
+ macro->serdesmode = serdesmode;
+
+ sparx5_serdes_clock_config(macro);
+
+ if (macro->serdestype == SPX5_SDT_25G)
+ err = sparx5_sd25g28_config(macro, false);
+ else
+ err = sparx5_sd10g28_config(macro, false);
+ if (err) {
+ dev_err(dev, "SerDes %u, config error: %d\n",
+ macro->sidx, err);
+ }
+ return err;
+}
+
+static int sparx5_serdes_power_off(struct sparx5_serdes_phy *phy)
+{
+ struct sparx5_serdes_macro *macro = phy->data;
+
+ return sparx5_serdes_power_save(macro, true);
+}
+
+static int sparx5_serdes_set_mode(struct sparx5_serdes_phy *phy, int submode)
+{
+ struct sparx5_serdes_macro *macro;
+
+ switch (submode) {
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ macro = phy->data;
+ macro->portmode = submode;
+ sparx5_serdes_config(macro);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+int sparx5_serdes_reset(struct sparx5_serdes_phy *phy)
+{
+ struct sparx5_serdes_macro *macro = phy->data;
+ int err;
+
+ if (macro->serdestype == SPX5_SDT_25G)
+ err = sparx5_sd25g28_config(macro, true);
+ else
+ err = sparx5_sd10g28_config(macro, true);
+ if (err) {
+ dev_err(phy->dev, "SerDes %u, reset error: %d\n",
+ macro->sidx, err);
+ }
+ return err;
+}
+
+static void sparx5_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx)
+{
+ if (sidx < SPX5_SERDES_10G_START) {
+ macro->serdestype = SPX5_SDT_6G;
+ macro->stpidx = macro->sidx;
+ } else if (sidx < SPX5_SERDES_25G_START) {
+ macro->serdestype = SPX5_SDT_10G;
+ macro->stpidx = macro->sidx - SPX5_SERDES_10G_START;
+ } else {
+ macro->serdestype = SPX5_SDT_25G;
+ macro->stpidx = macro->sidx - SPX5_SERDES_25G_START;
+ }
+}
+
+static void lan969x_set_serdes_type(struct sparx5_serdes_macro *macro, int sidx)
+{
+ macro->serdestype = SPX5_SDT_10G;
+ macro->stpidx = macro->sidx;
+}
+
+static int sparx5_phy_create(struct sparx5_serdes_private *priv,
+ int idx, struct sparx5_serdes_phy **phy)
+{
+ struct sparx5_serdes_macro *macro;
+
+ *phy = devm_kzalloc(priv->dev, sizeof(struct sparx5_serdes_phy),
+ GFP_KERNEL);
+ if (!*phy)
+ return -ENOMEM;
+
+ macro = devm_kzalloc(priv->dev, sizeof(*macro), GFP_KERNEL);
+ if (!macro)
+ return -ENOMEM;
+
+ macro->sidx = idx;
+ macro->priv = priv;
+ macro->speed = -1;
+
+ priv->data->ops.serdes_type_set(macro, idx);
+
+ (*phy)->ops = priv->data->ops;
+ (*phy)->data = macro;
+ (*phy)->dev = priv->dev;
+
+ /* Power down serdes by default */
+ sparx5_serdes_power_off(*phy);
+
+ return 0;
+}
+
+static struct sparx5_serdes_io_resource sparx5_serdes_iomap[] = {
+ { TARGET_SD_CMU, 0x0 }, /* 0x610808000: sd_cmu_0 */
+ { TARGET_SD_CMU + 1, 0x8000 }, /* 0x610810000: sd_cmu_1 */
+ { TARGET_SD_CMU + 2, 0x10000 }, /* 0x610818000: sd_cmu_2 */
+ { TARGET_SD_CMU + 3, 0x18000 }, /* 0x610820000: sd_cmu_3 */
+ { TARGET_SD_CMU + 4, 0x20000 }, /* 0x610828000: sd_cmu_4 */
+ { TARGET_SD_CMU + 5, 0x28000 }, /* 0x610830000: sd_cmu_5 */
+ { TARGET_SD_CMU + 6, 0x30000 }, /* 0x610838000: sd_cmu_6 */
+ { TARGET_SD_CMU + 7, 0x38000 }, /* 0x610840000: sd_cmu_7 */
+ { TARGET_SD_CMU + 8, 0x40000 }, /* 0x610848000: sd_cmu_8 */
+ { TARGET_SD_CMU_CFG, 0x48000 }, /* 0x610850000: sd_cmu_cfg_0 */
+ { TARGET_SD_CMU_CFG + 1, 0x50000 }, /* 0x610858000: sd_cmu_cfg_1 */
+ { TARGET_SD_CMU_CFG + 2, 0x58000 }, /* 0x610860000: sd_cmu_cfg_2 */
+ { TARGET_SD_CMU_CFG + 3, 0x60000 }, /* 0x610868000: sd_cmu_cfg_3 */
+ { TARGET_SD_CMU_CFG + 4, 0x68000 }, /* 0x610870000: sd_cmu_cfg_4 */
+ { TARGET_SD_CMU_CFG + 5, 0x70000 }, /* 0x610878000: sd_cmu_cfg_5 */
+ { TARGET_SD_CMU_CFG + 6, 0x78000 }, /* 0x610880000: sd_cmu_cfg_6 */
+ { TARGET_SD_CMU_CFG + 7, 0x80000 }, /* 0x610888000: sd_cmu_cfg_7 */
+ { TARGET_SD_CMU_CFG + 8, 0x88000 }, /* 0x610890000: sd_cmu_cfg_8 */
+ { TARGET_SD6G_LANE, 0x90000 }, /* 0x610898000: sd6g_lane_0 */
+ { TARGET_SD6G_LANE + 1, 0x98000 }, /* 0x6108a0000: sd6g_lane_1 */
+ { TARGET_SD6G_LANE + 2, 0xa0000 }, /* 0x6108a8000: sd6g_lane_2 */
+ { TARGET_SD6G_LANE + 3, 0xa8000 }, /* 0x6108b0000: sd6g_lane_3 */
+ { TARGET_SD6G_LANE + 4, 0xb0000 }, /* 0x6108b8000: sd6g_lane_4 */
+ { TARGET_SD6G_LANE + 5, 0xb8000 }, /* 0x6108c0000: sd6g_lane_5 */
+ { TARGET_SD6G_LANE + 6, 0xc0000 }, /* 0x6108c8000: sd6g_lane_6 */
+ { TARGET_SD6G_LANE + 7, 0xc8000 }, /* 0x6108d0000: sd6g_lane_7 */
+ { TARGET_SD6G_LANE + 8, 0xd0000 }, /* 0x6108d8000: sd6g_lane_8 */
+ { TARGET_SD6G_LANE + 9, 0xd8000 }, /* 0x6108e0000: sd6g_lane_9 */
+ { TARGET_SD6G_LANE + 10, 0xe0000 }, /* 0x6108e8000: sd6g_lane_10 */
+ { TARGET_SD6G_LANE + 11, 0xe8000 }, /* 0x6108f0000: sd6g_lane_11 */
+ { TARGET_SD6G_LANE + 12, 0xf0000 }, /* 0x6108f8000: sd6g_lane_12 */
+ { TARGET_SD10G_LANE, 0xf8000 }, /* 0x610900000: sd10g_lane_0 */
+ { TARGET_SD10G_LANE + 1, 0x100000 }, /* 0x610908000: sd10g_lane_1 */
+ { TARGET_SD10G_LANE + 2, 0x108000 }, /* 0x610910000: sd10g_lane_2 */
+ { TARGET_SD10G_LANE + 3, 0x110000 }, /* 0x610918000: sd10g_lane_3 */
+ { TARGET_SD_LANE, 0x1a0000 }, /* 0x6109a8000: sd_lane_0 */
+ { TARGET_SD_LANE + 1, 0x1a8000 }, /* 0x6109b0000: sd_lane_1 */
+ { TARGET_SD_LANE + 2, 0x1b0000 }, /* 0x6109b8000: sd_lane_2 */
+ { TARGET_SD_LANE + 3, 0x1b8000 }, /* 0x6109c0000: sd_lane_3 */
+ { TARGET_SD_LANE + 4, 0x1c0000 }, /* 0x6109c8000: sd_lane_4 */
+ { TARGET_SD_LANE + 5, 0x1c8000 }, /* 0x6109d0000: sd_lane_5 */
+ { TARGET_SD_LANE + 6, 0x1d0000 }, /* 0x6109d8000: sd_lane_6 */
+ { TARGET_SD_LANE + 7, 0x1d8000 }, /* 0x6109e0000: sd_lane_7 */
+ { TARGET_SD_LANE + 8, 0x1e0000 }, /* 0x6109e8000: sd_lane_8 */
+ { TARGET_SD_LANE + 9, 0x1e8000 }, /* 0x6109f0000: sd_lane_9 */
+ { TARGET_SD_LANE + 10, 0x1f0000 }, /* 0x6109f8000: sd_lane_10 */
+ { TARGET_SD_LANE + 11, 0x1f8000 }, /* 0x610a00000: sd_lane_11 */
+ { TARGET_SD_LANE + 12, 0x200000 }, /* 0x610a08000: sd_lane_12 */
+ { TARGET_SD_LANE + 13, 0x208000 }, /* 0x610a10000: sd_lane_13 */
+ { TARGET_SD_LANE + 14, 0x210000 }, /* 0x610a18000: sd_lane_14 */
+ { TARGET_SD_LANE + 15, 0x218000 }, /* 0x610a20000: sd_lane_15 */
+ { TARGET_SD_LANE + 16, 0x220000 }, /* 0x610a28000: sd_lane_16 */
+ { TARGET_SD_CMU + 9, 0x400000 }, /* 0x610c08000: sd_cmu_9 */
+ { TARGET_SD_CMU + 10, 0x408000 }, /* 0x610c10000: sd_cmu_10 */
+ { TARGET_SD_CMU + 11, 0x410000 }, /* 0x610c18000: sd_cmu_11 */
+ { TARGET_SD_CMU + 12, 0x418000 }, /* 0x610c20000: sd_cmu_12 */
+ { TARGET_SD_CMU + 13, 0x420000 }, /* 0x610c28000: sd_cmu_13 */
+ { TARGET_SD_CMU_CFG + 9, 0x428000 }, /* 0x610c30000: sd_cmu_cfg_9 */
+ { TARGET_SD_CMU_CFG + 10, 0x430000 }, /* 0x610c38000: sd_cmu_cfg_10 */
+ { TARGET_SD_CMU_CFG + 11, 0x438000 }, /* 0x610c40000: sd_cmu_cfg_11 */
+ { TARGET_SD_CMU_CFG + 12, 0x440000 }, /* 0x610c48000: sd_cmu_cfg_12 */
+ { TARGET_SD_CMU_CFG + 13, 0x448000 }, /* 0x610c50000: sd_cmu_cfg_13 */
+ { TARGET_SD10G_LANE + 4, 0x450000 }, /* 0x610c58000: sd10g_lane_4 */
+ { TARGET_SD10G_LANE + 5, 0x458000 }, /* 0x610c60000: sd10g_lane_5 */
+ { TARGET_SD10G_LANE + 6, 0x460000 }, /* 0x610c68000: sd10g_lane_6 */
+ { TARGET_SD10G_LANE + 7, 0x468000 }, /* 0x610c70000: sd10g_lane_7 */
+ { TARGET_SD10G_LANE + 8, 0x470000 }, /* 0x610c78000: sd10g_lane_8 */
+ { TARGET_SD10G_LANE + 9, 0x478000 }, /* 0x610c80000: sd10g_lane_9 */
+ { TARGET_SD10G_LANE + 10, 0x480000 }, /* 0x610c88000: sd10g_lane_10 */
+ { TARGET_SD10G_LANE + 11, 0x488000 }, /* 0x610c90000: sd10g_lane_11 */
+ { TARGET_SD25G_LANE, 0x490000 }, /* 0x610c98000: sd25g_lane_0 */
+ { TARGET_SD25G_LANE + 1, 0x498000 }, /* 0x610ca0000: sd25g_lane_1 */
+ { TARGET_SD25G_LANE + 2, 0x4a0000 }, /* 0x610ca8000: sd25g_lane_2 */
+ { TARGET_SD25G_LANE + 3, 0x4a8000 }, /* 0x610cb0000: sd25g_lane_3 */
+ { TARGET_SD25G_LANE + 4, 0x4b0000 }, /* 0x610cb8000: sd25g_lane_4 */
+ { TARGET_SD25G_LANE + 5, 0x4b8000 }, /* 0x610cc0000: sd25g_lane_5 */
+ { TARGET_SD25G_LANE + 6, 0x4c0000 }, /* 0x610cc8000: sd25g_lane_6 */
+ { TARGET_SD25G_LANE + 7, 0x4c8000 }, /* 0x610cd0000: sd25g_lane_7 */
+ { TARGET_SD_LANE + 17, 0x550000 }, /* 0x610d58000: sd_lane_17 */
+ { TARGET_SD_LANE + 18, 0x558000 }, /* 0x610d60000: sd_lane_18 */
+ { TARGET_SD_LANE + 19, 0x560000 }, /* 0x610d68000: sd_lane_19 */
+ { TARGET_SD_LANE + 20, 0x568000 }, /* 0x610d70000: sd_lane_20 */
+ { TARGET_SD_LANE + 21, 0x570000 }, /* 0x610d78000: sd_lane_21 */
+ { TARGET_SD_LANE + 22, 0x578000 }, /* 0x610d80000: sd_lane_22 */
+ { TARGET_SD_LANE + 23, 0x580000 }, /* 0x610d88000: sd_lane_23 */
+ { TARGET_SD_LANE + 24, 0x588000 }, /* 0x610d90000: sd_lane_24 */
+ { TARGET_SD_LANE_25G, 0x590000 }, /* 0x610d98000: sd_lane_25g_25 */
+ { TARGET_SD_LANE_25G + 1, 0x598000 }, /* 0x610da0000: sd_lane_25g_26 */
+ { TARGET_SD_LANE_25G + 2, 0x5a0000 }, /* 0x610da8000: sd_lane_25g_27 */
+ { TARGET_SD_LANE_25G + 3, 0x5a8000 }, /* 0x610db0000: sd_lane_25g_28 */
+ { TARGET_SD_LANE_25G + 4, 0x5b0000 }, /* 0x610db8000: sd_lane_25g_29 */
+ { TARGET_SD_LANE_25G + 5, 0x5b8000 }, /* 0x610dc0000: sd_lane_25g_30 */
+ { TARGET_SD_LANE_25G + 6, 0x5c0000 }, /* 0x610dc8000: sd_lane_25g_31 */
+ { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */
+};
+
+static const struct sparx5_serdes_io_resource lan969x_serdes_iomap[] = {
+ { TARGET_SD_CMU, 0x0 }, /* 0xe3410000 */
+ { TARGET_SD_CMU + 1, 0x8000 }, /* 0xe3418000 */
+ { TARGET_SD_CMU + 2, 0x10000 }, /* 0xe3420000 */
+ { TARGET_SD_CMU + 3, 0x18000 }, /* 0xe3428000 */
+ { TARGET_SD_CMU + 4, 0x20000 }, /* 0xe3430000 */
+ { TARGET_SD_CMU + 5, 0x28000 }, /* 0xe3438000 */
+ { TARGET_SD_CMU_CFG, 0x30000 }, /* 0xe3440000 */
+ { TARGET_SD_CMU_CFG + 1, 0x38000 }, /* 0xe3448000 */
+ { TARGET_SD_CMU_CFG + 2, 0x40000 }, /* 0xe3450000 */
+ { TARGET_SD_CMU_CFG + 3, 0x48000 }, /* 0xe3458000 */
+ { TARGET_SD_CMU_CFG + 4, 0x50000 }, /* 0xe3460000 */
+ { TARGET_SD_CMU_CFG + 5, 0x58000 }, /* 0xe3468000 */
+ { TARGET_SD10G_LANE, 0x60000 }, /* 0xe3470000 */
+ { TARGET_SD10G_LANE + 1, 0x68000 }, /* 0xe3478000 */
+ { TARGET_SD10G_LANE + 2, 0x70000 }, /* 0xe3480000 */
+ { TARGET_SD10G_LANE + 3, 0x78000 }, /* 0xe3488000 */
+ { TARGET_SD10G_LANE + 4, 0x80000 }, /* 0xe3490000 */
+ { TARGET_SD10G_LANE + 5, 0x88000 }, /* 0xe3498000 */
+ { TARGET_SD10G_LANE + 6, 0x90000 }, /* 0xe34a0000 */
+ { TARGET_SD10G_LANE + 7, 0x98000 }, /* 0xe34a8000 */
+ { TARGET_SD10G_LANE + 8, 0xa0000 }, /* 0xe34b0000 */
+ { TARGET_SD10G_LANE + 9, 0xa8000 }, /* 0xe34b8000 */
+ { TARGET_SD_LANE, 0x100000 }, /* 0xe3510000 */
+ { TARGET_SD_LANE + 1, 0x108000 }, /* 0xe3518000 */
+ { TARGET_SD_LANE + 2, 0x110000 }, /* 0xe3520000 */
+ { TARGET_SD_LANE + 3, 0x118000 }, /* 0xe3528000 */
+ { TARGET_SD_LANE + 4, 0x120000 }, /* 0xe3530000 */
+ { TARGET_SD_LANE + 5, 0x128000 }, /* 0xe3538000 */
+ { TARGET_SD_LANE + 6, 0x130000 }, /* 0xe3540000 */
+ { TARGET_SD_LANE + 7, 0x138000 }, /* 0xe3548000 */
+ { TARGET_SD_LANE + 8, 0x140000 }, /* 0xe3550000 */
+ { TARGET_SD_LANE + 9, 0x148000 }, /* 0xe3558000 */
+};
+
+static struct sparx5_serdes_match_data sparx5_desc = {
+ .type = SPX5_TARGET_SPARX5,
+ .iomap = sparx5_serdes_iomap,
+ .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap),
+ .tsize = sparx5_serdes_tsize,
+ .consts = {
+ .sd_max = 33,
+ .cmu_max = 14,
+ },
+ .ops = {
+ .serdes_type_set = &sparx5_serdes_type_set,
+ .serdes_cmu_get = &sparx5_serdes_cmu_get,
+ },
+};
+
+static struct sparx5_serdes_match_data lan969x_desc = {
+ .type = SPX5_TARGET_LAN969X,
+ .iomap = lan969x_serdes_iomap,
+ .iomap_size = ARRAY_SIZE(lan969x_serdes_iomap),
+ .tsize = lan969x_serdes_tsize,
+ .consts = {
+ .sd_max = 10,
+ .cmu_max = 6,
+ },
+ .ops = {
+ .serdes_type_set = &lan969x_set_serdes_type,
+ .serdes_cmu_get = &lan969x_serdes_cmu_get,
+ }
+};
+
+void *sparx5_serdes_probe(struct udevice *dev)
+{
+ struct sparx5_serdes_private *serdes;
+ struct mscc_match_data *data;
+ void __iomem *iomem;
+ unsigned long clock;
+ struct clk clk;
+ int idx;
+ int err;
+
+ serdes = devm_kzalloc(dev, sizeof(*serdes), GFP_KERNEL);
+ if (!serdes)
+ return ERR_PTR(-ENOMEM);
+
+ data = (struct mscc_match_data*)dev_get_driver_data(dev);
+ if (!data)
+ return ERR_PTR(-EINVAL);
+
+ if (data->target == SPARX5_TARGET)
+ serdes->data = &sparx5_desc;
+ if (data->target == LAN969X_TARGET)
+ serdes->data = &lan969x_desc;
+
+ serdes->dev = dev;
+ tsize = serdes->data->tsize;
+
+ /* Get coreclock */
+ err = clk_get_by_index(dev, 0, &clk);
+ if (err < 0) {
+ dev_err(serdes->dev, "Failed to get coreclock\n");
+ return ERR_PTR(err);
+ }
+
+ clock = clk_get_rate(&clk);
+ if (clock == 0) {
+ dev_err(serdes->dev, "Invalid coreclock %lu\n", clock);
+ return ERR_PTR(-EINVAL);
+ }
+ serdes->coreclock = clock;
+
+ iomem = dev_remap_addr_index(dev, data->num_regs);
+ if (!iomem) {
+ dev_err(serdes->dev, "Unable to get serdes registers");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ for (idx = 0; idx < serdes->data->iomap_size; idx++) {
+ const struct sparx5_serdes_io_resource *iomap =
+ &serdes->data->iomap[idx];
+
+ serdes->regs[iomap->id] = iomem + iomap->offset;
+ }
+
+ for (idx = 0; idx < serdes->data->consts.sd_max; idx++) {
+ err = sparx5_phy_create(serdes, idx, &serdes->phys[idx]);
+ if (err)
+ return ERR_PTR(err);
+ }
+
+ /* Power down all CMU's by default */
+ if (serdes->data->type == SPX5_TARGET_SPARX5)
+ sparx5_serdes_cmu_power_off(serdes);
+
+ return serdes;
+}
+
+struct sparx5_serdes_phy *sparx5_serdes_phy_get(void *data, u32 serdes_type, u32 serdes_idx)
+{
+ struct sparx5_serdes_private *serdes = data;
+
+ return serdes->phys[serdes_idx];
+}
+
+void sparx5_serdes_port_init(struct sparx5_serdes_phy *phy, u32 mac_type)
+{
+ switch (mac_type) {
+ case IF_SGMII:
+ case IF_SGMII_CISCO:
+ sparx5_serdes_set_mode(phy, PHY_INTERFACE_MODE_SGMII);
+ break;
+ case IF_QSGMII:
+ sparx5_serdes_set_mode(phy, PHY_INTERFACE_MODE_QSGMII);
+ break;
+ default:
+ break;
+ }
+}
diff --git a/drivers/net/mscc_eswitch/sparx5_serdes.h b/drivers/net/mscc_eswitch/sparx5_serdes.h
new file mode 100644
index 00000000000..5fd047f1b14
--- /dev/null
+++ b/drivers/net/mscc_eswitch/sparx5_serdes.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ * Microchip Sparx5 SerDes driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc.
+ */
+
+#ifndef _SPARX5_SERDES_H_
+#define _SPARX5_SERDES_H_
+
+enum phy_media {
+ PHY_MEDIA_DEFAULT,
+ PHY_MEDIA_SR,
+ PHY_MEDIA_DAC,
+};
+
+enum sparx5_serdes_type {
+ SPX5_SDT_6G = 6,
+ SPX5_SDT_10G = 10,
+ SPX5_SDT_25G = 25,
+};
+
+enum sparx5_serdes_mode {
+ SPX5_SD_MODE_NONE,
+ SPX5_SD_MODE_2G5,
+ SPX5_SD_MODE_QSGMII,
+ SPX5_SD_MODE_100FX,
+ SPX5_SD_MODE_1000BASEX,
+ SPX5_SD_MODE_SFI,
+};
+
+enum sparx5_10g28cmu_mode {
+ SPX5_SD10G28_CMU_MAIN = 0,
+ SPX5_SD10G28_CMU_AUX1 = 1,
+ SPX5_SD10G28_CMU_AUX2 = 3,
+ SPX5_SD10G28_CMU_NONE = 4,
+ SPX5_SD10G28_CMU_MAX,
+};
+
+struct sparx5_serdes_macro {
+ struct sparx5_serdes_private *priv;
+ u32 sidx;
+ u32 stpidx;
+ enum sparx5_serdes_type serdestype;
+ enum sparx5_serdes_mode serdesmode;
+ phy_interface_t portmode;
+ int speed;
+ enum phy_media media;
+};
+
+struct sparx5_serdes_ops {
+ void (*serdes_type_set)(struct sparx5_serdes_macro *macro, int sidx);
+ int (*serdes_cmu_get)(enum sparx5_10g28cmu_mode mode, int sd_index);
+};
+
+struct sparx5_serdes_phy {
+ void *data;
+ struct udevice *dev;
+ struct sparx5_serdes_ops ops;
+};
+
+// This is the old API just to be able to compile
+void sparx5_serdes_port_init(struct sparx5_serdes_phy *phy, u32 mac_type);
+
+// This is the new API, add more functions here
+void *sparx5_serdes_probe(struct udevice *dev);
+struct sparx5_serdes_phy *sparx5_serdes_phy_get(void *data, u32 serdes_type, u32 serdes_idx);
+int sparx5_serdes_reset(struct sparx5_serdes_phy *phy);
+
+#endif /* _SPARX5_SERDES_H_ */
diff --git a/drivers/net/mscc_eswitch/sparx5_serdes_priv.h b/drivers/net/mscc_eswitch/sparx5_serdes_priv.h
new file mode 100644
index 00000000000..65b67f190ee
--- /dev/null
+++ b/drivers/net/mscc_eswitch/sparx5_serdes_priv.h
@@ -0,0 +1,130 @@
+#ifndef _SPARX5_SERDES_PRIV_H_
+#define _SPARX5_SERDES_PRIV_H_
+
+#include <phy_interface.h>
+
+#include "sparx5_serdes_regs.h"
+
+#define SPX5_SERDES_MAX 33
+
+enum sparx5_target {
+ SPX5_TARGET_SPARX5,
+ SPX5_TARGET_LAN969X,
+};
+
+struct sparx5_serdes_io_resource {
+ enum sparx5_serdes_target id;
+ phys_addr_t offset;
+};
+
+struct sparx5_serdes_consts {
+ int sd_max;
+ int cmu_max;
+};
+
+struct sparx5_serdes_match_data {
+ enum sparx5_target type;
+ const struct sparx5_serdes_consts consts;
+ const struct sparx5_serdes_ops ops;
+ const struct sparx5_serdes_io_resource *iomap;
+ int iomap_size;
+ const unsigned int *tsize;
+};
+
+struct sparx5_serdes_private {
+ struct udevice *dev;
+ void __iomem *regs[NUM_TARGETS];
+ struct sparx5_serdes_phy *phys[SPX5_SERDES_MAX];
+ bool cmu_enabled;
+ unsigned long coreclock;
+ struct sparx5_serdes_match_data *data;
+};
+
+/* Read, Write and modify registers content.
+ * The register definition macros start at the id
+ */
+static inline void __iomem *sdx5_addr(void __iomem *base[],
+ int id, int tinst, int tcnt,
+ int gbase, int ginst,
+ int gcnt, int gwidth,
+ int raddr, int rinst,
+ int rcnt, int rwidth)
+{
+ WARN_ON((tinst) >= tcnt);
+ WARN_ON((ginst) >= gcnt);
+ WARN_ON((rinst) >= rcnt);
+ return base[id + (tinst)] +
+ gbase + ((ginst) * gwidth) +
+ raddr + ((rinst) * rwidth);
+}
+
+static inline void __iomem *sdx5_inst_baseaddr(void __iomem *base,
+ int gbase, int ginst,
+ int gcnt, int gwidth,
+ int raddr, int rinst,
+ int rcnt, int rwidth)
+{
+ WARN_ON((ginst) >= gcnt);
+ WARN_ON((rinst) >= rcnt);
+ return base +
+ gbase + ((ginst) * gwidth) +
+ raddr + ((rinst) * rwidth);
+}
+
+static inline void sdx5_rmw(u32 val, u32 mask, struct sparx5_serdes_private *priv,
+ int id, int tinst, int tcnt,
+ int gbase, int ginst, int gcnt, int gwidth,
+ int raddr, int rinst, int rcnt, int rwidth)
+{
+ u32 nval;
+ void __iomem *addr =
+ sdx5_addr(priv->regs, id, tinst, tcnt,
+ gbase, ginst, gcnt, gwidth,
+ raddr, rinst, rcnt, rwidth);
+ nval = readl(addr);
+ nval = (nval & ~mask) | (val & mask);
+ writel(nval, addr);
+}
+
+static inline void sdx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,
+ int id, int tinst, int tcnt,
+ int gbase, int ginst, int gcnt, int gwidth,
+ int raddr, int rinst, int rcnt, int rwidth)
+{
+ u32 nval;
+ void __iomem *addr =
+ sdx5_inst_baseaddr(iomem,
+ gbase, ginst, gcnt, gwidth,
+ raddr, rinst, rcnt, rwidth);
+ nval = readl(addr);
+ nval = (nval & ~mask) | (val & mask);
+ writel(nval, addr);
+}
+
+static inline void sdx5_rmw_addr(u32 val, u32 mask, void __iomem *addr)
+{
+ u32 nval;
+
+ nval = readl(addr);
+ nval = (nval & ~mask) | (val & mask);
+ writel(nval, addr);
+}
+
+static inline void __iomem *sdx5_inst_get(struct sparx5_serdes_private *priv,
+ int id, int tinst)
+{
+ return priv->regs[id + tinst];
+}
+
+static inline void __iomem *sdx5_inst_addr(void __iomem *iomem,
+ int id, int tinst, int tcnt,
+ int gbase,
+ int ginst, int gcnt, int gwidth,
+ int raddr,
+ int rinst, int rcnt, int rwidth)
+{
+ return sdx5_inst_baseaddr(iomem, gbase, ginst, gcnt, gwidth,
+ raddr, rinst, rcnt, rwidth);
+}
+
+#endif /* _SPARX5_SERDES_PRIV_H_ */
diff --git a/drivers/net/mscc_eswitch/sparx5_serdes_regs.h b/drivers/net/mscc_eswitch/sparx5_serdes_regs.h
new file mode 100644
index 00000000000..544f0386d5a
--- /dev/null
+++ b/drivers/net/mscc_eswitch/sparx5_serdes_regs.h
@@ -0,0 +1,3047 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ * Microchip Sparx5 SerDes driver
+ *
+ * Copyright (c) 2023 Microchip Technology Inc.
+ */
+
+/* This file is autogenerated by cml-utils 2023-04-13 15:02:00 +0200.
+ * Commit ID: 5ac560288d46048f872ecdb8add53717f1efc0e1 (dirty)
+ */
+
+#ifndef _SPARX5_MAIN_REGS_H_
+#define _SPARX5_MAIN_REGS_H_
+
+#include <linux/bitfield.h>
+#include <linux/types.h>
+#include <linux/bug.h>
+
+#include "sparx5_serdes.h"
+
+enum sparx5_serdes_target {
+ TARGET_SD10G_LANE = 200,
+ TARGET_SD25G_LANE = 212,
+ TARGET_SD6G_LANE = 233,
+ TARGET_SD_CMU = 248,
+ TARGET_SD_CMU_CFG = 262,
+ TARGET_SD_LANE = 276,
+ TARGET_SD_LANE_25G = 301,
+ NUM_TARGETS = 332
+};
+
+enum sparx5_serdes_tsize_enum {
+ TC_SD10G_LANE,
+ TC_SD_CMU,
+ TC_SD_CMU_CFG,
+ TC_SD_LANE,
+ TSIZE_LAST,
+};
+
+const unsigned int *tsize;
+
+#define TSIZE(o) tsize[o]
+
+#define __REG(...) __VA_ARGS__
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */
+#define SD10G_LANE_LANE_01(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 4, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)
+#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
+#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
+
+#define SD10G_LANE_LANE_01_CFG_RXDET_EN BIT(4)
+#define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
+#define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
+
+#define SD10G_LANE_LANE_01_CFG_RXDET_STR BIT(5)
+#define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
+#define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */
+#define SD10G_LANE_LANE_02(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 8, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_02_CFG_EN_ADV BIT(0)
+#define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
+#define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
+
+#define SD10G_LANE_LANE_02_CFG_EN_MAIN BIT(1)
+#define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
+#define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
+
+#define SD10G_LANE_LANE_02_CFG_EN_DLY BIT(2)
+#define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
+#define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
+
+#define SD10G_LANE_LANE_02_CFG_EN_DLY2 BIT(3)
+#define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
+#define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
+
+#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0 GENMASK(7, 4)
+#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
+#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */
+#define SD10G_LANE_LANE_03(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 12, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_03_CFG_TAP_MAIN BIT(0)
+#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
+#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */
+#define SD10G_LANE_LANE_04(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 16, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0 GENMASK(4, 0)
+#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
+#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */
+#define SD10G_LANE_LANE_06(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 24, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_06_CFG_PD_DRIVER BIT(0)
+#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
+#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
+
+#define SD10G_LANE_LANE_06_CFG_PD_CLK BIT(1)
+#define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
+#define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
+
+#define SD10G_LANE_LANE_06_CFG_PD_CML BIT(2)
+#define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CML, x)
+#define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CML, x)
+
+#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN BIT(3)
+#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
+#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
+
+#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN BIT(4)
+#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
+#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
+
+#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH BIT(5)
+#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
+#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */
+#define SD10G_LANE_LANE_0B(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 44, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0 GENMASK(3, 0)
+#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
+#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
+
+#define SD10G_LANE_LANE_0B_CFG_PD_CTLE BIT(4)
+#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
+#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
+
+#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN BIT(5)
+#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
+#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
+
+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE BIT(6)
+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
+
+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ BIT(7)
+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */
+#define SD10G_LANE_LANE_0C(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 48, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE BIT(0)
+#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
+#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
+
+#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ BIT(1)
+#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
+#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
+
+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE BIT(2)
+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
+
+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ BIT(3)
+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
+
+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE BIT(4)
+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
+
+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ BIT(5)
+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
+
+#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS BIT(6)
+#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
+#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
+
+#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12 BIT(7)
+#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
+#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */
+#define SD10G_LANE_LANE_0D(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 52, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0 GENMASK(1, 0)
+#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
+#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
+
+#define SD10G_LANE_LANE_0D_CFG_EQR_BYP BIT(4)
+#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
+#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */
+#define SD10G_LANE_LANE_0E(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 56, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 GENMASK(3, 0)
+#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
+#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
+
+#define SD10G_LANE_LANE_0E_CFG_RXLB_EN BIT(4)
+#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
+#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
+
+#define SD10G_LANE_LANE_0E_CFG_TXLB_EN BIT(5)
+#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
+#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
+
+#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN BIT(6)
+#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
+#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */
+#define SD10G_LANE_LANE_0F(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 60, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0 GENMASK(7, 0)
+#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
+#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */
+#define SD10G_LANE_LANE_13(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 76, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_13_CFG_DCDR_PD BIT(0)
+#define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
+#define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
+
+#define SD10G_LANE_LANE_13_CFG_PHID_1T BIT(1)
+#define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
+#define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
+
+#define SD10G_LANE_LANE_13_CFG_CDRCK_EN BIT(2)
+#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
+#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */
+#define SD10G_LANE_LANE_14(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 80, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0 GENMASK(7, 0)
+#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
+#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */
+#define SD10G_LANE_LANE_15(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 84, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8 GENMASK(7, 0)
+#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
+#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */
+#define SD10G_LANE_LANE_16(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 88, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16 GENMASK(7, 0)
+#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
+#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */
+#define SD10G_LANE_LANE_1A(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 104, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN BIT(0)
+#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
+#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
+
+#define SD10G_LANE_LANE_1A_CFG_PI_EN BIT(1)
+#define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
+#define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
+
+#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN BIT(2)
+#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
+#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
+
+#define SD10G_LANE_LANE_1A_CFG_PI_STEPS BIT(3)
+#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
+#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
+
+#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4)
+#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
+#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */
+#define SD10G_LANE_LANE_22(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 136, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1 GENMASK(4, 0)
+#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
+#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */
+#define SD10G_LANE_LANE_23(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 140, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_23_CFG_DFE_PD BIT(0)
+#define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
+#define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
+
+#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG BIT(1)
+#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
+#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
+
+#define SD10G_LANE_LANE_23_CFG_DFECK_EN BIT(2)
+#define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
+#define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
+
+#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD BIT(3)
+#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
+#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
+
+#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0 GENMASK(6, 4)
+#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
+#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */
+#define SD10G_LANE_LANE_24(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 144, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0 GENMASK(3, 0)
+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
+
+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0 GENMASK(7, 4)
+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */
+#define SD10G_LANE_LANE_26(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 152, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0)
+#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
+#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */
+#define SD10G_LANE_LANE_2F(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 188, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0 GENMASK(2, 0)
+#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
+#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
+
+#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0 GENMASK(7, 4)
+#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
+#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */
+#define SD10G_LANE_LANE_30(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 192, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_30_CFG_SUMMER_EN BIT(0)
+#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
+#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
+
+#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0 GENMASK(6, 4)
+#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
+#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */
+#define SD10G_LANE_LANE_31(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 196, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_31_CFG_PI_RSTN BIT(0)
+#define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
+#define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
+
+#define SD10G_LANE_LANE_31_CFG_CDR_RSTN BIT(1)
+#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
+#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
+
+#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG BIT(2)
+#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
+#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
+
+#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN BIT(3)
+#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
+#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
+
+#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8 BIT(4)
+#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
+#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
+
+#define SD10G_LANE_LANE_31_CFG_R50_EN BIT(5)
+#define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_31_CFG_R50_EN, x)
+#define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */
+#define SD10G_LANE_LANE_32(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 200, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0)
+#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
+#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
+
+#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
+#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
+#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */
+#define SD10G_LANE_LANE_33(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 204, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)
+#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
+#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
+
+#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4)
+#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
+#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */
+#define SD10G_LANE_LANE_35(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 212, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0 GENMASK(1, 0)
+#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
+#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
+
+#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0 GENMASK(5, 4)
+#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
+#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */
+#define SD10G_LANE_LANE_36(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 216, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0)
+#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
+#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
+
+#define SD10G_LANE_LANE_36_CFG_EID_LP BIT(4)
+#define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_36_CFG_EID_LP, x)
+#define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_36_CFG_EID_LP, x)
+
+#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH BIT(5)
+#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
+#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
+
+#define SD10G_LANE_LANE_36_CFG_PRBS_SEL BIT(6)
+#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
+#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
+
+#define SD10G_LANE_LANE_36_CFG_PRBS_SETB BIT(7)
+#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
+#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */
+#define SD10G_LANE_LANE_37(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 220, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD BIT(0)
+#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
+#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
+
+#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE BIT(1)
+#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
+#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
+
+#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF BIT(2)
+#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
+#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
+
+#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0 GENMASK(5, 4)
+#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
+#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */
+#define SD10G_LANE_LANE_39(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 228, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0 GENMASK(2, 0)
+#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
+#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
+
+#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH BIT(4)
+#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
+#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */
+#define SD10G_LANE_LANE_3A(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 232, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0 GENMASK(3, 0)
+#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
+#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
+
+#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0 GENMASK(7, 4)
+#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
+#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */
+#define SD10G_LANE_LANE_3C(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 240, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_3C_CFG_DIS_ACC BIT(0)
+#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
+#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
+
+#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER BIT(1)
+#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
+#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */
+#define SD10G_LANE_LANE_40(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 256, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0 GENMASK(7, 0)
+#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
+#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */
+#define SD10G_LANE_LANE_41(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 260, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0)
+#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
+#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */
+#define SD10G_LANE_LANE_42(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 264, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0 GENMASK(2, 0)
+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
+
+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0 GENMASK(6, 4)
+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */
+#define SD10G_LANE_LANE_48(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 0, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0 GENMASK(3, 0)
+#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
+#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
+
+#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL BIT(4)
+#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
+#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
+
+#define SD10G_LANE_LANE_48_CFG_CLK_ENQ BIT(5)
+#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
+#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */
+#define SD10G_LANE_LANE_50(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 32, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0 GENMASK(1, 0)
+#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
+#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
+
+#define SD10G_LANE_LANE_50_CFG_SSC_RESETB BIT(4)
+#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
+#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
+
+#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL BIT(5)
+#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
+#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
+
+#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL BIT(6)
+#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
+#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
+
+#define SD10G_LANE_LANE_50_CFG_JT_EN BIT(7)
+#define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_50_CFG_JT_EN, x)
+#define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */
+#define SD10G_LANE_LANE_52(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 328, 0, 1, 24, 0, 0, \
+ 1, 4)
+
+#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0)
+#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
+#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */
+#define SD10G_LANE_LANE_83(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 464, 0, 1, 112, 60, \
+ 0, 1, 4)
+
+#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE BIT(0)
+#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
+#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
+
+#define SD10G_LANE_LANE_83_R_TX_POL_INV BIT(1)
+#define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
+#define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
+
+#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE BIT(2)
+#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
+#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
+
+#define SD10G_LANE_LANE_83_R_RX_POL_INV BIT(3)
+#define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
+#define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
+
+#define SD10G_LANE_LANE_83_R_DFE_RSTN BIT(4)
+#define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
+#define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
+
+#define SD10G_LANE_LANE_83_R_CDR_RSTN BIT(5)
+#define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
+#define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
+
+#define SD10G_LANE_LANE_83_R_CTLE_RSTN BIT(6)
+#define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
+#define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */
+#define SD10G_LANE_LANE_93(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 12, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN BIT(0)
+#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
+#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
+
+#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT BIT(1)
+#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
+#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
+
+#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE BIT(2)
+#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
+#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
+
+#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL BIT(3)
+#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
+#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
+
+#define SD10G_LANE_LANE_93_R_REG_MANUAL BIT(4)
+#define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
+#define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
+
+#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT BIT(5)
+#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
+#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
+
+#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT BIT(6)
+#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
+#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
+
+#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT BIT(7)
+#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
+#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */
+#define SD10G_LANE_LANE_94(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 16, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0 GENMASK(2, 0)
+#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
+#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
+
+#define SD10G_LANE_LANE_94_R_ISCAN_REG BIT(4)
+#define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
+#define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
+
+#define SD10G_LANE_LANE_94_R_TXEQ_REG BIT(5)
+#define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
+#define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
+
+#define SD10G_LANE_LANE_94_R_MISC_REG BIT(6)
+#define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_94_R_MISC_REG, x)
+#define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_94_R_MISC_REG, x)
+
+#define SD10G_LANE_LANE_94_R_SWING_REG BIT(7)
+#define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_94_R_SWING_REG, x)
+#define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */
+#define SD10G_LANE_LANE_9E(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 56, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_9E_R_RXEQ_REG BIT(0)
+#define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
+#define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
+
+#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN BIT(1)
+#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
+#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
+
+#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN BIT(2)
+#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
+#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */
+#define SD10G_LANE_LANE_A1(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 4, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0)
+#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
+#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
+
+#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT BIT(4)
+#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
+#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
+
+#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT BIT(5)
+#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
+#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
+
+#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT BIT(6)
+#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
+#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
+
+#define SD10G_LANE_LANE_A1_R_PCLK_GATING BIT(7)
+#define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
+#define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */
+#define SD10G_LANE_LANE_A2(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 8, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)
+#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
+#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
+
+/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */
+#define SD10G_LANE_LANE_DF(t) \
+ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 832, 0, 1, 84, 60, 0,\
+ 1, 4)
+
+#define SD10G_LANE_LANE_DF_LOL_UDL BIT(0)
+#define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_DF_LOL_UDL, x)
+#define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_DF_LOL_UDL, x)
+
+#define SD10G_LANE_LANE_DF_LOL BIT(1)
+#define SD10G_LANE_LANE_DF_LOL_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)
+#define SD10G_LANE_LANE_DF_LOL_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_DF_LOL, x)
+
+#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)
+#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
+#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
+
+#define SD10G_LANE_LANE_DF_SQUELCH BIT(3)
+#define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\
+ FIELD_PREP(SD10G_LANE_LANE_DF_SQUELCH, x)
+#define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\
+ FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_0:CMU_09 */
+#define SD25G_LANE_CMU_09(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4)
+
+#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN BIT(0)
+#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
+#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
+
+#define SD25G_LANE_CMU_09_CFG_EN_DUMMY BIT(1)
+#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
+#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
+
+#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET BIT(2)
+#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
+#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
+
+#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD BIT(3)
+#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
+#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
+
+#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4)
+#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
+#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_0:CMU_0B */
+#define SD25G_LANE_CMU_0B(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4)
+
+#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT BIT(0)
+#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
+#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
+
+#define SD25G_LANE_CMU_0B_CFG_DISLOL BIT(1)
+#define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
+#define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
+
+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN BIT(2)
+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
+
+#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN BIT(3)
+#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
+#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
+
+#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD BIT(4)
+#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
+#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
+
+#define SD25G_LANE_CMU_0B_CFG_DISLOS BIT(5)
+#define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
+#define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
+
+#define SD25G_LANE_CMU_0B_CFG_DCLOL BIT(6)
+#define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
+#define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
+
+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN BIT(7)
+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_0:CMU_0C */
+#define SD25G_LANE_CMU_0C(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4)
+
+#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET BIT(0)
+#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
+#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
+
+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN BIT(1)
+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
+
+#define SD25G_LANE_CMU_0C_CFG_VCO_PD BIT(2)
+#define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
+#define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
+
+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP BIT(3)
+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
+
+#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0 GENMASK(5, 4)
+#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
+#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_0:CMU_0D */
+#define SD25G_LANE_CMU_0D(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4)
+
+#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD BIT(0)
+#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
+#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
+
+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN BIT(1)
+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
+
+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP BIT(2)
+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
+
+#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP BIT(3)
+#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
+#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
+
+#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0 GENMASK(5, 4)
+#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
+#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_0:CMU_0E */
+#define SD25G_LANE_CMU_0E(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4)
+
+#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0 GENMASK(3, 0)
+#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
+#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
+
+#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD BIT(4)
+#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
+#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_0:CMU_13 */
+#define SD25G_LANE_CMU_13(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4)
+
+#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0 GENMASK(3, 0)
+#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
+#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
+
+#define SD25G_LANE_CMU_13_CFG_JT_EN BIT(4)
+#define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_13_CFG_JT_EN, x)
+#define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_0:CMU_18 */
+#define SD25G_LANE_CMU_18(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4)
+
+#define SD25G_LANE_CMU_18_R_PLL_RSTN BIT(0)
+#define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
+#define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
+
+#define SD25G_LANE_CMU_18_R_PLL_LOL_SET BIT(1)
+#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
+#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
+
+#define SD25G_LANE_CMU_18_R_PLL_LOS_SET BIT(2)
+#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
+#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
+
+#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0 GENMASK(5, 4)
+#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
+#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_0:CMU_19 */
+#define SD25G_LANE_CMU_19(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4)
+
+#define SD25G_LANE_CMU_19_R_CK_RESETB BIT(0)
+#define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_19_R_CK_RESETB, x)
+#define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_19_R_CK_RESETB, x)
+
+#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN BIT(1)
+#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
+#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_0:CMU_1A */
+#define SD25G_LANE_CMU_1A(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4)
+
+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0 GENMASK(2, 0)
+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
+
+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT BIT(4)
+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
+
+#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE BIT(5)
+#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
+#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
+
+#define SD25G_LANE_CMU_1A_R_REG_MANUAL BIT(6)
+#define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
+#define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_1:CMU_2A */
+#define SD25G_LANE_CMU_2A(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4)
+
+#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0 GENMASK(1, 0)
+#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
+#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
+
+#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE BIT(4)
+#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
+#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
+
+#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS BIT(5)
+#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
+#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_1:CMU_30 */
+#define SD25G_LANE_CMU_30(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4)
+
+#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0)
+#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
+#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
+
+#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0 GENMASK(6, 4)
+#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
+#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_1:CMU_31 */
+#define SD25G_LANE_CMU_31(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4)
+
+#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0)
+#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
+#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_2:CMU_40 */
+#define SD25G_LANE_CMU_40(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4)
+
+#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL BIT(0)
+#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
+#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
+
+#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD BIT(1)
+#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
+#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
+
+#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK BIT(2)
+#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
+#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
+
+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN BIT(3)
+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
+
+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN BIT(4)
+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
+
+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST BIT(5)
+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_2:CMU_45 */
+#define SD25G_LANE_CMU_45(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4)
+
+#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0 GENMASK(7, 0)
+#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
+#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_2:CMU_46 */
+#define SD25G_LANE_CMU_46(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4)
+
+#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0)
+#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
+#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_3:CMU_C0 */
+#define SD25G_LANE_CMU_C0(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4)
+
+#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0 GENMASK(3, 0)
+#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
+#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
+
+#define SD25G_LANE_CMU_C0_PLL_LOL_UDL BIT(4)
+#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
+#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:CMU_GRP_4:CMU_FF */
+#define SD25G_LANE_CMU_FF(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4)
+
+#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX GENMASK(7, 0)
+#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\
+ FIELD_PREP(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
+#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\
+ FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_00 */
+#define SD25G_LANE_LANE_00(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4)
+
+#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0)
+#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
+#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
+
+#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
+#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
+#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_01 */
+#define SD25G_LANE_LANE_01(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4)
+
+#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)
+#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
+#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
+
+#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0 GENMASK(5, 4)
+#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
+#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_03 */
+#define SD25G_LANE_LANE_03(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4)
+
+#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0 GENMASK(4, 0)
+#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
+#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_04 */
+#define SD25G_LANE_LANE_04(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4)
+
+#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN BIT(0)
+#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
+#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
+
+#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN BIT(1)
+#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
+#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
+
+#define SD25G_LANE_LANE_04_LN_CFG_PD_CML BIT(2)
+#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
+#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
+
+#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK BIT(3)
+#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
+#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
+
+#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER BIT(4)
+#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
+#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
+
+#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN BIT(5)
+#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
+#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_05 */
+#define SD25G_LANE_LANE_05(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4)
+
+#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0 GENMASK(3, 0)
+#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
+#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
+
+#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0 GENMASK(5, 4)
+#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
+#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_06 */
+#define SD25G_LANE_LANE_06(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4)
+
+#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN BIT(0)
+#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
+#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
+
+#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0 GENMASK(7, 4)
+#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
+#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_07 */
+#define SD25G_LANE_LANE_07(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4)
+
+#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV BIT(0)
+#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
+#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
+
+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2 BIT(1)
+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
+
+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY BIT(2)
+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_09 */
+#define SD25G_LANE_LANE_09(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4)
+
+#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0)
+#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
+#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_0A */
+#define SD25G_LANE_LANE_0A(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4)
+
+#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0)
+#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
+#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_0B */
+#define SD25G_LANE_LANE_0B(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4)
+
+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN BIT(0)
+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
+
+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST BIT(1)
+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
+
+#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0 GENMASK(5, 4)
+#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
+#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_0C */
+#define SD25G_LANE_LANE_0C(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4)
+
+#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)
+#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
+#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
+
+#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN BIT(4)
+#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
+#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
+
+#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD BIT(5)
+#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
+#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_0D */
+#define SD25G_LANE_LANE_0D(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4)
+
+#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0 GENMASK(2, 0)
+#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
+#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
+
+#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8 BIT(4)
+#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
+#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
+
+#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN BIT(5)
+#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
+#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
+
+#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD BIT(6)
+#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
+#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
+
+#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN BIT(7)
+#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
+#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_0E */
+#define SD25G_LANE_LANE_0E(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4)
+
+#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN BIT(0)
+#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
+#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
+
+#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD BIT(1)
+#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
+#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
+
+#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG BIT(2)
+#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
+#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
+
+#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0 GENMASK(6, 4)
+#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
+#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_0F */
+#define SD25G_LANE_LANE_0F(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4)
+
+#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1 GENMASK(4, 0)
+#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
+#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_18 */
+#define SD25G_LANE_LANE_18(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4)
+
+#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN BIT(0)
+#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
+#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
+
+#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT BIT(1)
+#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
+#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
+
+#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN BIT(2)
+#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
+#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
+
+#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD BIT(3)
+#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
+#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
+
+#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0 GENMASK(6, 4)
+#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
+#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_19 */
+#define SD25G_LANE_LANE_19(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4)
+
+#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD BIT(0)
+#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
+#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
+
+#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD BIT(1)
+#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
+#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
+
+#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL BIT(2)
+#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
+#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
+
+#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN BIT(3)
+#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
+#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
+
+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU BIT(4)
+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
+
+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP BIT(5)
+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
+
+#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET BIT(6)
+#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
+#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
+
+#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE BIT(7)
+#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
+#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_1A */
+#define SD25G_LANE_LANE_1A(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4)
+
+#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN BIT(0)
+#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
+#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
+
+#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0 GENMASK(6, 4)
+#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
+#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_1B */
+#define SD25G_LANE_LANE_1B(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4)
+
+#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0 GENMASK(7, 0)
+#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
+#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_1C */
+#define SD25G_LANE_LANE_1C(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4)
+
+#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN BIT(0)
+#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
+#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
+
+#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD BIT(1)
+#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
+#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
+
+#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD BIT(2)
+#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
+#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
+
+#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 GENMASK(7, 4)
+#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
+#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_1D */
+#define SD25G_LANE_LANE_1D(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4)
+
+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR BIT(0)
+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
+
+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD BIT(1)
+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
+
+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN BIT(2)
+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
+
+#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP BIT(3)
+#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
+#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
+
+#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T BIT(4)
+#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
+#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
+
+#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN BIT(5)
+#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
+#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
+
+#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR BIT(6)
+#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
+#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
+
+#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD BIT(7)
+#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
+#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_1E */
+#define SD25G_LANE_LANE_1E(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4)
+
+#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0 GENMASK(1, 0)
+#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
+#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
+
+#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN BIT(4)
+#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
+#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
+
+#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN BIT(5)
+#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
+#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
+
+#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR BIT(6)
+#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
+#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
+
+#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD BIT(7)
+#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
+#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_21 */
+#define SD25G_LANE_LANE_21(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4)
+
+#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0)
+#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
+#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_22 */
+#define SD25G_LANE_LANE_22(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4)
+
+#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0 GENMASK(3, 0)
+#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
+#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_25 */
+#define SD25G_LANE_LANE_25(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4)
+
+#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0)
+#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
+#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_26 */
+#define SD25G_LANE_LANE_26(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4)
+
+#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0)
+#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
+#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_28 */
+#define SD25G_LANE_LANE_28(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4)
+
+#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN BIT(0)
+#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
+#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
+
+#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH BIT(1)
+#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
+#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
+
+#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL BIT(2)
+#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
+#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
+
+#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0 GENMASK(6, 4)
+#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
+#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_2B */
+#define SD25G_LANE_LANE_2B(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4)
+
+#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0 GENMASK(3, 0)
+#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
+#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
+
+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR BIT(4)
+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
+
+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU BIT(5)
+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_2C */
+#define SD25G_LANE_LANE_2C(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4)
+
+#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0)
+#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
+#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
+
+#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER BIT(4)
+#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
+#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_2D */
+#define SD25G_LANE_LANE_2D(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4)
+
+#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0 GENMASK(2, 0)
+#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
+#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
+
+#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0 GENMASK(6, 4)
+#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
+#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_2E */
+#define SD25G_LANE_LANE_2E(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4)
+
+#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN BIT(0)
+#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
+#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
+
+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ BIT(1)
+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
+
+#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ BIT(2)
+#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
+#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
+
+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS BIT(3)
+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
+
+#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC BIT(4)
+#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
+#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
+
+#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG BIT(5)
+#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
+#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
+
+#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN BIT(6)
+#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
+#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
+
+#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN BIT(7)
+#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
+#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_40 */
+#define SD25G_LANE_LANE_40(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4)
+
+#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE BIT(0)
+#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
+#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
+
+#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV BIT(1)
+#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
+#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
+
+#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE BIT(2)
+#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
+#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
+
+#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV BIT(3)
+#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
+#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
+
+#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN BIT(4)
+#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
+#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
+
+#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN BIT(5)
+#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
+#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
+
+#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN BIT(6)
+#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
+#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_42 */
+#define SD25G_LANE_LANE_42(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4)
+
+#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0)
+#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
+#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_43 */
+#define SD25G_LANE_LANE_43(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4)
+
+#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0)
+#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
+#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_44 */
+#define SD25G_LANE_LANE_44(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4)
+
+#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0)
+#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
+#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_0:LANE_45 */
+#define SD25G_LANE_LANE_45(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4)
+
+#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0)
+#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
+#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
+
+/* SPARX5 ONLY */
+/* SD25G_TARGET:LANE_GRP_1:LANE_DE */
+#define SD25G_LANE_LANE_DE(t) \
+ __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4)
+
+#define SD25G_LANE_LANE_DE_LN_LOL_UDL BIT(0)
+#define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
+#define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
+
+#define SD25G_LANE_LANE_DE_LN_LOL BIT(1)
+#define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL, x)
+#define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL, x)
+
+#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED BIT(2)
+#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
+#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
+
+#define SD25G_LANE_LANE_DE_LN_PMA_RXEI BIT(3)
+#define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\
+ FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
+#define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\
+ FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
+
+/* SPARX5 ONLY */
+/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */
+#define SD6G_LANE_LANE_DF(t) \
+ __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4)
+
+#define SD6G_LANE_LANE_DF_LOL_UDL BIT(0)
+#define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\
+ FIELD_PREP(SD6G_LANE_LANE_DF_LOL_UDL, x)
+#define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\
+ FIELD_GET(SD6G_LANE_LANE_DF_LOL_UDL, x)
+
+#define SD6G_LANE_LANE_DF_LOL BIT(1)
+#define SD6G_LANE_LANE_DF_LOL_SET(x)\
+ FIELD_PREP(SD6G_LANE_LANE_DF_LOL, x)
+#define SD6G_LANE_LANE_DF_LOL_GET(x)\
+ FIELD_GET(SD6G_LANE_LANE_DF_LOL, x)
+
+#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)
+#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
+ FIELD_PREP(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
+#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
+ FIELD_GET(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
+
+#define SD6G_LANE_LANE_DF_SQUELCH BIT(3)
+#define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\
+ FIELD_PREP(SD6G_LANE_LANE_DF_SQUELCH, x)
+#define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\
+ FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */
+#define SD_CMU_CMU_00(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 0, 0, 1, 20, 0, 0, 1, 4)
+
+#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE BIT(0)
+#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
+#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\
+ FIELD_GET(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
+
+#define SD_CMU_CMU_00_CFG_PLL_LOL_SET BIT(1)
+#define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
+#define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\
+ FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
+
+#define SD_CMU_CMU_00_CFG_PLL_LOS_SET BIT(2)
+#define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
+#define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\
+ FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
+
+#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4)
+#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
+#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\
+ FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */
+#define SD_CMU_CMU_05(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 0, 0, 1, 4)
+
+#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN BIT(0)
+#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
+#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\
+ FIELD_GET(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
+
+#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0 GENMASK(5, 4)
+#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
+#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\
+ FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */
+#define SD_CMU_CMU_06(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 4, 0, 1, 4)
+
+#define SD_CMU_CMU_06_CFG_DISLOS BIT(0)
+#define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOS, x)
+#define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\
+ FIELD_GET(SD_CMU_CMU_06_CFG_DISLOS, x)
+
+#define SD_CMU_CMU_06_CFG_DISLOL BIT(1)
+#define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOL, x)
+#define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\
+ FIELD_GET(SD_CMU_CMU_06_CFG_DISLOL, x)
+
+#define SD_CMU_CMU_06_CFG_DCLOL BIT(2)
+#define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_06_CFG_DCLOL, x)
+#define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\
+ FIELD_GET(SD_CMU_CMU_06_CFG_DCLOL, x)
+
+#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT BIT(3)
+#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)
+#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\
+ FIELD_GET(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)
+
+#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD BIT(4)
+#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)
+#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\
+ FIELD_GET(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)
+
+#define SD_CMU_CMU_06_CFG_VCO_PD BIT(5)
+#define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_PD, x)
+#define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\
+ FIELD_GET(SD_CMU_CMU_06_CFG_VCO_PD, x)
+
+#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN BIT(6)
+#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)
+#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\
+ FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)
+
+#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP BIT(7)
+#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)
+#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\
+ FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */
+#define SD_CMU_CMU_08(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 12, 0, 1, 4)
+
+#define SD_CMU_CMU_08_CFG_VFILT2PAD BIT(0)
+#define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_08_CFG_VFILT2PAD, x)
+#define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\
+ FIELD_GET(SD_CMU_CMU_08_CFG_VFILT2PAD, x)
+
+#define SD_CMU_CMU_08_CFG_EN_DUMMY BIT(1)
+#define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_08_CFG_EN_DUMMY, x)
+#define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\
+ FIELD_GET(SD_CMU_CMU_08_CFG_EN_DUMMY, x)
+
+#define SD_CMU_CMU_08_CFG_CK_TREE_PD BIT(2)
+#define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)
+#define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\
+ FIELD_GET(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)
+
+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN BIT(3)
+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)
+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\
+ FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)
+
+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN BIT(4)
+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)
+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\
+ FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */
+#define SD_CMU_CMU_09(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 16, 0, 1, 4)
+
+#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP BIT(0)
+#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
+#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\
+ FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
+
+#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN BIT(1)
+#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
+#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\
+ FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
+
+#define SD_CMU_CMU_09_CFG_SW_8G BIT(4)
+#define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x)
+#define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\
+ FIELD_GET(SD_CMU_CMU_09_CFG_SW_8G, x)
+
+#define SD_CMU_CMU_09_CFG_SW_10G BIT(5)
+#define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_09_CFG_SW_10G, x)
+#define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\
+ FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */
+#define SD_CMU_CMU_0D(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 32, 0, 1, 4)
+
+#define SD_CMU_CMU_0D_CFG_PD_DIV64 BIT(0)
+#define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
+#define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\
+ FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
+
+#define SD_CMU_CMU_0D_CFG_PD_DIV66 BIT(1)
+#define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
+#define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\
+ FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
+
+#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD BIT(2)
+#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
+#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\
+ FIELD_GET(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
+
+#define SD_CMU_CMU_0D_CFG_JC_BYP BIT(3)
+#define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_0D_CFG_JC_BYP, x)
+#define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\
+ FIELD_GET(SD_CMU_CMU_0D_CFG_JC_BYP, x)
+
+#define SD_CMU_CMU_0D_CFG_REFCK_PD BIT(4)
+#define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
+#define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\
+ FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */
+#define SD_CMU_CMU_1B(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 104, 0, 1, 20, 4, 0, 1, 4)
+
+#define SD_CMU_CMU_1B_CFG_RESERVE_7_0 GENMASK(7, 0)
+#define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
+#define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\
+ FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */
+#define SD_CMU_CMU_1F(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 124, 0, 1, 68, 0, 0, 1, 4)
+
+#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN BIT(0)
+#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
+#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\
+ FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
+
+#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN BIT(1)
+#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
+#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\
+ FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
+
+#define SD_CMU_CMU_1F_CFG_IC2IP_N BIT(2)
+#define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
+#define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\
+ FIELD_GET(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
+
+#define SD_CMU_CMU_1F_CFG_VTUNE_SEL BIT(3)
+#define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
+#define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\
+ FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */
+#define SD_CMU_CMU_30(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 192, 0, 1, 72, 0, 0, 1, 4)
+
+#define SD_CMU_CMU_30_R_PLL_DLOL_EN BIT(0)
+#define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
+#define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\
+ FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */
+#define SD_CMU_CMU_44(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 8, 0, 1, 4)
+
+#define SD_CMU_CMU_44_R_PLL_RSTN BIT(0)
+#define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_44_R_PLL_RSTN, x)
+#define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\
+ FIELD_GET(SD_CMU_CMU_44_R_PLL_RSTN, x)
+
+#define SD_CMU_CMU_44_R_CK_RESETB BIT(1)
+#define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_44_R_CK_RESETB, x)
+#define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\
+ FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */
+#define SD_CMU_CMU_45(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 12, 0, 1, 4)
+
+#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL BIT(0)
+#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
+#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\
+ FIELD_GET(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
+
+#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT BIT(1)
+#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
+#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\
+ FIELD_GET(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
+
+#define SD_CMU_CMU_45_RESERVED BIT(2)
+#define SD_CMU_CMU_45_RESERVED_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_45_RESERVED, x)
+#define SD_CMU_CMU_45_RESERVED_GET(x)\
+ FIELD_GET(SD_CMU_CMU_45_RESERVED, x)
+
+#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT BIT(3)
+#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
+#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\
+ FIELD_GET(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
+
+#define SD_CMU_CMU_45_RESERVED_2 BIT(4)
+#define SD_CMU_CMU_45_RESERVED_2_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_45_RESERVED_2, x)
+#define SD_CMU_CMU_45_RESERVED_2_GET(x)\
+ FIELD_GET(SD_CMU_CMU_45_RESERVED_2, x)
+
+#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT BIT(5)
+#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
+#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\
+ FIELD_GET(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
+
+#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT BIT(6)
+#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
+#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\
+ FIELD_GET(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
+
+#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN BIT(7)
+#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
+#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\
+ FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */
+#define SD_CMU_CMU_47(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 20, 0, 1, 4)
+
+#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)
+#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
+#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\
+ FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
+
+/* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */
+#define SD_CMU_CMU_E0(t) \
+ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 896, 0, 1, 8, 0, 0, 1, 4)
+
+#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0 GENMASK(3, 0)
+#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
+#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\
+ FIELD_GET(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
+
+#define SD_CMU_CMU_E0_PLL_LOL_UDL BIT(4)
+#define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\
+ FIELD_PREP(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
+#define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\
+ FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
+
+/* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */
+#define SD_CMU_CFG_SD_CMU_CFG(t) \
+ __REG(TARGET_SD_CMU_CFG, t, TSIZE(TC_SD_CMU_CFG), 0, 0, 1, 8, 0, 0, 1, \
+ 4)
+
+#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST BIT(0)
+#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\
+ FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
+#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\
+ FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
+
+#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST BIT(1)
+#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\
+ FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
+#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\
+ FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
+
+/* SD_LANE_TARGET:SD_RESET:SD_SER_RST */
+#define SD_LANE_SD_SER_RST(t) \
+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 0, 0, 1, 4)
+
+#define SD_LANE_SD_SER_RST_SER_RST BIT(0)
+#define SD_LANE_SD_SER_RST_SER_RST_SET(x)\
+ FIELD_PREP(SD_LANE_SD_SER_RST_SER_RST, x)
+#define SD_LANE_SD_SER_RST_SER_RST_GET(x)\
+ FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x)
+
+/* SD_LANE_TARGET:SD_RESET:SD_DES_RST */
+#define SD_LANE_SD_DES_RST(t) \
+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 4, 0, 1, 4)
+
+#define SD_LANE_SD_DES_RST_DES_RST BIT(0)
+#define SD_LANE_SD_DES_RST_DES_RST_SET(x)\
+ FIELD_PREP(SD_LANE_SD_DES_RST_DES_RST, x)
+#define SD_LANE_SD_DES_RST_DES_RST_GET(x)\
+ FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x)
+
+/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */
+#define SD_LANE_SD_LANE_CFG(t) \
+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 0, 0, 1, 4)
+
+#define SD_LANE_SD_LANE_CFG_MACRO_RST BIT(0)
+#define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\
+ FIELD_PREP(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
+#define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\
+ FIELD_GET(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
+
+#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST BIT(1)
+#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\
+ FIELD_PREP(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
+#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\
+ FIELD_GET(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
+
+#define SD_LANE_SD_LANE_CFG_TX_REF_SEL GENMASK(5, 4)
+#define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\
+ FIELD_PREP(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
+#define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\
+ FIELD_GET(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
+
+#define SD_LANE_SD_LANE_CFG_RX_REF_SEL GENMASK(7, 6)
+#define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\
+ FIELD_PREP(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
+#define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\
+ FIELD_GET(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
+
+#define SD_LANE_SD_LANE_CFG_LANE_RST BIT(8)
+#define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\
+ FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RST, x)
+#define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\
+ FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RST, x)
+
+#define SD_LANE_SD_LANE_CFG_LANE_TX_RST BIT(9)
+#define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\
+ FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
+#define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\
+ FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
+
+#define SD_LANE_SD_LANE_CFG_LANE_RX_RST BIT(10)
+#define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\
+ FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
+#define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\
+ FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
+
+/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */
+#define SD_LANE_SD_LANE_STAT(t) \
+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 4, 0, 1, 4)
+
+#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE BIT(0)
+#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\
+ FIELD_PREP(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
+#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\
+ FIELD_GET(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
+
+#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE BIT(1)
+#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\
+ FIELD_PREP(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
+#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\
+ FIELD_GET(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
+
+#define SD_LANE_SD_LANE_STAT_DBG_OBS GENMASK(31, 16)
+#define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\
+ FIELD_PREP(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
+#define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\
+ FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
+
+/* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */
+#define SD_LANE_QUIET_MODE_6G(t) \
+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 24, 0, 1, 8, 4, 0, 1, 4)
+
+#define SD_LANE_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0)
+#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\
+ FIELD_PREP(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)
+#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\
+ FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)
+
+/* SD_LANE_TARGET:CFG_STAT_FX100:MISC */
+#define SD_LANE_MISC(t) \
+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 0, 0, 1, 4)
+
+#define SD_LANE_MISC_SD_125_RST_DIS BIT(0)
+#define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\
+ FIELD_PREP(SD_LANE_MISC_SD_125_RST_DIS, x)
+#define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\
+ FIELD_GET(SD_LANE_MISC_SD_125_RST_DIS, x)
+
+#define SD_LANE_MISC_RX_ENA BIT(1)
+#define SD_LANE_MISC_RX_ENA_SET(x)\
+ FIELD_PREP(SD_LANE_MISC_RX_ENA, x)
+#define SD_LANE_MISC_RX_ENA_GET(x)\
+ FIELD_GET(SD_LANE_MISC_RX_ENA, x)
+
+#define SD_LANE_MISC_MUX_ENA BIT(2)
+#define SD_LANE_MISC_MUX_ENA_SET(x)\
+ FIELD_PREP(SD_LANE_MISC_MUX_ENA, x)
+#define SD_LANE_MISC_MUX_ENA_GET(x)\
+ FIELD_GET(SD_LANE_MISC_MUX_ENA, x)
+
+/* SPARX5 ONLY */
+#define SD_LANE_MISC_CORE_CLK_FREQ GENMASK(5, 4)
+#define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\
+ FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x)
+#define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\
+ FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x)
+
+/* LAN969X ONLY */
+#define SD_LANE_MISC_FX_RX_CLK_CYCLE_LEN GENMASK(10, 8)
+#define SD_LANE_MISC_FX_RX_CLK_CYCLE_LEN_SET(x)\
+ FIELD_PREP(SD_LANE_MISC_FX_RX_CLK_CYCLE_LEN, x)
+#define SD_LANE_MISC_FX_RX_CLK_CYCLE_LEN_GET(x)\
+ FIELD_GET(SD_LANE_MISC_FX_RX_CLK_CYCLE_LEN, x)
+
+/* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */
+#define SD_LANE_M_STAT_MISC(t) \
+ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 36, 0, 1, 4)
+
+#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0)
+#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\
+ FIELD_PREP(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
+#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\
+ FIELD_GET(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
+
+#define SD_LANE_M_STAT_MISC_M_LOCK_CNT GENMASK(31, 24)
+#define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\
+ FIELD_PREP(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
+#define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\
+ FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
+
+/* SPARX5 ONLY */
+/* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */
+#define SD_LANE_25G_SD_SER_RST(t) \
+ __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4)
+
+#define SD_LANE_25G_SD_SER_RST_SER_RST BIT(0)
+#define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_SER_RST_SER_RST, x)
+#define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x)
+
+/* SPARX5 ONLY */
+/* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */
+#define SD_LANE_25G_SD_DES_RST(t) \
+ __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4)
+
+#define SD_LANE_25G_SD_DES_RST_DES_RST BIT(0)
+#define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_DES_RST_DES_RST, x)
+#define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x)
+
+/* SPARX5 ONLY */
+/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */
+#define SD_LANE_25G_SD_LANE_CFG(t) \
+ __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4)
+
+#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST BIT(0)
+#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
+#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST BIT(1)
+#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
+#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE BIT(4)
+#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
+#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE GENMASK(7, 5)
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_LANE_RST BIT(8)
+#define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
+#define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV BIT(9)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN BIT(10)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY BIT(11)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV GENMASK(15, 12)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN BIT(16)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY GENMASK(21, 17)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN BIT(22)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN BIT(23)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING BIT(24)
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI BIT(25)
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
+
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN GENMASK(28, 26)
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
+
+/* SPARX5 ONLY */
+/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */
+#define SD_LANE_25G_SD_LANE_CFG2(t) \
+ __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4)
+
+#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL GENMASK(2, 0)
+#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
+#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
+
+#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL GENMASK(5, 3)
+#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
+#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
+
+#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL GENMASK(8, 6)
+#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
+#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
+
+#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED GENMASK(10, 9)
+#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
+#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
+
+#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV GENMASK(13, 11)
+#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
+#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
+
+#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV GENMASK(16, 14)
+#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
+#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
+
+#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL GENMASK(19, 17)
+#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
+#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
+
+#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV GENMASK(23, 20)
+#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
+#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
+
+#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL GENMASK(25, 24)
+#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
+#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
+
+#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL GENMASK(28, 26)
+#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
+#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
+
+#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL GENMASK(31, 29)
+#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
+#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
+
+/* SPARX5 ONLY */
+/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */
+#define SD_LANE_25G_SD_LANE_STAT(t) \
+ __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4)
+
+#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE BIT(0)
+#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
+#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
+
+#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE BIT(1)
+#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
+#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
+
+#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS GENMASK(31, 16)
+#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\
+ FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
+#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\
+ FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
+
+/* SPARX5 ONLY */
+/* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */
+#define SD_LANE_25G_QUIET_MODE_6G(t) \
+ __REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4)
+
+#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0)
+#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\
+ FIELD_PREP(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)
+#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\
+ FIELD_GET(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)
+
+#endif /* _SPARX5_MAIN_REGS_H_ */
diff --git a/drivers/net/mscc_eswitch/sparx5_switch.c b/drivers/net/mscc_eswitch/sparx5_switch.c
new file mode 100644
index 00000000000..4e36c983d35
--- /dev/null
+++ b/drivers/net/mscc_eswitch/sparx5_switch.c
@@ -0,0 +1,1181 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include <config.h>
+#include <dm.h>
+#include <dm/devres.h>
+#include <dm/of_access.h>
+#include <dm/of_addr.h>
+#include <fdt_support.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <miiphy.h>
+#include <net.h>
+#include <wait_bit.h>
+#include <command.h>
+
+#include "sparx5_switch.h"
+
+#include "sparx5_regs.h"
+#include "sparx5_reg_offset.h"
+
+#include <dt-bindings/mscc/sparx5_data.h>
+
+static struct sparx5_private *dev_priv;
+
+#define MAC_VID 1 /* Also = FID 1 */
+#define ETH_ALEN 6
+
+#define PGID_L2_UC(priv) (priv->data->num_ports + 0)
+#define PGID_L2_MC(priv) (priv->data->num_ports + 1)
+#define PGID_BROADCAST(priv) (priv->data->num_ports + 2)
+#define PGID_HOST(priv) (priv->data->num_ports + 3)
+
+#define CONFIG_IFH_FMT_NONE 0
+
+#define DSM_CAL_MAX_DEVS_PER_TAXI 10
+#define DSM_CAL_TAXIS 5
+#define DSM_CAL_LEN 64
+
+#define SPX5_RGMII_TX_CLK_125MHZ 1 /* 1000Mbps */
+#define SPX5_RGMII_TX_CLK_25MHZ 2 /* 100Mbps */
+#define SPX5_RGMII_TX_CLK_2M5MHZ 3 /* 10Mbps */
+
+static const char * const sparx5_reg_names[] = {
+ "ana_ac", "ana_cl", "ana_l2", "ana_l3",
+ "asm", "lrn", "qfwd", "qs",
+ "qsys", "rew", "vop", "dsm", "eacl",
+ "vcap_super", "hsch", "port_conf", "xqs", "hsio", "gcb", "cpu", "ptp",
+ "port0", "port1", "port2", "port3", "port4", "port5", "port6",
+ "port7", "port8", "port9", "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17", "port18", "port19", "port20",
+ "port21", "port22", "port23", "port24", "port25", "port26", "port27",
+ "port28", "port29", "port30", "port31", "port32", "port33", "port34",
+ "port35", "port36", "port37", "port38", "port39", "port40", "port41",
+ "port42", "port43", "port44", "port45", "port46", "port47", "port48",
+ "port49", "port50", "port51", "port52", "port53", "port54", "port55",
+ "port56", "port57", "port58", "port59", "port60", "port61", "port62",
+ "port63", "port64",
+};
+
+static const char * const lan969x_reg_names[] = {
+ "ana_ac", "ana_cl", "ana_l2", "ana_l3",
+ "asm", "lrn", "qfwd", "qs",
+ "qsys", "rew", "vop", "dsm", "eacl",
+ "vcap_super", "hsch", "port_conf", "xqs", "hsio", "gcb", "cpu", "ptp",
+ "port0", "port1", "port2", "port3", "port4", "port5", "port6",
+ "port7", "port8", "port9", "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17", "port18", "port19", "port20",
+ "port21", "port22", "port23", "port24", "port25", "port26", "port27",
+ "port28", "port29",
+};
+
+enum sparx5_ctrl_regs {
+ TARGET_ANA_AC,
+ TARGET_ANA_CL,
+ TARGET_ANA_L2,
+ TARGET_ANA_L3,
+ TARGET_ASM,
+ TARGET_LRN,
+ TARGET_QFWD,
+ TARGET_QS,
+ TARGET_QSYS,
+ TARGET_REW,
+ TARGET_VOP,
+ TARGET_DSM,
+ TARGET_EACL,
+ TARGET_VCAP_SUPER,
+ TARGET_HSCH,
+ TARGET_PORT_CONF,
+ TARGET_XQS,
+ TARGET_HSIO,
+ TARGET_GCB,
+ TARGET_CPU,
+ TARGET_PTP,
+ __REG_MAX,
+ /* This is used for all the ports even if it a 2.5G or RGMII */
+ TARGET_DEV2G5 = __REG_MAX,
+};
+
+static const unsigned long sparx5_regs_qs[] = {
+ [MSCC_QS_XTR_RD] = 0x8,
+ [MSCC_QS_XTR_FLUSH] = 0x18,
+ [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
+ [MSCC_QS_INJ_WR] = 0x2c,
+ [MSCC_QS_INJ_CTRL] = 0x34,
+};
+
+enum {
+ SERDES_ARG_MAC_TYPE,
+ SERDES_ARG_SERDES,
+ SERDES_ARG_SER_IDX,
+ SERDES_ARG_MAX,
+};
+
+static struct mscc_match_data mscc_sparx5_data = {
+ .reg_names = sparx5_reg_names,
+ .regs = {
+ .reggrp_addr = sparx5_reggrp_addr,
+ .reggrp_cnt = sparx5_reggrp_cnt,
+ .reggrp_size = sparx5_reggrp_sz,
+ .reg_addr = sparx5_reg_addr,
+ .reg_cnt = sparx5_reg_cnt,
+ .regfield_addr = sparx5_regfield_addr,
+ },
+ .num_regs = 86,
+ .num_ports = 65,
+ .num_bus = 4,
+ .cpu_port = 65,
+ .npi_port = 64,
+ .ifh_len = 9,
+ .num_cal_auto = 7,
+ .target = SPARX5_TARGET,
+};
+
+static struct mscc_match_data mscc_lan969x_data = {
+ .reg_names = lan969x_reg_names,
+ .regs = {
+ .reggrp_addr = lan969x_reggrp_addr,
+ .reggrp_cnt = lan969x_reggrp_cnt,
+ .reggrp_size = lan969x_reggrp_sz,
+ .reg_addr = lan969x_reg_addr,
+ .reg_cnt = lan969x_reg_cnt,
+ .regfield_addr = lan969x_regfield_addr,
+ },
+ .num_regs = 51,
+ .num_ports = 30,
+ .num_bus = 2,
+ .cpu_port = 30,
+ .npi_port = 24,
+ .ifh_len = 9,
+ .num_cal_auto = 4,
+ .target = LAN969X_TARGET,
+};
+
+/* Keep the id, tinst and tcnt just to be able to use the same macros
+ * as in the linux kernel
+ */
+static u32 spx5_rd(struct sparx5_private *priv,
+ int id, int tinst, int tcnt,
+ u32 gbase, u32 ginst, u32 gcnt, u32 gwidth,
+ u32 raddr, u32 rinst, u32 rcnt, u32 rwidth)
+{
+ return readl(priv->regs[id + tinst] +
+ gbase + ((ginst) * gwidth) +
+ raddr + ((rinst) * rwidth));
+}
+
+static void spx5_wr(u32 val, struct sparx5_private *priv,
+ int id, int tinst, int tcnt,
+ u32 gbase, u32 ginst, u32 gcnt, u32 gwidth,
+ u32 raddr, u32 rinst, u32 rcnt, u32 rwidth)
+{
+ writel(val,
+ priv->regs[id + tinst] + gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth));
+}
+
+static void spx5_rmw(u32 val, u32 mask, struct sparx5_private *priv,
+ int id, int tinst, int tcnt,
+ u32 gbase, u32 ginst, u32 gcnt, u32 gwidth,
+ u32 raddr, u32 rinst, u32 rcnt, u32 rwidth)
+{
+ u32 nval;
+
+ nval = readl(priv->regs[id + tinst] + gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth));
+ nval = (nval & ~mask) | (val & mask);
+ writel(nval, priv->regs[id + tinst] + gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth));
+}
+
+static void __iomem *spx5_offset(struct sparx5_private *priv,
+ u32 id, u32 tinst, u32 tcnt,
+ u32 gbase, u32 ginst, u32 gcnt, u32 gwidth,
+ u32 raddr, u32 rinst, u32 rcnt, u32 rwidth)
+{
+ return priv->regs[id + tinst] + gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth);
+}
+
+static int ram_init(void __iomem *addr)
+{
+ writel(BIT(1), addr);
+
+ if (wait_for_bit_le32(addr, BIT(1), false, 2000, false)) {
+ printf("Timeout in memory reset, addr: %p = 0x%08x\n", addr, readl(addr));
+ return 1;
+ }
+
+ return 0;
+}
+
+static int sparx5_switch_init(struct sparx5_private *priv)
+{
+ /* Initialize memories */
+ ram_init(spx5_offset(priv, QSYS_RAM_INIT));
+ ram_init(spx5_offset(priv, ASM_RAM_INIT));
+ ram_init(spx5_offset(priv, ANA_AC_RAM_INIT));
+ ram_init(spx5_offset(priv, REW_RAM_INIT));
+ ram_init(spx5_offset(priv, DSM_RAM_INIT));
+ ram_init(spx5_offset(priv, EACL_RAM_INIT));
+ ram_init(spx5_offset(priv, VCAP_SUPER_RAM_INIT));
+ ram_init(spx5_offset(priv, VOP_RAM_INIT));
+
+ /* Reset counters */
+ spx5_wr(0x1, priv, ANA_AC_STAT_RESET);
+ spx5_wr(0x1, priv, ASM_STAT_CFG);
+
+ return 0;
+}
+
+static void sparx5_taxi2ports(u32 taxi, u32 *port_ptr) {
+ u32 taxi_ports[DSM_CAL_TAXIS][DSM_CAL_MAX_DEVS_PER_TAXI] = {
+ {0,4,1,2,3,5,6,7,28,29},
+ {8,12,9,13,10,11,14,15,99,99},
+ {16,20,17,21,18,19,22,23,99,99},
+ {24,25,99,99,99,99,99,99,99,99},
+ {26,27,99,99,99,99,99,99,99,99}};
+
+ memcpy(port_ptr, &taxi_ports[taxi],
+ sizeof(u32) * DSM_CAL_MAX_DEVS_PER_TAXI);
+}
+
+static int sparx5_dsm_calc_calendar(u32 *speeds, u32 ports, u32 freq_mhz,
+ u32 *cal, u32 *cal_len) {
+ int bw = freq_mhz * 128 / 1.05;
+ int grps = 3;
+ int grp[ports];
+ int cnt[30];
+ int grpspd = 10000;
+ int bwavail[3], s_values[] = {5000, 2500, 1000};
+ int i, j, p, sp, win, grplen, lcs, s, found;
+
+ if (bw < 30000) {
+ for (i = 0; i < ports && speeds[i] != 10000; i++);
+ if (i == ports)
+ grpspd = 5000;
+ else
+ grps = 2;
+ }
+
+ lcs = grpspd;
+ for (i = 0; i < 3; i++) {
+ s = s_values[i];
+ found = 0;
+ for (j = 0; j < ports; j++) {
+ if (speeds[j] == s) {
+ found = 1;
+ break;
+ }
+ }
+
+ if (found) {
+ if (lcs == 2500) {
+ lcs = 500;
+ } else {
+ lcs = s;
+ }
+ }
+ }
+ grplen = grpspd / lcs;
+
+ for (i = 0; i < grps; bwavail[i++] = grpspd);
+
+ for (i = 0; i < ports; i++) {
+ if (!speeds[i]) {
+ continue;
+ }
+ for (j = 0; j < grps && bwavail[j] < speeds[i]; j++);
+ if (j == grps) {
+ printf("Could not generate calendar at taxibw %d\n", bw);
+ return -1;
+ }
+ grp[i] = j;
+ bwavail[j] -= speeds[i];
+ }
+
+ memset(cnt, 0, sizeof(cnt));
+ for (i = 0; i < grplen; i++) {
+ for (j = 0; j < grps; j++) {
+ sp = 1;
+ win = ports;
+ for (p = 0; p < ports; p++) {
+ if (grp[p] != j) {
+ continue;
+ }
+ cnt[p] -= (cnt[p] > 0);
+ if (speeds[p] > sp && !cnt[p]) {
+ win = p;
+ sp = speeds[p];
+ }
+ }
+ if (win == ports) {
+ win = 10;
+ }
+
+ cnt[win] = grpspd/sp;
+ cal[i * grps + j] = win;
+ }
+ }
+
+ *cal_len = (cal[0] >= ports) ? 1 : (grps * grplen);
+ return 0;
+}
+
+static void sparx5_dsm_set_calendar(struct sparx5_private *priv,
+ u32 taxi, u32 *calendar, u32 len)
+{
+ u32 active_calendar;
+ u32 val;
+ u32 i;
+
+ val = spx5_rd(priv, DSM_TAXI_CAL_CFG(taxi));
+ active_calendar = DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(val);
+
+ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(!active_calendar),
+ DSM_TAXI_CAL_CFG_CAL_PGM_SEL,
+ priv, DSM_TAXI_CAL_CFG(taxi));
+
+ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1),
+ DSM_TAXI_CAL_CFG_CAL_PGM_ENA,
+ priv, DSM_TAXI_CAL_CFG(taxi));
+
+ for (i = 0; i < len; i++) {
+ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(i),
+ DSM_TAXI_CAL_CFG_CAL_IDX,
+ priv, DSM_TAXI_CAL_CFG(taxi));
+
+ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(calendar[i]),
+ DSM_TAXI_CAL_CFG_CAL_PGM_VAL,
+ priv, DSM_TAXI_CAL_CFG(taxi));
+ }
+
+ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0),
+ DSM_TAXI_CAL_CFG_CAL_PGM_ENA,
+ priv, DSM_TAXI_CAL_CFG(taxi));
+
+ val = spx5_rd(priv, DSM_TAXI_CAL_CFG(taxi));
+ val = DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(val);
+ if (val != len - 1) {
+ printf("Calendar length is not correct (%d) %d\n", val, len);
+ }
+
+ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(1),
+ DSM_TAXI_CAL_CFG_CAL_SWITCH,
+ priv, DSM_TAXI_CAL_CFG(taxi));
+}
+
+static void sparx5_lan969x_cal_cfg(struct sparx5_private *priv)
+{
+ u32 taxi_speeds[DSM_CAL_MAX_DEVS_PER_TAXI] = {};
+ u32 taxi_ports[DSM_CAL_MAX_DEVS_PER_TAXI] = {0};
+ u32 calendar[DSM_CAL_LEN], taxi;
+ u32 freq_mhz = 328;
+ u32 *dev_speeds;
+ u32 cal_len, p;
+
+ dev_speeds = devm_kzalloc(priv->dev,
+ priv->data->num_ports * sizeof(u32),
+ GFP_KERNEL);
+ if (!dev_speeds)
+ return;
+
+ for (p = 0; p < priv->data->num_ports; p++) {
+ dev_speeds[p] = 1000;
+ }
+
+ for (taxi = 0; taxi < DSM_CAL_TAXIS; taxi++) {
+ sparx5_taxi2ports(taxi, taxi_ports);
+ for (p = 0; p < DSM_CAL_MAX_DEVS_PER_TAXI; p++) {
+ if (taxi_ports[p] < priv->data->num_ports) {
+ taxi_speeds[p] = dev_speeds[taxi_ports[p]];
+ } else {
+ break;
+ }
+ }
+ sparx5_dsm_calc_calendar(taxi_speeds, p, freq_mhz,
+ calendar, &cal_len);
+ sparx5_dsm_set_calendar(priv, taxi, calendar, cal_len);
+ }
+
+ devm_kfree(priv->dev, dev_speeds);
+}
+
+static void sparx5_switch_config(struct sparx5_private *priv)
+{
+ int i;
+
+ /* Halt the calendar while changing it */
+ spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10),
+ QSYS_CAL_CTRL_CAL_MODE,
+ priv, QSYS_CAL_CTRL);
+
+ for (i = 0; i < priv->data->num_cal_auto; i++)
+ /* All ports to '001' - 1Gb/s */
+ spx5_wr(0x09249249, priv, QSYS_CAL_AUTO(i));
+
+ /* Enable Auto mode */
+ spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(8),
+ QSYS_CAL_CTRL_CAL_MODE,
+ priv, QSYS_CAL_CTRL);
+
+ if (priv->data->target == LAN969X_TARGET) {
+ sparx5_lan969x_cal_cfg(priv);
+
+ spx5_wr(0x18624dd2, priv, PTP_CLK_PER_CFG(0, 1));
+ spx5_rmw(PTP_PTP_DOM_CFG_PTP_ENA_SET(1),
+ PTP_PTP_DOM_CFG_PTP_ENA,
+ priv, PTP_PTP_DOM_CFG);
+ }
+
+ /* Configure NPI port */
+ switch (priv->ports[priv->data->npi_port].mac_type) {
+ case IF_SGMII:
+ if (priv->data->target == SPARX5_TARGET) {
+ spx5_rmw(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(1),
+ PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE,
+ priv, PORT_CONF_DEV5G_MODES);
+ }
+ break;
+ case IF_RGMII:
+ case IF_SGMII_CISCO:
+ /* Nothing to do here */
+ break;
+ default:
+ spx5_rmw(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(0),
+ PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE,
+ priv, PORT_CONF_DEV5G_MODES);
+ break;
+ }
+
+ /* Enable all 5G, 10G and 25G ports to behave as 2.5G port */
+ if (priv->data->target == SPARX5_TARGET) {
+ spx5_wr(0x1fff, priv, PORT_CONF_DEV5G_MODES);
+ spx5_wr(0xfff, priv, PORT_CONF_DEV10G_MODES);
+ spx5_wr(0xff, priv, PORT_CONF_DEV25G_MODES);
+ }
+
+ /* As we currently support speeds of 1G or less, then it is OK to set
+ * all the ports that we support lower speeds than 2.5G.
+ */
+ if (priv->data->target == LAN969X_TARGET) {
+ spx5_wr(0xf117001, priv, PORT_CONF_DEV10G_MODES);
+ spx5_wr(0x222200, priv, PORT_CONF_DEV5G_MODES);
+ }
+
+ for (i = 0; i < priv->data->num_ports; i++) {
+ struct sparx5_phy_port *p = &priv->ports[i];
+
+ if (p->active) {
+ /* Enable 10G shadow interfaces */
+ spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1),
+ DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA,
+ priv, DSM_DEV_TX_STOP_WM_CFG(i));
+ }
+
+ if (p->mac_type == IF_QSGMII) {
+ /* Enable the QSGMII interface */
+ u32 val = spx5_rd(priv, PORT_CONF_QSGMII_ENA);
+ val |= BIT(i / 4);
+ spx5_wr(val, priv, PORT_CONF_QSGMII_ENA);
+
+ /* Must take the PCS out of reset for all 4 QSGMII instances,
+ */
+ for (u32 cnt = 0; cnt < 4; ++cnt) {
+ u32 base = (i / 4) * 4;
+ spx5_rmw(DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(0),
+ DEV2G5_DEV_RST_CTRL_PCS_TX_RST,
+ priv, DEV2G5_DEV_RST_CTRL(base + cnt));
+ }
+
+ if (priv->data->target == SPARX5_TARGET) {
+ if (i < 12)
+ spx5_rmw(BIT(i), BIT(i),
+ priv, PORT_CONF_DEV5G_MODES);
+ if (i >= 12 && i <= 15)
+ spx5_rmw(BIT(i - 12), BIT(i - 12),
+ priv, PORT_CONF_DEV10G_MODES);
+
+ if ((i / 4 % 2) == 0)
+ /* Affects d0-d3,d8-d11..d40-d43 */
+ spx5_wr(0x332, priv, PORT_CONF_USGMII_CFG(i / 8));
+ }
+ }
+ }
+
+ /* BCAST/CPU pgid */
+ if (priv->data->target == SPARX5_TARGET) {
+ spx5_wr(0xffffffff, priv, ANA_AC_PGID_CFG(PGID_BROADCAST(priv)));
+ spx5_wr(0xffffffff, priv, ANA_AC_PGID_CFG1(PGID_BROADCAST(priv)));
+ spx5_wr(0x00000001, priv, ANA_AC_PGID_CFG2(PGID_BROADCAST(priv)));
+ spx5_wr(0x00000000, priv, ANA_AC_PGID_CFG(PGID_HOST(priv)));
+ spx5_wr(0x00000000, priv, ANA_AC_PGID_CFG1(PGID_HOST(priv)));
+ spx5_wr(0x00000000, priv, ANA_AC_PGID_CFG2(PGID_HOST(priv)));
+ }
+
+ if (priv->data->target == LAN969X_TARGET) {
+ spx5_wr(0xffffffff, priv, ANA_AC_PGID_CFG(PGID_BROADCAST(priv)));
+ spx5_wr(0x00000000, priv, ANA_AC_PGID_CFG(PGID_HOST(priv)));
+ }
+
+ /* Disable port-to-port by switching
+ * Put front ports in "port isolation modes" - i.e. they can't send
+ * to other ports - via the PGID sorce masks.
+ */
+ for (i = 0; i < priv->data->num_ports; i++) {
+ if (priv->data->target == SPARX5_TARGET) {
+ spx5_wr(0, priv, ANA_AC_SRC_CFG(i));
+ spx5_wr(0, priv, ANA_AC_SRC_CFG1(i));
+ spx5_wr(0, priv, ANA_AC_SRC_CFG2(i));
+ }
+
+ if (priv->data->target == LAN969X_TARGET) {
+ spx5_wr(0, priv, ANA_AC_SRC_CFG(i));
+ }
+ }
+
+ spx5_wr(priv->data->cpu_port << 5, priv, XQS_STAT_CFG);
+
+ /* VLAN aware CPU port */
+ spx5_wr(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(1) |
+ ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(1) |
+ ANA_CL_VLAN_CTRL_PORT_VID_SET(MAC_VID),
+ priv, ANA_CL_VLAN_CTRL(priv->data->cpu_port));
+
+ /* Map PVID = FID, DISABLE LEARNING */
+ spx5_wr(ANA_L3_VLAN_CFG_VLAN_FID_SET(MAC_VID) |
+ ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(1),
+ priv, ANA_L3_VLAN_CFG(MAC_VID));
+
+ /* Enable VLANs */
+ spx5_wr(ANA_L3_VLAN_CTRL_VLAN_ENA_SET(1),
+ priv, ANA_L3_VLAN_CTRL);
+
+ /* Enable switch-core and queue system */
+ spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1),
+ priv, HSCH_RESET_CFG);
+
+ /* Flush queues */
+ mscc_flush(priv->regs[TARGET_QS], sparx5_regs_qs);
+}
+
+static void sparx5_cpu_capture_setup(struct sparx5_private *priv)
+{
+ /* ASM CPU port: No preamble/IFH, enable padding */
+ spx5_wr(ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) |
+ ASM_PORT_CFG_PAD_ENA_SET(1) |
+ ASM_PORT_CFG_INJ_FORMAT_CFG_SET(CONFIG_IFH_FMT_NONE),
+ priv, ASM_PORT_CFG(priv->data->cpu_port));
+
+ /* Set Manual injection via DEVCPU_QS registers for CPU queue 0 */
+ spx5_wr(QS_INJ_GRP_CFG_MODE_SET(1) |
+ QS_INJ_GRP_CFG_BYTE_SWAP_SET(1),
+ priv, QS_INJ_GRP_CFG(0));
+
+ /* Set Manual extraction via DEVCPU_QS registers for CPU queue 0 */
+ spx5_wr(QS_XTR_GRP_CFG_MODE_SET(1) |
+ QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(1) |
+ QS_XTR_GRP_CFG_BYTE_SWAP_SET(1),
+ priv, QS_XTR_GRP_CFG(0));
+
+ /* Enable CPU port for any frame transfer */
+ spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1),
+ QFWD_SWITCH_PORT_MODE_PORT_ENA,
+ priv, QFWD_SWITCH_PORT_MODE(priv->data->cpu_port));
+
+ /* Recalc injected frame FCS */
+ spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1),
+ ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA,
+ priv, ANA_CL_FILTER_CTRL(priv->data->cpu_port));
+
+ /* Send a copy to CPU when found as forwarding entry */
+ spx5_rmw(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(1),
+ ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA,
+ priv, ANA_L2_FWD_CFG);
+}
+
+static void sparx5_port_sgmii_init(struct sparx5_private *priv, int port)
+{
+ sparx5_serdes_port_init(priv->ports[port].serdes_phy,
+ priv->ports[port].mac_type);
+
+ /* Enable PCS */
+ spx5_wr(DEV2G5_PCS1G_CFG_PCS_ENA_SET(1),
+ priv, DEV2G5_PCS1G_CFG(port));
+
+ /* Disable Signal Detect */
+ spx5_wr(0, priv, DEV2G5_USXGMII_PCS_SD_CFG(port));
+
+ /* Enable MAC RX and TX */
+ spx5_wr(DEV2G5_MAC_ENA_CFG_TX_ENA_SET(1) |
+ DEV2G5_MAC_ENA_CFG_RX_ENA_SET(1),
+ priv, DEV2G5_MAC_ENA_CFG(port));
+
+ /* Enable sgmii_mode_ena */
+ spx5_wr(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(1),
+ priv, DEV2G5_PCS1G_MODE_CFG(port));
+
+ if (priv->ports[port].mac_type == IF_SGMII ||
+ priv->ports[port].mac_type == IF_QSGMII) {
+ /*
+ * Clear sw_resolve_ena(bit 0) and set adv_ability to
+ * something meaningful just in case
+ */
+ spx5_wr(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(0x20),
+ priv, DEV2G5_PCS1G_ANEG_CFG(port));
+ } else {
+ /* IF_SGMII_CISCO */
+ spx5_wr(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(0x0001) |
+ DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(1) |
+ DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(1) |
+ DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(1),
+ priv, DEV2G5_PCS1G_ANEG_CFG(port));
+ }
+
+ /* Set MAC IFG Gaps */
+ spx5_wr(DEV2G5_MAC_IFG_CFG_TX_IFG_SET(4) |
+ DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(5) |
+ DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(1),
+ priv, DEV2G5_MAC_IFG_CFG(port));
+
+ /* Set link speed and release all resets but USX */
+ spx5_wr(DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(2) |
+ DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(1) |
+ DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(1),
+ priv, DEV2G5_DEV_RST_CTRL(port));
+}
+
+static void sparx5_port_rgmii_init(struct sparx5_private *priv, int port)
+{
+ /* This function is called only on lan969x, and the RGMII ports are only
+ * on the D28 and D29. They map in the DEVRGMII
+ */
+ int rgmii_index = port - 28;
+ struct phy_device *phydev = priv->ports[port].phy;
+ int spd = phydev->speed;
+ int tx_clk_freq;
+ u32 clk_spd;
+
+ clk_spd = spd == SPEED_10 ? 0 : spd == SPEED_100 ? 1 : 2;
+ tx_clk_freq = (spd == SPEED_10 ? SPX5_RGMII_TX_CLK_2M5MHZ :
+ spd == SPEED_100 ? SPX5_RGMII_TX_CLK_25MHZ :
+ SPX5_RGMII_TX_CLK_125MHZ);
+
+ /* Enable the RGMII0 on the GPIOs */
+ spx5_wr(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(1),
+ priv, HSIO_WRAP_XMII_CFG(!rgmii_index));
+
+ /* Take the RGMII out of reset and set speed to 1G */
+ spx5_wr(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(tx_clk_freq),
+ priv, HSIO_WRAP_RGMII_CFG(rgmii_index));
+
+ /* Enable the RGMII delays on the MAC both on the RX and TX.
+ * The signal is shft by 90 degress
+ */
+ spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) |
+ HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) |
+ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(0) |
+ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(3),
+ HSIO_WRAP_DLL_CFG_DLL_ENA |
+ HSIO_WRAP_DLL_CFG_DLL_RST |
+ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA |
+ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL,
+ priv, HSIO_WRAP_DLL_CFG(rgmii_index, 0));
+
+ spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) |
+ HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) |
+ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(1) |
+ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(3),
+ HSIO_WRAP_DLL_CFG_DLL_ENA |
+ HSIO_WRAP_DLL_CFG_DLL_RST |
+ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA |
+ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL,
+ priv, HSIO_WRAP_DLL_CFG(rgmii_index, 1));
+
+ /* Configure the port now */
+ spx5_wr(DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(1) |
+ DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(1),
+ priv, DEVRGMII_MAC_ENA_CFG(port));
+
+ spx5_wr(DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(4) |
+ DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(5) |
+ DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(1),
+ priv, DEVRGMII_MAC_IFG_CFG(port));
+
+ spx5_wr(DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(clk_spd),
+ priv, DEVRGMII_DEV_RST_CTRL(port));
+}
+
+static void sparx5_port_init(struct sparx5_private *priv, int port)
+{
+ switch (priv->ports[port].mac_type) {
+ case IF_SGMII:
+ case IF_QSGMII:
+ case IF_SGMII_CISCO:
+ sparx5_port_sgmii_init(priv, port);
+ break;
+ case IF_RGMII:
+ sparx5_port_rgmii_init(priv, port);
+ break;
+ default:
+ printf("Unknown interface type: %d\n",
+ priv->ports[port].mac_type);
+ return;
+ }
+
+ /* Make VLAN aware for CPU traffic */
+ spx5_wr(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(1) |
+ ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(1) |
+ ANA_CL_VLAN_CTRL_PORT_VID_SET(MAC_VID),
+ priv, ANA_CL_VLAN_CTRL(port));
+
+ /* Enable CPU port for any frame transfer */
+ spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1),
+ QFWD_SWITCH_PORT_MODE_PORT_ENA,
+ priv, QFWD_SWITCH_PORT_MODE(port));
+}
+
+static inline int sparx5_vlant_wait_for_completion(struct sparx5_private *priv)
+{
+ if (wait_for_bit_le32(spx5_offset(priv, LRN_COMMON_ACCESS_CTRL),
+ LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT,
+ false, 2000, false))
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static void mac_table_write_entry(struct sparx5_private *priv,
+ const unsigned char *mac,
+ u16 vid)
+{
+ u32 macl = 0, mach = 0;
+
+ /*
+ * Set the MAC address to handle and the vlan associated in a format
+ * understood by the hardware.
+ */
+ mach |= vid << 16;
+ mach |= ((u32)mac[0]) << 8;
+ mach |= ((u32)mac[1]) << 0;
+ macl |= ((u32)mac[2]) << 24;
+ macl |= ((u32)mac[3]) << 16;
+ macl |= ((u32)mac[4]) << 8;
+ macl |= ((u32)mac[5]) << 0;
+
+ spx5_wr(mach, priv, LRN_MAC_ACCESS_CFG_0);
+ spx5_wr(macl, priv, LRN_MAC_ACCESS_CFG_1);
+}
+
+static int sparx5_mac_table_add(struct sparx5_private *priv,
+ const unsigned char *mac, int pgid)
+{
+ mac_table_write_entry(priv, mac, MAC_VID);
+
+ spx5_wr(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(pgid - priv->data->num_ports) |
+ LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(0x3) |
+ LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(1) |
+ LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(0) |
+ LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(1) |
+ LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(1),
+ priv, LRN_MAC_ACCESS_CFG_2);
+
+ spx5_wr(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(1),
+ priv, LRN_COMMON_ACCESS_CTRL);
+
+ return sparx5_vlant_wait_for_completion(priv);
+}
+
+static int sparx5_mac_table_getnext(struct sparx5_private *priv,
+ unsigned char *mac,
+ int *addr,
+ u32 *pvid,
+ u32 *cfg0p,
+ u32 *cfg1p,
+ u32 *cfg2p)
+{
+ int ret;
+
+ mac_table_write_entry(priv, mac, *pvid);
+
+ spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(1) |
+ LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(1),
+ priv, LRN_SCAN_NEXT_CFG);
+
+ spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(6) |
+ LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(1),
+ priv, LRN_COMMON_ACCESS_CTRL);
+
+ ret = sparx5_vlant_wait_for_completion(priv);
+
+ if (ret == 0) {
+ u32 cfg0, cfg1, cfg2;
+ cfg2 = spx5_rd(priv, LRN_MAC_ACCESS_CFG_2);
+ if (cfg2 & LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD) {
+ cfg0 = spx5_rd(priv, LRN_MAC_ACCESS_CFG_0);
+ cfg1 = spx5_rd(priv, LRN_MAC_ACCESS_CFG_1);
+ mac[0] = ((cfg0 >> 8) & 0xff);
+ mac[1] = ((cfg0 >> 0) & 0xff);
+ mac[2] = ((cfg1 >> 24) & 0xff);
+ mac[3] = ((cfg1 >> 16) & 0xff);
+ mac[4] = ((cfg1 >> 8) & 0xff);
+ mac[5] = ((cfg1 >> 0) & 0xff);
+ *addr = LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR & cfg2;
+ *pvid = cfg0 >> 16;
+ *cfg0p = cfg0;
+ *cfg1p = cfg1;
+ *cfg2p = cfg2;
+ } else {
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static int sparx5_initialize(struct sparx5_private *priv)
+{
+ int ret, i;
+
+ /* Initialize switch memories, enable core */
+ ret = sparx5_switch_init(priv);
+ if (ret)
+ return ret;
+
+ board_init();
+ sparx5_switch_config(priv);
+
+ for (i = 0; i < priv->data->num_ports; i++)
+ if (priv->ports[i].active)
+ sparx5_port_init(priv, i);
+
+ sparx5_cpu_capture_setup(priv);
+
+ return 0;
+}
+
+static bool sparx5_port_has_link(struct sparx5_private *priv, int port)
+{
+ u32 mask, val;
+
+ if (priv->ports[port].mac_type == IF_RGMII)
+ return priv->ports[port].phy->link;
+
+ if (priv->ports[port].mdio_dev) {
+ val = spx5_rd(priv, DEV2G5_PCS1G_LINK_STATUS(port));
+ mask = DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS;
+ } else {
+ val = spx5_rd(priv, DEV2G5_PCS1G_ANEG_STATUS(port));
+ mask = DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE;
+ }
+
+ return !!(val & mask);
+}
+
+static int sparx5_start(struct udevice *dev)
+{
+ const u8 mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+ struct sparx5_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ int i, ret, phy_ok = 0, ret_err = 0;
+
+ /* Set MAC address tables entries for CPU redirection */
+ ret = sparx5_mac_table_add(priv, mac, PGID_BROADCAST(priv));
+ if (ret)
+ return ret;
+
+ ret = sparx5_mac_table_add(priv, pdata->enetaddr, PGID_HOST(priv));
+ if (ret)
+ return ret;
+
+ for (i = 0; i < priv->data->num_ports; i++) {
+ struct phy_device *phy = priv->ports[i].phy;
+
+ if (!priv->ports[i].active || !phy)
+ continue;
+
+ /* Start up the PHY */
+ phy_config(phy);
+ ret = phy_startup(phy);
+ if (ret) {
+ printf("Could not initialize PHY %s (port %d)\n",
+ phy->dev->name, i);
+ ret_err = ret;
+ continue; /* try all phys */
+ } else {
+ phy_ok = 1;
+ if (i == priv->data->npi_port)
+ printf("NPI Port: ");
+ else
+ printf("Port %3d: ", i);
+
+ printf("%s (internal)\n", sparx5_port_has_link(priv, i) ? "Up" : "Down");
+ }
+
+ sparx5_port_init(priv, i);
+ }
+
+ return phy_ok ? 0 : ret_err;
+}
+
+static void sparx5_stop(struct udevice *dev)
+{
+ struct sparx5_private *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < priv->data->num_ports; i++) {
+ struct phy_device *phy = priv->ports[i].phy;
+
+ if (phy)
+ phy_shutdown(phy);
+ }
+}
+
+static int sparx5_send(struct udevice *dev, void *packet, int length)
+{
+ struct sparx5_private *priv = dev_get_priv(dev);
+
+ return mscc_send(priv->regs[TARGET_QS], sparx5_regs_qs,
+ NULL, 0, packet, length);
+}
+
+static int sparx5_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct sparx5_private *priv = dev_get_priv(dev);
+ u32 *rxbuf = (u32 *)net_rx_packets[0];
+ int byte_cnt = 0;
+
+ byte_cnt = mscc_recv(priv->regs[TARGET_QS], sparx5_regs_qs, rxbuf,
+ priv->data->ifh_len, false);
+
+ *packetp = net_rx_packets[0];
+
+ if (byte_cnt > 0) {
+ if (byte_cnt >= ETH_FCS_LEN)
+ byte_cnt -= ETH_FCS_LEN;
+ else
+ byte_cnt = 0; /* Runt? */
+ }
+
+ return byte_cnt;
+}
+
+static int sparx5_probe(struct udevice *dev)
+{
+ u32 serdes_args[SERDES_ARG_MAX];
+ struct sparx5_private *priv;
+ int i;
+ int ret;
+ ofnode eth_node, node, mdio_node;
+ u32 phy_addr;
+ struct udevice *mdio_dev;
+ ofnode phy_node;
+ phy_interface_t mode;
+
+ priv = dev_get_priv(dev);
+ if (!priv)
+ return -EINVAL;
+
+ priv->dev = dev;
+
+ priv->data = (struct mscc_match_data*)dev_get_driver_data(dev);
+ if (!priv->data)
+ return -EINVAL;
+
+ /* Allocate the resources dynamically */
+ priv->regs = devm_kzalloc(dev,
+ priv->data->num_regs * sizeof(void __iomem *),
+ GFP_KERNEL);
+ if (!priv->regs)
+ return -ENOMEM;
+
+ priv->ports = devm_kzalloc(dev,
+ priv->data->num_ports * sizeof(struct sparx5_phy_port),
+ GFP_KERNEL);
+ if (!priv->ports)
+ return -ENOMEM;
+
+ /* Get registers and map them to the private structure */
+ for (i = 0; i < priv->data->num_regs; i++) {
+ priv->regs[i] = dev_remap_addr_name(dev,
+ priv->data->reg_names[i]);
+ if (!priv->regs[i]) {
+ printf("Error can't get regs base addresses for %s\n",
+ priv->data->reg_names[i]);
+ return -ENOMEM;
+ }
+ }
+
+ priv->serdes = sparx5_serdes_probe(dev);
+ if (IS_ERR(priv->serdes))
+ return PTR_ERR(priv->serdes);
+
+ /* iterate all the ports and find out on which bus they are */
+ i = 0;
+ eth_node = dev_read_first_subnode(dev);
+ for (node = ofnode_first_subnode(eth_node);
+ ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ ret = ofnode_read_u32(node, "reg", &i);
+ if (ret)
+ return ret;
+
+ mdio_dev = NULL;
+ phy_node = ofnode_get_phy_node(node);
+
+ /* Do we have a PHY to worry about? */
+ if (ofnode_valid(phy_node)) {
+ /* Get phy address on mdio bus */
+ ret = ofnode_read_u32(phy_node, "reg", &phy_addr);
+ if (ret)
+ return ret;
+
+ /* Get mdio node */
+ mdio_node = ofnode_get_parent(phy_node);
+
+ ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio_node, &mdio_dev);
+ if (ret) {
+ printf("%s: Cannot get MDIO device: %d\n", __FUNCTION__, ret);
+ return ret;
+ }
+
+ mode = ofnode_read_phy_mode(node);
+ } else {
+ mdio_dev = NULL;
+ phy_addr = -1;
+ mode = PHY_INTERFACE_MODE_NA;
+ }
+
+ priv->ports[i].active = true;
+ priv->ports[i].phy_addr = phy_addr;
+ priv->ports[i].mdio_dev = mdio_dev;
+ priv->ports[i].mode = mode;
+
+ /* Get serdes info */
+ ret = ofnode_read_u32_array(node, "phys", serdes_args, SERDES_ARG_MAX);
+ if (ret) {
+ ret = ofnode_read_u32_array(node, "phys", serdes_args, 1);
+ if (ret) {
+ printf("%s: Port %d no 'phys' properties?\n",
+ __func__, i);
+ return -EINVAL;
+ } else {
+ priv->ports[i].mac_type = serdes_args[SERDES_ARG_MAC_TYPE];
+ }
+ } else {
+ priv->ports[i].mac_type = serdes_args[SERDES_ARG_MAC_TYPE];
+ priv->ports[i].serdes_type = serdes_args[SERDES_ARG_SERDES];
+ priv->ports[i].serdes_index = serdes_args[SERDES_ARG_SER_IDX];
+ priv->ports[i].serdes_phy = sparx5_serdes_phy_get(priv->serdes,
+ priv->ports[i].serdes_type,
+ priv->ports[i].serdes_index);
+ }
+
+ debug("%s: Add port %d bus %s addr %u serdes %s serdes# %d\n",
+ __func__, i, priv->ports[i].mdio_dev ? priv->ports[i].mdio_dev->name : "(none)", phy_addr,
+ priv->ports[i].serdes_type == FA_SERDES_TYPE_6G ? "6g" : "10g",
+ priv->ports[i].serdes_index);
+ }
+
+ for (i = 0; i < priv->data->num_ports; i++) {
+ struct phy_device *phy;
+
+ if (!priv->ports[i].mdio_dev)
+ continue;
+
+ phy = dm_mdio_phy_connect(priv->ports[i].mdio_dev,
+ priv->ports[i].phy_addr, dev,
+ priv->ports[i].mode);
+ if (phy)
+ priv->ports[i].phy = phy;
+ }
+
+ sparx5_initialize(priv);
+
+ dev_priv = priv;
+
+ return 0;
+}
+
+static int sparx5_remove(struct udevice *dev)
+{
+ struct sparx5_private *priv = dev_get_priv(dev);
+
+ /* Make sure the core is PROTECTED from reset */
+ spx5_rmw(CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE,
+ CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE,
+ priv, CPU_RESET_PROT_STAT);
+
+ /* Reset switch core */
+ spx5_wr(GCB_SOFT_RST_SOFT_CHIP_RST_SET(1),
+ priv, GCB_SOFT_RST);
+
+ dev_priv = NULL;
+
+ return 0;
+}
+
+static const struct eth_ops sparx5_ops = {
+ .start = sparx5_start,
+ .stop = sparx5_stop,
+ .send = sparx5_send,
+ .recv = sparx5_recv,
+};
+
+static const struct udevice_id mscc_sparx5_ids[] = {
+ {.compatible = "mscc,vsc7558-switch", .data = (ulong)&mscc_sparx5_data },
+ {.compatible = "microchip,lan9691-switch", .data = (ulong)&mscc_lan969x_data },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(sparx5) = {
+ .name = "sparx5-switch",
+ .id = UCLASS_ETH,
+ .of_match = mscc_sparx5_ids,
+ .probe = sparx5_probe,
+ .remove = sparx5_remove,
+ .ops = &sparx5_ops,
+ .priv_auto = sizeof(struct sparx5_private),
+ .plat_auto = sizeof(struct eth_pdata),
+};
+
+static int do_switch(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct sparx5_private *priv = dev_priv;
+ u8 mac[ETH_ALEN];
+ int i, addr, cnt = 0;
+ u32 cfg0, cfg1, cfg2;
+
+ if (priv) {
+ memset(mac, 0, sizeof(mac));
+ u32 vid = 0;
+ while (sparx5_mac_table_getnext(priv, mac, &addr, &vid, &cfg0, &cfg1, &cfg2) == 0) {
+ printf("%4d: %02x:%02x:%02x:%02x:%02x:%02x %d:%d 0x%08x 0x%08x 0x%08x\n",
+ cnt++,
+ mac[0], mac[1], mac[2],
+ mac[3], mac[4], mac[5], vid, addr, cfg0, cfg1, cfg2);
+ }
+ for (i = 0; i < priv->data->num_ports; i++)
+ if (priv->ports[i].active) {
+ u32 mask, val;
+ if (priv->ports[i].mdio_dev) {
+ val = spx5_rd(priv, DEV2G5_PCS1G_LINK_STATUS(i));
+ mask = DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS;
+ } else {
+ val = spx5_rd(priv, DEV2G5_PCS1G_ANEG_STATUS(i));
+ mask = DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE;
+ }
+ printf("%2d: Link %s (0x%08x)\n", i,
+ val & mask ? "Up" : "--",
+ val);
+ }
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ switch, 3, 1, do_switch,
+ "display switch status",
+ ""
+);
diff --git a/drivers/net/mscc_eswitch/sparx5_switch.h b/drivers/net/mscc_eswitch/sparx5_switch.h
new file mode 100644
index 00000000000..ff6a729e484
--- /dev/null
+++ b/drivers/net/mscc_eswitch/sparx5_switch.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ * Microchip Sparx5 SerDes driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc.
+ */
+
+#ifndef _SPARX5_SWITCH_H_
+#define _SPARX5_SWITCH_H_
+
+#include "sparx5_serdes.h"
+
+#include "mscc_xfer.h"
+#include "mscc_miim.h"
+
+enum {
+ SPARX5_TARGET,
+ LAN969X_TARGET,
+};
+
+struct sparx5_regs {
+ const unsigned int *reggrp_addr;
+ const unsigned int *reggrp_cnt;
+ const unsigned int *reggrp_size;
+ const unsigned int *reg_addr;
+ const unsigned int *reg_cnt;
+ const unsigned int *regfield_addr;
+};
+
+struct mscc_match_data {
+ const char * const *reg_names;
+ struct sparx5_regs regs;
+ u8 num_regs;
+ u8 num_ports;
+ u8 num_bus;
+ u8 cpu_port;
+ u8 npi_port;
+ u8 ifh_len;
+ u8 num_cal_auto;
+ u8 target;
+};
+
+struct sparx5_phy_port {
+ bool active;
+ struct udevice *mdio_dev;
+ u8 phy_addr;
+ struct phy_device *phy;
+ phy_interface_t mode;
+ u32 mac_type;
+ u32 serdes_type;
+ u32 serdes_index;
+
+ /* This is the serdes that correspond to the port */
+ struct sparx5_serdes_phy *serdes_phy;
+};
+
+struct sparx5_private {
+ struct mscc_match_data *data;
+
+ void __iomem **regs;
+ struct sparx5_phy_port *ports;
+ struct udevice *dev;
+
+ /* This is a container for the entire serdes, which correspond to
+ * sparx5_serdes_private
+ */
+ void *serdes;
+};
+
+#endif /* _SPARX5_SWITCH_H_ */
diff --git a/include/dt-bindings/mscc/sparx5_data.h b/include/dt-bindings/mscc/sparx5_data.h
new file mode 100644
index 00000000000..aba0d3c4493
--- /dev/null
+++ b/include/dt-bindings/mscc/sparx5_data.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#ifndef _SPARX5_DATA_H_
+#define _SPARX5_DATA_H_
+
+#define FA_SERDES_TYPE_6G 6
+#define FA_SERDES_TYPE_10G 10
+#define FA_SERDES_TYPE_25G 25
+
+/* similar with phy_interface_t */
+#define IF_SGMII 1
+#define IF_SGMII_CISCO 2
+#define IF_QSGMII 3
+#define IF_RGMII 4
+
+#endif
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 13/14] net: phy: add Microchip LAN8841 support
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (10 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 12/14] net: add Microchip SparX-5 and " Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-04-09 10:04 ` Manikandan.M
2026-03-26 11:26 ` [PATCH 14/14] arch: arm: add Microchip LAN969x support Robert Marko
2026-04-25 13:35 ` [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Eugen Hristev
13 siblings, 1 reply; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
Add driver for the Microchip LAN8841 PHY.
It provides fixes for erratas, as well as support for enabling the required
RGMII delays based on the PHY mode.
It is based on the upstream Linux driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/phy/Kconfig | 3 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/microchip.c | 185 ++++++++++++++++++++++++++++++++++++
3 files changed, 189 insertions(+)
create mode 100644 drivers/net/phy/microchip.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 709f1c91eb2..3eaf9d7495f 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -231,6 +231,9 @@ config PHY_MICREL_KSZ8XXX
endif # PHY_MICREL
+config PHY_MICROCHIP
+ bool "Microchip Ethernet PHYs support"
+
config PHY_MOTORCOMM
tristate "Motorcomm PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 83520de7f1f..04e9d61a3c2 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -25,6 +25,7 @@ obj-y += mediatek/
obj-y += airoha/
obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
+obj-$(CONFIG_PHY_MICROCHIP) += microchip.o
obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o
obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
diff --git a/drivers/net/phy/microchip.c b/drivers/net/phy/microchip.c
new file mode 100644
index 00000000000..bc54311ab72
--- /dev/null
+++ b/drivers/net/phy/microchip.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <phy.h>
+#include <linux/bitops.h>
+
+#define PHY_ID_MATCH_MODEL_MASK GENMASK(31, 4)
+#define PHY_ID_LAN8841 0x00221650
+
+#define LAN8841_MMD_COMMON_CTRL_REG 2
+#define LAN8841_RXC_DLL_CTRL 76
+#define LAN8841_TXC_DLL_CTRL 77
+#define LAN8841_DLL_ENABLE_DELAY 0
+
+#define LAN8841_MMD_TIMER_REG 0
+#define LAN8841_MMD0_REGISTER_17 17
+#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
+#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
+#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
+#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
+#define LAN8841_MMD_ANALOG_REG 28
+#define LAN8841_ANALOG_CONTROL_1 1
+#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
+#define LAN8841_ANALOG_CONTROL_10 13
+#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
+#define LAN8841_ANALOG_CONTROL_11 14
+#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
+#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
+#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
+#define LAN8841_BTRX_POWER_DOWN 70
+#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
+#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
+#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
+#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
+#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
+#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
+#define LAN8841_ADC_CHANNEL_MASK 198
+#define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370
+#define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371
+#define LAN8841_PTP_RX_VERSION 374
+#define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434
+#define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435
+#define LAN8841_PTP_TX_VERSION 438
+#define LAN8841_PTP_CMD_CTL 256
+#define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2)
+#define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1)
+#define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0)
+#define LAN8841_PTP_RX_PARSE_CONFIG 368
+#define LAN8841_PTP_TX_PARSE_CONFIG 432
+#define LAN8841_PTP_RX_MODE 381
+#define LAN8841_PTP_INSERT_TS_EN BIT(0)
+#define LAN8841_PTP_INSERT_TS_32BIT BIT(1)
+
+static int lan8841_config_rgmii_delay(struct phy_device *phydev)
+{
+ u16 rxcdll_val, txcdll_val;
+ int ret;
+
+ switch (phydev->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ rxcdll_val = BIT(14);
+ txcdll_val = BIT(14);
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ rxcdll_val = LAN8841_DLL_ENABLE_DELAY;
+ txcdll_val = LAN8841_DLL_ENABLE_DELAY;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ rxcdll_val = LAN8841_DLL_ENABLE_DELAY;
+ txcdll_val = BIT(14);
+ break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ rxcdll_val = BIT(14);
+ txcdll_val = LAN8841_DLL_ENABLE_DELAY;
+ break;
+ default:
+ return 0;
+ }
+
+ ret = phy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_RXC_DLL_CTRL, BIT_MASK(14),
+ rxcdll_val);
+ if (ret < 0)
+ return ret;
+
+ return phy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_TXC_DLL_CTRL, BIT_MASK(14),
+ txcdll_val);
+}
+
+static int lan8841_config_init(struct phy_device *phydev)
+{
+ int ret;
+
+ if (phy_interface_is_rgmii(phydev)) {
+ ret = lan8841_config_rgmii_delay(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Initialize the HW by resetting everything */
+ phy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_PTP_CMD_CTL,
+ LAN8841_PTP_CMD_CTL_PTP_RESET,
+ LAN8841_PTP_CMD_CTL_PTP_RESET);
+
+ phy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_PTP_CMD_CTL,
+ LAN8841_PTP_CMD_CTL_PTP_ENABLE,
+ LAN8841_PTP_CMD_CTL_PTP_ENABLE);
+
+ /* Don't process any frames */
+ phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_PTP_RX_PARSE_CONFIG, 0);
+ phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_PTP_TX_PARSE_CONFIG, 0);
+ phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);
+ phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);
+ phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);
+ phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);
+
+ /* Disable checking for minorVersionPTP field */
+ phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_PTP_RX_VERSION, 0xff00);
+ phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_PTP_TX_VERSION, 0xff00);
+
+ /* 100BT Clause 40 improvement errata */
+ phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
+ LAN8841_ANALOG_CONTROL_1,
+ LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
+ phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
+ LAN8841_ANALOG_CONTROL_10,
+ LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
+
+ /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
+ * Magnetics
+ */
+ ret = phy_read_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
+ LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
+ if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
+ phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
+ LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
+ LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
+ phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
+ LAN8841_BTRX_POWER_DOWN,
+ LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
+ LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
+ LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
+ LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
+ LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
+ LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
+ }
+
+ /* LDO Adjustment errata */
+ phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
+ LAN8841_ANALOG_CONTROL_11,
+ LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
+
+ /* 100BT RGMII latency tuning errata */
+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
+ LAN8841_ADC_CHANNEL_MASK, 0x0);
+ phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
+ LAN8841_MMD0_REGISTER_17,
+ LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
+ LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
+
+ /* Disable Power Down */
+ phy_modify(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_PDOWN, 0);
+
+ return 0;
+}
+
+U_BOOT_PHY_DRIVER(lan8841) = {
+ .name = "Microchip LAN8841",
+ .uid = PHY_ID_LAN8841,
+ .mask = PHY_ID_MATCH_MODEL_MASK,
+ .features = PHY_GBIT_FEATURES,
+ .config = &lan8841_config_init,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 14/14] arch: arm: add Microchip LAN969x support
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (11 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 13/14] net: phy: add Microchip LAN8841 support Robert Marko
@ 2026-03-26 11:26 ` Robert Marko
2026-04-25 13:35 ` [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Eugen Hristev
13 siblings, 0 replies; 18+ messages in thread
From: Robert Marko @ 2026-03-26 11:26 UTC (permalink / raw)
To: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon
Cc: luka.perkov, Robert Marko
Microchip LAN9696x is a Cortex-A53 based switch SoC.
Since Microchip also has LAN966x and SparX-5 families of switch SoC-s
lets add a generic architecture so those could be added in future as
well under the same architecture.
Support is included for the SoC and the EV23X71A board.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
arch/arm/Kconfig | 10 +
arch/arm/Makefile | 1 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/clk-lan9691.h | 24 +
arch/arm/dts/lan9691.dtsi | 545 +++++++++++++
arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi | 18 +
arch/arm/dts/lan9696-ev23x71a.dts | 795 +++++++++++++++++++
arch/arm/dts/lan969x-u-boot.dtsi | 72 ++
arch/arm/mach-microchipsw/Kconfig | 31 +
arch/arm/mach-microchipsw/Makefile | 3 +
arch/arm/mach-microchipsw/include/mach/soc.h | 29 +
arch/arm/mach-microchipsw/lan969x/Makefile | 3 +
arch/arm/mach-microchipsw/lan969x/soc.c | 136 ++++
board/microchip/lan969x/Makefile | 3 +
board/microchip/lan969x/lan969x.c | 115 +++
configs/microchip_ev23x71a_defconfig | 77 ++
include/configs/lan969x.h | 36 +
17 files changed, 1900 insertions(+)
create mode 100644 arch/arm/dts/clk-lan9691.h
create mode 100644 arch/arm/dts/lan9691.dtsi
create mode 100644 arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi
create mode 100644 arch/arm/dts/lan9696-ev23x71a.dts
create mode 100644 arch/arm/dts/lan969x-u-boot.dtsi
create mode 100644 arch/arm/mach-microchipsw/Kconfig
create mode 100644 arch/arm/mach-microchipsw/Makefile
create mode 100644 arch/arm/mach-microchipsw/include/mach/soc.h
create mode 100644 arch/arm/mach-microchipsw/lan969x/Makefile
create mode 100644 arch/arm/mach-microchipsw/lan969x/soc.c
create mode 100644 board/microchip/lan969x/Makefile
create mode 100644 board/microchip/lan969x/lan969x.c
create mode 100644 configs/microchip_ev23x71a_defconfig
create mode 100644 include/configs/lan969x.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cd6a454fd60..ebd9d96452f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -869,6 +869,14 @@ config ARCH_MEDIATEK
Support for the MediaTek SoCs family developed by MediaTek Inc.
Please refer to doc/README.mediatek for more information.
+config ARCH_MICROCHIPSW
+ bool "Microchip switch SoCs"
+ select DM
+ select OF_CONTROL
+ imply CMD_DM
+ help
+ Support for Microchip switch focused SoC-s.
+
config ARCH_MMP
bool "Marvell MMP"
select ARM64
@@ -2400,6 +2408,8 @@ source "arch/arm/mach-nexell/Kconfig"
source "arch/arm/mach-npcm/Kconfig"
+source "arch/arm/mach-microchipsw/Kconfig"
+
source "board/armltd/total_compute/Kconfig"
source "board/armltd/corstone1000/Kconfig"
source "board/bosch/shc/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b36b0742580..2d5e4836b06 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -70,6 +70,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MESON) += meson
+machine-$(CONFIG_ARCH_MICROCHIPSW) += microchipsw
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_NEXELL) += nexell
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 82ad3035308..ec6ba8c5f55 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1210,6 +1210,8 @@ dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb
+dtb-$(CONFIG_ARCH_MICROCHIPSW) += lan9696-ev23x71a.dtb
+
include $(srctree)/scripts/Makefile.dts
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/clk-lan9691.h b/arch/arm/dts/clk-lan9691.h
new file mode 100644
index 00000000000..0f2d7a0f881
--- /dev/null
+++ b/arch/arm/dts/clk-lan9691.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
+
+#ifndef _DTS_CLK_LAN9691_H
+#define _DTS_CLK_LAN9691_H
+
+#define GCK_ID_QSPI0 0
+#define GCK_ID_QSPI2 1
+#define GCK_ID_SDMMC0 2
+#define GCK_ID_SDMMC1 3
+#define GCK_ID_MCAN0 4
+#define GCK_ID_MCAN1 5
+#define GCK_ID_FLEXCOM0 6
+#define GCK_ID_FLEXCOM1 7
+#define GCK_ID_FLEXCOM2 8
+#define GCK_ID_FLEXCOM3 9
+#define GCK_ID_TIMER 10
+#define GCK_ID_USB_REFCLK 11
+
+/* Gate clocks */
+#define GCK_GATE_USB_DRD 12
+#define GCK_GATE_MCRAMC 13
+#define GCK_GATE_HMATRIX 14
+
+#endif
diff --git a/arch/arm/dts/lan9691.dtsi b/arch/arm/dts/lan9691.dtsi
new file mode 100644
index 00000000000..b79923fba00
--- /dev/null
+++ b/arch/arm/dts/lan9691.dtsi
@@ -0,0 +1,545 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mfd/at91-usart.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+#include "clk-lan9691.h"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "Microchip LAN969x";
+ compatible = "microchip,lan9691";
+ interrupt-parent = <&gic>;
+
+ clocks {
+ fx100_clk: fx100-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <320000000>;
+ };
+
+ cpu_clk: cpu-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ ddr_clk: ddr-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ };
+
+ fabric_clk: fabric-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ next-level-cache = <&l2_0>;
+ };
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Secure Phys IRQ */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Non-secure Phys IRQ */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virt IRQ */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hyp IRQ */
+ };
+
+ axi: axi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usb: usb@300000 {
+ compatible = "microchip,lan9691-dwc3", "snps,dwc3";
+ reg = <0x300000 0x80000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks GCK_GATE_USB_DRD>,
+ <&clks GCK_ID_USB_REFCLK>;
+ clock-names = "bus_early", "ref";
+ assigned-clocks = <&clks GCK_ID_USB_REFCLK>;
+ assigned-clock-rates = <60000000>;
+ maximum-speed = "high-speed";
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ otp: otp@e0021000 {
+ compatible = "microchip,lan9691-otpc";
+ reg = <0xe0021000 0x1000>;
+ };
+
+ flx0: flexcom@e0040000 {
+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
+ reg = <0xe0040000 0x100>;
+ ranges = <0x0 0xe0040000 0x800>;
+ clocks = <&clks GCK_ID_FLEXCOM0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usart0: serial@200 {
+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi0: spi@400 {
+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@600 {
+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flx1: flexcom@e0044000 {
+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
+ reg = <0xe0044000 0x100>;
+ ranges = <0x0 0xe0044000 0x800>;
+ clocks = <&clks GCK_ID_FLEXCOM1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usart1: serial@200 {
+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi1: spi@400 {
+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@600 {
+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ trng: rng@e0048000 {
+ compatible = "microchip,lan9691-trng", "atmel,at91sam9g45-trng";
+ reg = <0xe0048000 0x100>;
+ clocks = <&fabric_clk>;
+ status = "disabled";
+ };
+
+ aes: crypto@e004c000 {
+ compatible = "microchip,lan9691-aes", "atmel,at91sam9g46-aes";
+ reg = <0xe004c000 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(12)>,
+ <&dma AT91_XDMAC_DT_PERID(13)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "aes_clk";
+ status = "disabled";
+ };
+
+ flx2: flexcom@e0060000 {
+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
+ reg = <0xe0060000 0x100>;
+ ranges = <0x0 0xe0060000 0x800>;
+ clocks = <&clks GCK_ID_FLEXCOM2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usart2: serial@200 {
+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
+ <&dma AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi2: spi@400 {
+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
+ <&dma AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@600 {
+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
+ <&dma AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flx3: flexcom@e0064000 {
+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
+ reg = <0xe0064000 0x100>;
+ ranges = <0x0 0xe0064000 0x800>;
+ clocks = <&clks GCK_ID_FLEXCOM3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usart3: serial@200 {
+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
+ <&dma AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi3: spi@400 {
+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
+ <&dma AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@600 {
+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
+ <&dma AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ dma: dma-controller@e0068000 {
+ compatible = "microchip,lan9691-dma", "microchip,sama7g5-dma";
+ reg = <0xe0068000 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <16>;
+ #dma-cells = <1>;
+ clocks = <&fabric_clk>;
+ clock-names = "dma_clk";
+ };
+
+ sha: crypto@e006c000 {
+ compatible = "microchip,lan9691-sha", "atmel,at91sam9g46-sha";
+ reg = <0xe006c000 0xec>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(14)>;
+ dma-names = "tx";
+ clocks = <&fabric_clk>;
+ clock-names = "sha_clk";
+ status = "disabled";
+ };
+
+ timer: timer@e008c000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xe008c000 0x400>;
+ clocks = <&fabric_clk>;
+ clock-names = "timer";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ watchdog: watchdog@e0090000 {
+ compatible = "snps,dw-wdt";
+ reg = <0xe0090000 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fabric_clk>;
+ };
+
+ cpu_ctrl: syscon@e00c0000 {
+ compatible = "microchip,lan966x-cpu-syscon", "syscon";
+ reg = <0xe00c0000 0x350>;
+ };
+
+ switch: switch@e00c0000 {
+ compatible = "microchip,lan9691-switch";
+ reg = <0xe00c0000 0x0010000>,
+ <0xe2010000 0x1410000>;
+ reg-names = "cpu", "devices";
+ interrupt-names = "xtr", "fdma", "ptp";
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&reset 0>;
+ reset-names = "switch";
+ status = "disabled";
+ };
+
+ clks: clock-controller@e00c00b4 {
+ compatible = "microchip,lan9691-gck";
+ reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>;
+ #clock-cells = <1>;
+ clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>;
+ clock-names = "cpu", "ddr", "sys";
+ };
+
+ qspi0: spi@e0804000 {
+ compatible = "microchip,lan9691-qspi";
+ reg = <0xe0804000 0x00000100>,
+ <0x20000000 0x08000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>;
+ clock-names = "pclk", "gclk";
+ assigned-clocks = <&clks GCK_ID_QSPI0>;
+ assigned-clock-rates = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sdmmc0: mmc@e0830000 {
+ compatible = "microchip,lan9691-sdhci";
+ reg = <0xe0830000 0x00000300>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks GCK_ID_SDMMC0>, <&clks GCK_ID_SDMMC0>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&clks GCK_ID_SDMMC0>;
+ assigned-clock-rates = <100000000>;
+ status = "disabled";
+ };
+
+ sdmmc1: mmc@e0838000 {
+ compatible = "microchip,lan9691-sdhci";
+ reg = <0xe0838000 0x00000300>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks GCK_ID_SDMMC1>, <&clks GCK_ID_SDMMC1>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&clks GCK_ID_SDMMC1>;
+ assigned-clock-rates = <45000000>;
+ status = "disabled";
+ };
+
+ qspi2: spi@e0834000 {
+ compatible = "microchip,lan9691-qspi";
+ reg = <0xe0834000 0x00000100>,
+ <0x30000000 0x04000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>;
+ clock-names = "pclk", "gclk";
+ assigned-clocks = <&clks GCK_ID_QSPI2>;
+ assigned-clock-rates = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ reset: reset-controller@e201000c {
+ compatible = "microchip,lan9691-switch-reset",
+ "microchip,lan966x-switch-reset";
+ reg = <0xe201000c 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
+ };
+
+ gpio: pinctrl@e20100d4 {
+ compatible = "microchip,lan9691-pinctrl";
+ reg = <0xe20100d4 0xd4>,
+ <0xe2010370 0xa8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 66>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ };
+
+ mdio0: mdio@e20101a8 {
+ compatible = "microchip,lan9691-miim", "mscc,ocelot-miim";
+ reg = <0xe20101a8 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&fx100_clk>;
+ status = "disabled";
+ };
+
+ mdio1: mdio@e20101cc {
+ compatible = "microchip,lan9691-miim", "mscc,ocelot-miim";
+ reg = <0xe20101cc 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&fx100_clk>;
+ status = "disabled";
+ };
+
+ sgpio: gpio@e2010230 {
+ compatible = "microchip,lan9691-sgpio", "microchip,sparx5-sgpio";
+ reg = <0xe2010230 0x118>;
+ clocks = <&fx100_clk>;
+ resets = <&reset 0>;
+ reset-names = "switch";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgpio_in: gpio@0 {
+ compatible = "microchip,lan9691-sgpio-bank",
+ "microchip,sparx5-sgpio-bank";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ sgpio_out: gpio@1 {
+ compatible = "microchip,lan9691-sgpio-bank",
+ "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ };
+ };
+
+ tmon: hwmon@e2020100 {
+ compatible = "microchip,lan9691-temp", "microchip,sparx5-temp";
+ reg = <0xe2020100 0xc>;
+ clocks = <&fx100_clk>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ serdes: serdes@e3410000 {
+ compatible = "microchip,lan9691-serdes";
+ reg = <0xe3410000 0x150000>;
+ #phy-cells = <1>;
+ clocks = <&fabric_clk>;
+ };
+
+ gic: interrupt-controller@e8c11000 {
+ compatible = "arm,gic-400";
+ reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */
+ <0xe8c12000 0x2000>, /* CPU interface GICC_ */
+ <0xe8c14000 0x2000>, /* Virt interface control */
+ <0xe8c16000 0x2000>; /* Virt CPU interface */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
diff --git a/arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi b/arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi
new file mode 100644
index 00000000000..bbbb578cc57
--- /dev/null
+++ b/arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi
@@ -0,0 +1,18 @@
+
+#include <dt-bindings/mscc/sparx5_data.h>
+
+&switch {
+ /delete-node/ ethernet-ports;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port29: port@29 {
+ reg = <29>;
+ phy-handle = <&phy3>;
+ phy-mode = "rgmii-rxid";
+ phys = <IF_RGMII>;
+ };
+ };
+};
diff --git a/arch/arm/dts/lan9696-ev23x71a.dts b/arch/arm/dts/lan9696-ev23x71a.dts
new file mode 100644
index 00000000000..4935b6d7b14
--- /dev/null
+++ b/arch/arm/dts/lan9696-ev23x71a.dts
@@ -0,0 +1,795 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "lan9691.dtsi"
+
+/ {
+ model = "Microchip EV23X71A";
+ compatible = "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9691";
+
+ aliases {
+ serial0 = &usart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 60 GPIO_ACTIVE_LOW>;
+ open-source;
+ priority = <200>;
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c3>;
+ idle-state = <0x8>;
+ mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>,
+ <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>,
+ <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>;
+ settle-time-us = <100>;
+
+ i2c_sfp0: i2c@0 {
+ reg = <0x0>;
+ };
+
+ i2c_sfp1: i2c@1 {
+ reg = <0x1>;
+ };
+
+ i2c_sfp2: i2c@2 {
+ reg = <0x2>;
+ };
+
+ i2c_sfp3: i2c@3 {
+ reg = <0x3>;
+ };
+
+ i2c_poe: i2c@7 {
+ reg = <0x7>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-status {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio 61 GPIO_ACTIVE_LOW>;
+ };
+
+ led-sfp1-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <0>;
+ gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp1-yellow {
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <0>;
+ gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp2-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp2-yellow {
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp3-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp3-yellow {
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp4-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <3>;
+ gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp4-yellow {
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <3>;
+ gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>,
+ <&sgpio_out 1 3 GPIO_ACTIVE_LOW>;
+ };
+
+ sfp0: sfp0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp0>;
+ tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp1: sfp1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp2: sfp2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp3: sfp3 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp3>;
+ tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&gpio {
+ emmc_sd_pins: emmc-sd-pins {
+ /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */
+ pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17",
+ "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21",
+ "GPIO_22", "GPIO_23", "GPIO_24";
+ function = "emmc_sd";
+ };
+
+ fan_pins: fan-pins {
+ pins = "GPIO_25", "GPIO_26";
+ function = "fan";
+ };
+
+ fc0_pins: fc0-pins {
+ pins = "GPIO_3", "GPIO_4";
+ function = "fc";
+ };
+
+ fc2_pins: fc2-pins {
+ pins = "GPIO_64", "GPIO_65", "GPIO_66";
+ function = "fc";
+ };
+
+ fc3_pins: fc3-pins {
+ pins = "GPIO_55", "GPIO_56";
+ function = "fc";
+ };
+
+ mdio_irq_pins: mdio-irq-pins {
+ pins = "GPIO_11";
+ function = "miim_irq";
+ };
+
+ mdio_pins: mdio-pins {
+ pins = "GPIO_9", "GPIO_10";
+ function = "miim";
+ };
+
+ ptp_ext_pins: ptp-ext-pins {
+ pins = "GPIO_59";
+ function = "ptpsync_5";
+ };
+
+ ptp_out_pins: ptp-out-pins {
+ pins = "GPIO_58";
+ function = "ptpsync_4";
+ };
+
+ sgpio_pins: sgpio-pins {
+ /* SCK, D0, D1, LD */
+ pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8";
+ function = "sgpio_a";
+ };
+
+ usb_over_pins: usb-over-pins {
+ pins = "GPIO_13";
+ function = "usb_over_detect";
+ };
+
+ usb_power_pins: usb-power-pins {
+ pins = "GPIO_1";
+ function = "usb_power";
+ };
+
+ usb_rst_pins: usb-rst-pins {
+ pins = "GPIO_12";
+ function = "usb2phy_rst";
+ };
+
+ usb_ulpi_pins: usb-ulpi-pins {
+ pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33",
+ "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37",
+ "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41";
+ function = "usb_ulpi";
+ };
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+};
+
+&flx2 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+ status = "okay";
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-0 = <&fc3_pins>;
+ pinctrl-names = "default";
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ i2c-sda-hold-time-ns = <1500>;
+ status = "okay";
+};
+
+&mdio0 {
+ pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ phy3: phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy4: phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy5: phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <5>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy6: phy@6 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <6>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy7: phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy8: phy@8 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <8>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy9: phy@9 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <9>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy10: phy@10 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <10>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy11: phy@11 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <11>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy12: phy@12 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <12>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy13: phy@13 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <13>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy14: phy@14 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <14>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy15: phy@15 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <15>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy16: phy@16 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <16>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy17: phy@17 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <17>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy18: phy@18 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <18>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy19: phy@19 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <19>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy20: phy@20 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <20>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy21: phy@21 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <21>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy22: phy@22 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <22>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy23: phy@23 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <23>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy24: phy@24 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <24>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy25: phy@25 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <25>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy26: phy@26 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <26>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy27: phy@27 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <27>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+};
+
+&otp {
+ nvmem-layout {
+ compatible = "microchip,otp-layout";
+
+ base_mac_address: base-mac-address {
+ #nvmem-cell-cells = <1>;
+ };
+ };
+};
+
+&qspi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+ };
+};
+
+&sdmmc0 {
+ pinctrl-0 = <&emmc_sd_pins>;
+ pinctrl-names = "default";
+ max-frequency = <100000000>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ disable-wp;
+ status = "okay";
+};
+
+&serdes {
+ status = "okay";
+};
+
+&sgpio {
+ pinctrl-0 = <&sgpio_pins>;
+ pinctrl-names = "default";
+ microchip,sgpio-port-ranges = <0 1>, <6 9>;
+ status = "okay";
+
+ gpio@0 {
+ ngpios = <128>;
+ };
+ gpio@1 {
+ ngpios = <128>;
+ };
+};
+
+&spi2 {
+ pinctrl-0 = <&fc2_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&switch {
+ pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>;
+ pinctrl-names = "default";
+ nvmem-cells = <&base_mac_address 0>;
+ nvmem-cell-names = "mac-address";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ phy-handle = <&phy4>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 0>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port1: port@1 {
+ reg = <1>;
+ phy-handle = <&phy5>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 0>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port2: port@2 {
+ reg = <2>;
+ phy-handle = <&phy6>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 0>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port3: port@3 {
+ reg = <3>;
+ phy-handle = <&phy7>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 0>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port4: port@4 {
+ reg = <4>;
+ phy-handle = <&phy8>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 1>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port5: port@5 {
+ reg = <5>;
+ phy-handle = <&phy9>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 1>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port6: port@6 {
+ reg = <6>;
+ phy-handle = <&phy10>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 1>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port7: port@7 {
+ reg = <7>;
+ phy-handle = <&phy11>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 1>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port8: port@8 {
+ reg = <8>;
+ phy-handle = <&phy12>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 2>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port9: port@9 {
+ reg = <9>;
+ phy-handle = <&phy13>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 2>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port10: port@10 {
+ reg = <10>;
+ phy-handle = <&phy14>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 2>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port11: port@11 {
+ reg = <11>;
+ phy-handle = <&phy15>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 2>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port12: port@12 {
+ reg = <12>;
+ phy-handle = <&phy16>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 3>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port13: port@13 {
+ reg = <13>;
+ phy-handle = <&phy17>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 3>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port14: port@14 {
+ reg = <14>;
+ phy-handle = <&phy18>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 3>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port15: port@15 {
+ reg = <15>;
+ phy-handle = <&phy19>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 3>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port16: port@16 {
+ reg = <16>;
+ phy-handle = <&phy20>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 4>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port17: port@17 {
+ reg = <17>;
+ phy-handle = <&phy21>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 4>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port18: port@18 {
+ reg = <18>;
+ phy-handle = <&phy22>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 4>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port19: port@19 {
+ reg = <19>;
+ phy-handle = <&phy23>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 4>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port20: port@20 {
+ reg = <20>;
+ phy-handle = <&phy24>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 5>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port21: port@21 {
+ reg = <21>;
+ phy-handle = <&phy25>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 5>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port22: port@22 {
+ reg = <22>;
+ phy-handle = <&phy26>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 5>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port23: port@23 {
+ reg = <23>;
+ phy-handle = <&phy27>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 5>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port24: port@24 {
+ reg = <24>;
+ phys = <&serdes 6>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp0>;
+ managed = "in-band-status";
+ microchip,bandwidth = <10000>;
+ microchip,sd-sgpio = <24>;
+ };
+
+ port25: port@25 {
+ reg = <25>;
+ phys = <&serdes 7>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp1>;
+ managed = "in-band-status";
+ microchip,bandwidth = <10000>;
+ microchip,sd-sgpio = <28>;
+ };
+
+ port26: port@26 {
+ reg = <26>;
+ phys = <&serdes 8>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp2>;
+ managed = "in-band-status";
+ microchip,bandwidth = <10000>;
+ microchip,sd-sgpio = <32>;
+ };
+
+ port27: port@27 {
+ reg = <27>;
+ phys = <&serdes 9>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp3>;
+ managed = "in-band-status";
+ microchip,bandwidth = <10000>;
+ microchip,sd-sgpio = <36>;
+ };
+
+ port29: port@29 {
+ reg = <29>;
+ phy-handle = <&phy3>;
+ phy-mode = "rgmii-id";
+ microchip,bandwidth = <1000>;
+ };
+ };
+};
+
+&tmon {
+ pinctrl-0 = <&fan_pins>;
+ pinctrl-names = "default";
+};
+
+&usart0 {
+ pinctrl-0 = <&fc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb {
+ pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm/dts/lan969x-u-boot.dtsi b/arch/arm/dts/lan969x-u-boot.dtsi
new file mode 100644
index 00000000000..066e0697d77
--- /dev/null
+++ b/arch/arm/dts/lan969x-u-boot.dtsi
@@ -0,0 +1,72 @@
+
+&switch {
+ /delete-property/ reg;
+ /delete-property/ reg-names;
+
+ reg = <0xe2900000 0x100000>, // ANA_AC
+ <0xe2400000 0x100000>, // ANA_CL
+ <0xe2800000 0x100000>, // ANA_L2
+ <0xe2480000 0x100000>, // ANA_L3
+ <0xe3200000 0x10000>, // ASM
+ <0xe2060000 0x10000>, // LRN
+ <0xe20b0000 0x10000>, // QFWD
+ <0xe2030000 0x20000>, // DEVCPU_QS
+ <0xe20a0000 0x10000>, // QSYS
+ <0xe2600000 0x80000>, // REW
+ <0xe2a00000 0x80000>, // VOP
+ <0xe30ec000 0x80000>, // DSM
+ <0xe22c0000 0x80000>, // EACL
+ <0xe2080000 0x80000>, // VCAP_SUPER
+ <0xe2580000 0x80000>, // HSCH
+ <0xe30f0000 0x10000>, // PORT_CONF
+ <0xe20c0000 0x10000>, // XQS
+ <0xe3408000 0x10000>, // HSIO
+ <0xe2010000 0x10000>, // GCB
+ <0xe00c0000 0x10000>, // CPU
+ <0xe2040000 0x10000>, // PTP
+ <0xe3004000 0x4000>, // DEV2G5_0
+ <0xe3010000 0x4000>, // DEV2G5_1
+ <0xe3014000 0x4000>, // DEV2G5_2
+ <0xe3018000 0x4000>, // DEV2G5_3
+ <0xe301c000 0x4000>, // DEV2G5_4
+ <0xe3028000 0x4000>, // DEV2G5_5
+ <0xe302c000 0x4000>, // DEV2G5_6
+ <0xe3030000 0x4000>, // DEV2G5_7
+ <0xe3034000 0x4000>, // DEV2G5_8
+ <0xe3040000 0x4000>, // DEV2G5_9
+ <0xe304c000 0x4000>, // DEV2G5_10
+ <0xe3050000 0x4000>, // DEV2G5_11
+ <0xe3054000 0x4000>, // DEV2G5_12
+ <0xe3060000 0x4000>, // DEV2G5_13
+ <0xe306c000 0x4000>, // DEV2G5_14
+ <0xe3070000 0x4000>, // DEV2G5_15
+ <0xe3074000 0x4000>, // DEV2G5_16
+ <0xe3080000 0x4000>, // DEV2G5_17
+ <0xe308c000 0x4000>, // DEV2G5_18
+ <0xe3090000 0x4000>, // DEV2G5_19
+ <0xe3094000 0x4000>, // DEV2G5_20
+ <0xe30a0000 0x4000>, // DEV2G5_21
+ <0xe30ac000 0x4000>, // DEV2G5_22
+ <0xe30b0000 0x4000>, // DEV2G5_23
+ <0xe30b4000 0x4000>, // DEV2G5_24
+ <0xe30c0000 0x4000>, // DEV2G5_25
+ <0xe30cc000 0x4000>, // DEV2G5_26
+ <0xe30d8000 0x4000>, // DEV2G5_27
+ <0xe30e4000 0x4000>, // DEV2G5_28 (RGMII)
+ <0xe30e8000 0x4000>, // DEV2G5_29 (RGMII)
+ <0xe3410000 0x150000>; // SERDES
+ reg-names =
+ "ana_ac", "ana_cl", "ana_l2", "ana_l3",
+ "asm", "lrn", "qfwd", "qs",
+ "qsys", "rew", "vop", "dsm",
+ "eacl", "vcap_super", "hsch", "port_conf", "xqs",
+ "hsio", "gcb", "cpu", "ptp",
+ "port0", "port1", "port2", "port3",
+ "port4", "port5", "port6", "port7", "port8",
+ "port9", "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17", "port18",
+ "port19", "port20", "port21", "port22", "port23",
+ "port24", "port25", "port26", "port27", "port28",
+ "port29";
+ clocks = <&fabric_clk>;
+};
diff --git a/arch/arm/mach-microchipsw/Kconfig b/arch/arm/mach-microchipsw/Kconfig
new file mode 100644
index 00000000000..aadd6beb00d
--- /dev/null
+++ b/arch/arm/mach-microchipsw/Kconfig
@@ -0,0 +1,31 @@
+if ARCH_MICROCHIPSW
+
+config SYS_SOC
+ default "microchipsw"
+
+config SYS_VENDOR
+ default "microchip"
+
+choice
+ prompt "Microchip switch SoC select"
+
+config TARGET_LAN969X
+ bool "Microchip LAN969x SoC"
+ select ARM64
+ select ARCH_SUPPORT_TFABOOT
+ select DM_SERIAL
+ select DM_GPIO
+ help
+ Support for Microchip LAN969X reference board platform.
+
+endchoice
+
+config SYS_BOARD
+ string "Board name"
+ default "lan969x" if TARGET_LAN969X
+ default ""
+
+config SYS_CONFIG_NAME
+ default "lan969x" if TARGET_LAN969X
+
+endif
diff --git a/arch/arm/mach-microchipsw/Makefile b/arch/arm/mach-microchipsw/Makefile
new file mode 100644
index 00000000000..39eca321705
--- /dev/null
+++ b/arch/arm/mach-microchipsw/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_TARGET_LAN969X) += lan969x/
diff --git a/arch/arm/mach-microchipsw/include/mach/soc.h b/arch/arm/mach-microchipsw/include/mach/soc.h
new file mode 100644
index 00000000000..cd1d61ff121
--- /dev/null
+++ b/arch/arm/mach-microchipsw/include/mach/soc.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _MICROCHIPSW_SOC_H_
+#define _MICROCHIPSW_SOC_H_
+
+#if defined(CONFIG_TARGET_LAN969X)
+#include <asm/types.h>
+
+typedef enum {
+ BOOT_SOURCE_EMMC = 0,
+ BOOT_SOURCE_QSPI,
+ BOOT_SOURCE_SDMMC,
+ BOOT_SOURCE_NONE
+} boot_source_type_t;
+
+phys_size_t tfa_get_dram_size(void);
+
+boot_source_type_t tfa_get_boot_source(void);
+
+int tfa_get_board_number(void);
+
+phys_size_t tfa_get_sram_info(int ix, phys_addr_t *start);
+
+#endif /* CONFIG_TARGET_LAN969X */
+#endif /* _LAN969X_SOC_H_ */
diff --git a/arch/arm/mach-microchipsw/lan969x/Makefile b/arch/arm/mach-microchipsw/lan969x/Makefile
new file mode 100644
index 00000000000..efa5153a3b7
--- /dev/null
+++ b/arch/arm/mach-microchipsw/lan969x/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y = soc.o
diff --git a/arch/arm/mach-microchipsw/lan969x/soc.c b/arch/arm/mach-microchipsw/lan969x/soc.c
new file mode 100644
index 00000000000..d094b52f888
--- /dev/null
+++ b/arch/arm/mach-microchipsw/lan969x/soc.c
@@ -0,0 +1,136 @@
+#include <asm/io.h>
+#include <dm/uclass.h>
+#include <linux/arm-smccc.h>
+#include <linux/bitfield.h>
+
+#include <asm/arch/soc.h>
+
+#define CPU_RESET_PROT_STAT 0xe00c0088
+#define SYS_RST_PROT_VCORE_M BIT(5)
+
+#define GCB_CHIP_ID 0xe2010000
+#define PART_ID_M GENMASK(27, 12)
+
+#define GCB_SOFT_RST 0xe201000c
+#define CHIP_SOFT_RST_M BIT(0)
+
+#define SIP_SVC_UID 0x8200ff01
+#define SIP_SVC_VERSION 0x8200ff02
+#define SIP_SVC_GET_BOOTSRC 0x8200ff09
+#define SIP_SVC_GET_DDR_SIZE 0x8200ff0a
+#define SIP_SVC_GET_BOARD_NO 0x8200ff0b
+#define SIP_SVC_SRAM_INFO 0x8200ff0d
+
+enum lan969x_part_id {
+ LAN9691VAO = 0x9691, /* lan969x-40-VAO */
+ LAN9692VAO = 0x9692, /* lan969x-65-VAO */
+ LAN9693VAO = 0x9693, /* lan969x-100-VAO */
+ LAN9694 = 0x9694, /* lan969x-40 */
+ LAN9694TSN = 0x9695, /* lan969x-40-TSN */
+ LAN9694RED = 0x969A, /* lan969x-40-RED */
+ LAN9696 = 0x9696, /* lan969x-60 */
+ LAN9696TSN = 0x9697, /* lan969x-60-TSN */
+ LAN9696RED = 0x969B, /* lan969x-60-RED */
+ LAN9698 = 0x9698, /* lan969x-100 */
+ LAN9698TSN = 0x9699, /* lan969x-100-TSN */
+ LAN9698RED = 0x969C, /* lan969x-100-RED */
+};
+
+boot_source_type_t tfa_get_boot_source(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SIP_SVC_GET_BOOTSRC, -1, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0)
+ return BOOT_SOURCE_NONE;
+
+ return (boot_source_type_t) res.a1;
+}
+
+phys_size_t tfa_get_dram_size(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SIP_SVC_GET_DDR_SIZE, -1, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0)
+ return 0;
+
+ return res.a1;
+}
+
+int tfa_get_board_number(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SIP_SVC_GET_BOARD_NO, -1, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0)
+ return 0;
+
+ return res.a1;
+}
+
+phys_size_t tfa_get_sram_info(int ix, phys_addr_t *start)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SIP_SVC_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0 == 0 && res.a1 <= 1) {
+ /* SRAM info supported > 0.1 */
+ return 0;
+ }
+
+ arm_smccc_smc(SIP_SVC_SRAM_INFO, ix, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0) {
+ /* No SRAM segment 'ix' */
+ return 0;
+ }
+
+ /* Have SRAM segment */
+ *start = res.a1;
+ return res.a2;
+}
+
+__weak void reset_cpu(void)
+{
+ clrbits_le32(CPU_RESET_PROT_STAT, SYS_RST_PROT_VCORE_M);
+ setbits_le32(GCB_SOFT_RST, CHIP_SOFT_RST_M);
+}
+
+static char *part_id_string(u32 chip_id_reg)
+{
+ switch (FIELD_GET(PART_ID_M, chip_id_reg)) {
+ case LAN9691VAO:
+ return "LAN9691VAO";
+ case LAN9692VAO:
+ return "LAN9692VAO";
+ case LAN9693VAO:
+ return "LAN9693VAO";
+ case LAN9694:
+ return "LAN9694";
+ case LAN9694TSN:
+ return "LAN9694TSN";
+ case LAN9694RED:
+ return "LAN9694RED";
+ case LAN9696:
+ return "LAN9696";
+ case LAN9696TSN:
+ return "LAN9696TSN";
+ case LAN9696RED:
+ return "LAN9696RED";
+ case LAN9698:
+ return "LAN9698";
+ case LAN9698TSN:
+ return "LAN9698TSN";
+ case LAN9698RED:
+ return "LAN9698RED";
+ default:
+ return "Unknown ID";
+ }
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: %s\n", part_id_string(readl(GCB_CHIP_ID)));
+
+ return 0;
+}
diff --git a/board/microchip/lan969x/Makefile b/board/microchip/lan969x/Makefile
new file mode 100644
index 00000000000..97e3de097b4
--- /dev/null
+++ b/board/microchip/lan969x/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := lan969x.o
diff --git a/board/microchip/lan969x/lan969x.c b/board/microchip/lan969x/lan969x.c
new file mode 100644
index 00000000000..47083a95999
--- /dev/null
+++ b/board/microchip/lan969x/lan969x.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include <asm/io.h>
+#include <asm/armv8/cpu.h>
+#include <asm/armv8/mmu.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <linux/sizes.h>
+#include <asm/global_data.h>
+#include <env.h>
+#include <env_internal.h>
+
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region fa_mem_map[] = {
+ {
+ .virt = PHYS_SDRAM_1,
+ .phys = PHYS_SDRAM_1,
+ .size = PHYS_SDRAM_1_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = LAN969X_SRAM_BASE,
+ .phys = LAN969X_SRAM_BASE,
+ .size = LAN969X_SRAM_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = LAN969X_QSPI0_MMAP,
+ .phys = LAN969X_QSPI0_MMAP,
+ .size = LAN969X_QSPI0_RANGE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = LAN969X_DEV_BASE,
+ .phys = LAN969X_DEV_BASE,
+ .size = LAN969X_DEV_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = LAN969X_USB_BASE,
+ .phys = LAN969X_USB_BASE,
+ .size = LAN969X_USB_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+struct mm_region *mem_map = fa_mem_map;
+
+int dram_init(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ /* Fall-back to compile-time default */
+ if (!gd->ram_size)
+ gd->ram_size = LAN969X_DDR_SIZE_DEF;
+
+ return 0;
+}
+
+static void add_memory_bank(int bankno, phys_addr_t start, phys_size_t size)
+{
+ gd->bd->bi_dram[bankno].start = start;
+ gd->bd->bi_dram[bankno].size = size;
+}
+
+int dram_init_banksize(void)
+{
+ int bankno = 0;
+ phys_addr_t start;
+ phys_size_t size;
+
+ /* Add DDR */
+ add_memory_bank(bankno++, PHYS_SDRAM_1, gd->ram_size);
+
+ /* First the lower half of SRAM */
+ size = tfa_get_sram_info(0, &start);
+ if (size) {
+ add_memory_bank(bankno++, start, size);
+ }
+
+ /* Upper half of SRAM has 1st 128K reserved for BL31 */
+ size = tfa_get_sram_info(1, &start);
+ if (size) {
+ add_memory_bank(bankno++, start, size);
+ }
+
+ return 0;
+}
+
+int arch_cpu_init(void)
+{
+ return 0;
+}
+
+int mach_cpu_init(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/configs/microchip_ev23x71a_defconfig b/configs/microchip_ev23x71a_defconfig
new file mode 100644
index 00000000000..2717f6e9adf
--- /dev/null
+++ b/configs/microchip_ev23x71a_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_MICROCHIPSW=y
+CONFIG_TFABOOT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DEFAULT_DEVICE_TREE="lan9696-ev23x71a"
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_LOAD_ADDR=0x64000000
+CONFIG_DEBUG_UART_BASE=0xe0040200
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_HUSH_OLD_PARSER is not set
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_WGET=y
+CONFIG_EFI_PARTITION=y
+CONFIG_DEVICE_TREE_INCLUDES="lan969x-u-boot.dtsi"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_MMC_USE_SW_PARTITION=y
+CONFIG_ENV_MMC_SW_PARTITION="Env"
+CONFIG_PROT_TCP_SACK=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_CLK_LAN966X=y
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_MICROCHIP_FLEXCOM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MICROCHIP=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_MSCC_LAN969X_SWITCH=y
+CONFIG_MDIO_MSCC_MIIM=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_LAN969X=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
diff --git a/include/configs/lan969x.h b/include/configs/lan969x.h
new file mode 100644
index 00000000000..3164b1b3da2
--- /dev/null
+++ b/include/configs/lan969x.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __LAN969X_CONFIG_H
+#define __LAN969X_CONFIG_H
+
+#include <linux/sizes.h>
+
+/* LAN969X defines */
+#define LAN969X_QSPI0_MMAP UL(0x20000000)
+#define LAN969X_QSPI0_RANGE SZ_256M
+#define LAN969X_SRAM_BASE UL(0x00100000)
+#define LAN969X_SRAM_SIZE SZ_2M
+#define LAN969X_DDR_BASE UL(0x60000000)
+#define LAN969X_DDR_SIZE_DEF (SZ_1G - (SZ_1G / 8)) /* ECC enabled cost 1/8th capacity */
+#define LAN969X_DDR_SIZE_MAX SZ_2G
+
+#define LAN969X_DEV_BASE UL(0xE0000000)
+#define LAN969X_DEV_SIZE UL(0x10000000)
+
+#define LAN969X_USB_BASE 0x300000
+#define LAN969X_USB_SIZE 0x80000
+
+#define PHYS_SDRAM_1 LAN969X_DDR_BASE
+#define PHYS_SDRAM_1_SIZE LAN969X_DDR_SIZE_MAX /* Used for MMU table - only */
+
+#define CFG_SYS_SDRAM_BASE LAN969X_DDR_BASE
+#define CFG_SYS_INIT_RAM_ADDR (LAN969X_DDR_BASE + SZ_64M)
+#define CFG_SYS_INIT_RAM_SIZE SZ_32K
+
+#define CFG_SYS_BOOTMAPSZ SZ_64M /* Initial map for Linux*/
+
+#endif /* __LAN969X_CONFIG_H */
--
2.53.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 13/14] net: phy: add Microchip LAN8841 support
2026-03-26 11:26 ` [PATCH 13/14] net: phy: add Microchip LAN8841 support Robert Marko
@ 2026-04-09 10:04 ` Manikandan.M
0 siblings, 0 replies; 18+ messages in thread
From: Manikandan.M @ 2026-04-09 10:04 UTC (permalink / raw)
To: robert.marko, u-boot, trini, lukma, hs, peng.fan, jh80.chung,
gregory.clement, Lars.Povlsen, Horatiu.Vultur, jerome.forissier,
marex, Daniel.Machon
Cc: luka.perkov
Hi Robert,
LAN8841 support can be merged into the Microchip SMSC PHY driver that
handles other LAN8xxx PHYs.
On 26/03/26 4:56 pm, Robert Marko wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add driver for the Microchip LAN8841 PHY.
>
> It provides fixes for erratas, as well as support for enabling the required
> RGMII delays based on the PHY mode.
>
> It is based on the upstream Linux driver.
>
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> ---
> drivers/net/phy/Kconfig | 3 +
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/microchip.c | 185 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 189 insertions(+)
> create mode 100644 drivers/net/phy/microchip.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 709f1c91eb2..3eaf9d7495f 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -231,6 +231,9 @@ config PHY_MICREL_KSZ8XXX
>
> endif # PHY_MICREL
>
> +config PHY_MICROCHIP
> + bool "Microchip Ethernet PHYs support"
> +
> config PHY_MOTORCOMM
> tristate "Motorcomm PHYs"
> help
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index 83520de7f1f..04e9d61a3c2 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -25,6 +25,7 @@ obj-y += mediatek/
> obj-y += airoha/
> obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
> obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
> +obj-$(CONFIG_PHY_MICROCHIP) += microchip.o
> obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
> obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o
> obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
> diff --git a/drivers/net/phy/microchip.c b/drivers/net/phy/microchip.c
> new file mode 100644
> index 00000000000..bc54311ab72
> --- /dev/null
> +++ b/drivers/net/phy/microchip.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <phy.h>
> +#include <linux/bitops.h>
> +
> +#define PHY_ID_MATCH_MODEL_MASK GENMASK(31, 4)
> +#define PHY_ID_LAN8841 0x00221650
> +
> +#define LAN8841_MMD_COMMON_CTRL_REG 2
> +#define LAN8841_RXC_DLL_CTRL 76
> +#define LAN8841_TXC_DLL_CTRL 77
> +#define LAN8841_DLL_ENABLE_DELAY 0
> +
> +#define LAN8841_MMD_TIMER_REG 0
> +#define LAN8841_MMD0_REGISTER_17 17
> +#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
> +#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
> +#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
> +#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
> +#define LAN8841_MMD_ANALOG_REG 28
> +#define LAN8841_ANALOG_CONTROL_1 1
> +#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
> +#define LAN8841_ANALOG_CONTROL_10 13
> +#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
> +#define LAN8841_ANALOG_CONTROL_11 14
> +#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
> +#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
> +#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
> +#define LAN8841_BTRX_POWER_DOWN 70
> +#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
> +#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
> +#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
> +#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
> +#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
> +#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
> +#define LAN8841_ADC_CHANNEL_MASK 198
> +#define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370
> +#define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371
> +#define LAN8841_PTP_RX_VERSION 374
> +#define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434
> +#define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435
> +#define LAN8841_PTP_TX_VERSION 438
> +#define LAN8841_PTP_CMD_CTL 256
> +#define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2)
> +#define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1)
> +#define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0)
> +#define LAN8841_PTP_RX_PARSE_CONFIG 368
> +#define LAN8841_PTP_TX_PARSE_CONFIG 432
> +#define LAN8841_PTP_RX_MODE 381
> +#define LAN8841_PTP_INSERT_TS_EN BIT(0)
> +#define LAN8841_PTP_INSERT_TS_32BIT BIT(1)
> +
> +static int lan8841_config_rgmii_delay(struct phy_device *phydev)
> +{
> + u16 rxcdll_val, txcdll_val;
> + int ret;
> +
> + switch (phydev->interface) {
> + case PHY_INTERFACE_MODE_RGMII:
> + rxcdll_val = BIT(14);
> + txcdll_val = BIT(14);
> + break;
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + rxcdll_val = LAN8841_DLL_ENABLE_DELAY;
> + txcdll_val = LAN8841_DLL_ENABLE_DELAY;
> + break;
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + rxcdll_val = LAN8841_DLL_ENABLE_DELAY;
> + txcdll_val = BIT(14);
> + break;
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + rxcdll_val = BIT(14);
> + txcdll_val = LAN8841_DLL_ENABLE_DELAY;
> + break;
> + default:
> + return 0;
> + }
> +
> + ret = phy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_RXC_DLL_CTRL, BIT_MASK(14),
> + rxcdll_val);
> + if (ret < 0)
> + return ret;
> +
> + return phy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_TXC_DLL_CTRL, BIT_MASK(14),
> + txcdll_val);
> +}
> +
> +static int lan8841_config_init(struct phy_device *phydev)
> +{
> + int ret;
> +
> + if (phy_interface_is_rgmii(phydev)) {
> + ret = lan8841_config_rgmii_delay(phydev);
> + if (ret < 0)
> + return ret;
> + }
> +
> + /* Initialize the HW by resetting everything */
> + phy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_CMD_CTL,
> + LAN8841_PTP_CMD_CTL_PTP_RESET,
> + LAN8841_PTP_CMD_CTL_PTP_RESET);
> +
> + phy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_CMD_CTL,
> + LAN8841_PTP_CMD_CTL_PTP_ENABLE,
> + LAN8841_PTP_CMD_CTL_PTP_ENABLE);
> +
> + /* Don't process any frames */
> + phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_RX_PARSE_CONFIG, 0);
> + phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_TX_PARSE_CONFIG, 0);
> + phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);
> + phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);
> + phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);
> + phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);
> +
> + /* Disable checking for minorVersionPTP field */
> + phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_RX_VERSION, 0xff00);
> + phy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_TX_VERSION, 0xff00);
> +
> + /* 100BT Clause 40 improvement errata */
> + phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
> + LAN8841_ANALOG_CONTROL_1,
> + LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
> + phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
> + LAN8841_ANALOG_CONTROL_10,
> + LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
> +
> + /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
> + * Magnetics
> + */
> + ret = phy_read_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,
> + LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
> + if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
> + phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
> + LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
> + LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
> + phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
> + LAN8841_BTRX_POWER_DOWN,
> + LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
> + LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
> + LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
> + LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
> + LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
> + LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
> + }
> +
> + /* LDO Adjustment errata */
> + phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
> + LAN8841_ANALOG_CONTROL_11,
> + LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
> +
> + /* 100BT RGMII latency tuning errata */
> + phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
> + LAN8841_ADC_CHANNEL_MASK, 0x0);
> + phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
> + LAN8841_MMD0_REGISTER_17,
> + LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
> + LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
> +
> + /* Disable Power Down */
> + phy_modify(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_PDOWN, 0);
> +
> + return 0;
> +}
> +
> +U_BOOT_PHY_DRIVER(lan8841) = {
> + .name = "Microchip LAN8841",
> + .uid = PHY_ID_LAN8841,
> + .mask = PHY_ID_MATCH_MODEL_MASK,
> + .features = PHY_GBIT_FEATURES,
> + .config = &lan8841_config_init,
> + .startup = &genphy_startup,
> + .shutdown = &genphy_shutdown,
> +};
> --
> 2.53.0
>
--
Thanks and Regards,
Manikandan M.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
` (12 preceding siblings ...)
2026-03-26 11:26 ` [PATCH 14/14] arch: arm: add Microchip LAN969x support Robert Marko
@ 2026-04-25 13:35 ` Eugen Hristev
2026-04-27 9:56 ` Robert Marko
13 siblings, 1 reply; 18+ messages in thread
From: Eugen Hristev @ 2026-04-25 13:35 UTC (permalink / raw)
To: Robert Marko, u-boot, trini, lukma, hs, peng.fan, jh80.chung,
gregory.clement, lars.povlsen, horatiu.vultur, jerome.forissier,
marex, daniel.machon
Cc: luka.perkov
On 3/26/26 13:26, Robert Marko wrote:
> USART driver is reused by a lot of Microchip platforms, in this case we
> need it for LAN969x so allow selecting it when ARCH_MICROCHIPSW is used.
Hello Robert,
I apologize for not replying to this sooner, but my old email address
was bouncing.
I did not find any information(or cover letter), about this series,
because it looks like you are sending this on top of something else,
which is not merged yet.
I am not familiar with ARCH_MICROCHIPSW which is not in Uboot.
Can you please clarify ?
Sorry again,
Eugen
>
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> ---
> drivers/serial/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index b84cb9ec781..3848c3ca20e 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -665,7 +665,7 @@ config ARM_DCC
>
> config ATMEL_USART
> bool "Atmel USART support"
> - depends on ARCH_AT91
> + depends on ARCH_AT91 || ARCH_MICROCHIPSW
> help
> Select this to enable USART support for Atmel SoCs. It can be
> configured in the device tree, and input clock frequency can
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW
2026-04-25 13:35 ` [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Eugen Hristev
@ 2026-04-27 9:56 ` Robert Marko
2026-04-27 20:42 ` Eugen Hristev
0 siblings, 1 reply; 18+ messages in thread
From: Robert Marko @ 2026-04-27 9:56 UTC (permalink / raw)
To: Eugen Hristev
Cc: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon, luka.perkov
On Sat, Apr 25, 2026 at 3:35 PM Eugen Hristev <ehristev@kernel.org> wrote:
>
> On 3/26/26 13:26, Robert Marko wrote:
> > USART driver is reused by a lot of Microchip platforms, in this case we
> > need it for LAN969x so allow selecting it when ARCH_MICROCHIPSW is used.
>
> Hello Robert,
>
> I apologize for not replying to this sooner, but my old email address
> was bouncing.
>
> I did not find any information(or cover letter), about this series,
> because it looks like you are sending this on top of something else,
> which is not merged yet.
> I am not familiar with ARCH_MICROCHIPSW which is not in Uboot.
> Can you please clarify ?
Hi Eugen,
ARCH_MICROCHIPSW is not yet in U-Boot, but its being added via the
same series patch series.
Its the new arch that will hold LAN969x for start, but other Microchip
switch SoC-s in future as well.
Regards,
Robert
>
> Sorry again,
> Eugen
>
> >
> > Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> > ---
> > drivers/serial/Kconfig | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> > index b84cb9ec781..3848c3ca20e 100644
> > --- a/drivers/serial/Kconfig
> > +++ b/drivers/serial/Kconfig
> > @@ -665,7 +665,7 @@ config ARM_DCC
> >
> > config ATMEL_USART
> > bool "Atmel USART support"
> > - depends on ARCH_AT91
> > + depends on ARCH_AT91 || ARCH_MICROCHIPSW
> > help
> > Select this to enable USART support for Atmel SoCs. It can be
> > configured in the device tree, and input clock frequency can
>
--
Robert Marko
Staff Embedded Linux Engineer
Sartura d.d.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko@sartura.hr
Web: www.sartura.hr
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW
2026-04-27 9:56 ` Robert Marko
@ 2026-04-27 20:42 ` Eugen Hristev
0 siblings, 0 replies; 18+ messages in thread
From: Eugen Hristev @ 2026-04-27 20:42 UTC (permalink / raw)
To: Robert Marko
Cc: u-boot, trini, lukma, hs, peng.fan, jh80.chung, gregory.clement,
lars.povlsen, horatiu.vultur, jerome.forissier, marex,
daniel.machon, luka.perkov
On 4/27/26 12:56, Robert Marko wrote:
> On Sat, Apr 25, 2026 at 3:35 PM Eugen Hristev <ehristev@kernel.org> wrote:
>>
>> On 3/26/26 13:26, Robert Marko wrote:
>>> USART driver is reused by a lot of Microchip platforms, in this case we
>>> need it for LAN969x so allow selecting it when ARCH_MICROCHIPSW is used.
>>
>> Hello Robert,
>>
>> I apologize for not replying to this sooner, but my old email address
>> was bouncing.
>>
>> I did not find any information(or cover letter), about this series,
>> because it looks like you are sending this on top of something else,
>> which is not merged yet.
>> I am not familiar with ARCH_MICROCHIPSW which is not in Uboot.
>> Can you please clarify ?
>
> Hi Eugen,
> ARCH_MICROCHIPSW is not yet in U-Boot, but its being added via the
> same series patch series.
This is the first patch in the series, adding a dependency to a knob not
yet added.
I would expect a first patch that would introduce this ARCH.
Please add changes in a logical manner to make some sense
Thanks
Eugen
>
> Its the new arch that will hold LAN969x for start, but other Microchip
> switch SoC-s in future as well.
>
> Regards,
> Robert
>>
>> Sorry again,
>> Eugen
>>
>>>
>>> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
>>> ---
>>> drivers/serial/Kconfig | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
>>> index b84cb9ec781..3848c3ca20e 100644
>>> --- a/drivers/serial/Kconfig
>>> +++ b/drivers/serial/Kconfig
>>> @@ -665,7 +665,7 @@ config ARM_DCC
>>>
>>> config ATMEL_USART
>>> bool "Atmel USART support"
>>> - depends on ARCH_AT91
>>> + depends on ARCH_AT91 || ARCH_MICROCHIPSW
>>> help
>>> Select this to enable USART support for Atmel SoCs. It can be
>>> configured in the device tree, and input clock frequency can
>>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2026-04-28 3:50 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-03-26 11:26 [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Robert Marko
2026-03-26 11:26 ` [PATCH 02/14] pinctrl: add Microchip LAN969x driver Robert Marko
2026-03-26 11:26 ` [PATCH 03/14] clk: add Microchip LAN966x and LAN969x support Robert Marko
2026-03-26 11:26 ` [PATCH 04/14] mmc: atmel: remove duplicate depends on ARCH_AT91 Robert Marko
2026-03-26 11:26 ` [PATCH 05/14] mmc: atmel-sdhci: set GCK rate based on compatible Robert Marko
2026-03-26 11:26 ` [PATCH 06/14] mmc: atmel-sdhci: include arch specific clk.h only for AT91 Robert Marko
2026-03-26 11:26 ` [PATCH 07/14] mmc: atmel-sdhci: add support for LAN969x Robert Marko
2026-03-26 11:26 ` [PATCH 08/14] i2c: at91-i2c: include arch specific clk.h only for AT91 Robert Marko
2026-03-26 11:26 ` [PATCH 09/14] i2c: i2c-at91: allow selecting from ARCH_MICROCHIPSW Robert Marko
2026-03-26 11:26 ` [PATCH 10/14] usb: dwc3-generic: add support for Microchip LAN969x Robert Marko
2026-03-26 11:26 ` [PATCH 11/14] spi: atmel-quadspi: add Microchip LAN969x support Robert Marko
2026-03-26 11:26 ` [PATCH 12/14] net: add Microchip SparX-5 and " Robert Marko
2026-03-26 11:26 ` [PATCH 13/14] net: phy: add Microchip LAN8841 support Robert Marko
2026-04-09 10:04 ` Manikandan.M
2026-03-26 11:26 ` [PATCH 14/14] arch: arm: add Microchip LAN969x support Robert Marko
2026-04-25 13:35 ` [PATCH 01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW Eugen Hristev
2026-04-27 9:56 ` Robert Marko
2026-04-27 20:42 ` Eugen Hristev
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