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From: "Heiko Stübner" <heiko@sntech.de>
To: linux-rockchip@lists.infradead.org,
	Geraldo Nascimento <geraldogabriel@gmail.com>
Cc: "Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Valmantas Paliksa" <walmis@gmail.com>,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 3/4] phy: rockchip-pcie: Enable all four lanes if required
Date: Mon, 30 Jun 2025 23:33:19 +0200	[thread overview]
Message-ID: <4006908.X513TT2pbd@diego> (raw)
In-Reply-To: <d3e7dc38bd287aa93a5d6bba87bf3c428ae92ca4.1751307390.git.geraldogabriel@gmail.com>

Am Montag, 30. Juni 2025, 20:22:01 Mitteleuropäische Sommerzeit schrieb Geraldo Nascimento:
> Current code enables only Lane 0 because pwr_cnt will be incremented on
> first call to the function. Let's reorder the enablement code to enable
> all 4 lanes through GRF.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> 
> Signed-off-by: Valmantas Paliksa <walmis@gmail.com>
> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>

hmm, if Valmantas is the original author you should probably keep that authorship
  git commit --amend --author="Valmantas Paliksa <walmis@gmail.com>"
should do the trick.

The first signed-off should be from the patch author, then your signed-off
indicates you handling the patch later as part of this series.

[or, if you modified the code of the patch heavily, Co-developed-by could
 also be appropriate]

Heiko

> ---
>  drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
> index bd44af36c67a..f22ffb41cdc2 100644
> --- a/drivers/phy/rockchip/phy-rockchip-pcie.c
> +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
> @@ -160,6 +160,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
>  
>  	guard(mutex)(&rk_phy->pcie_mutex);
>  
> +	regmap_write(rk_phy->reg_base,
> +		     rk_phy->phy_data->pcie_laneoff,
> +		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> +				   PHY_LANE_IDLE_MASK,
> +				   PHY_LANE_IDLE_A_SHIFT + inst->index));
> +
>  	if (rk_phy->pwr_cnt++) {
>  		return 0;
>  	}
> @@ -176,12 +182,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
>  				   PHY_CFG_ADDR_MASK,
>  				   PHY_CFG_ADDR_SHIFT));
>  
> -	regmap_write(rk_phy->reg_base,
> -		     rk_phy->phy_data->pcie_laneoff,
> -		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> -				   PHY_LANE_IDLE_MASK,
> -				   PHY_LANE_IDLE_A_SHIFT + inst->index));
> -
>  	/*
>  	 * No documented timeout value for phy operation below,
>  	 * so we make it large enough here. And we use loop-break
> 






WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: linux-rockchip@lists.infradead.org,
	Geraldo Nascimento <geraldogabriel@gmail.com>
Cc: "Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Valmantas Paliksa" <walmis@gmail.com>,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 3/4] phy: rockchip-pcie: Enable all four lanes if required
Date: Mon, 30 Jun 2025 23:33:19 +0200	[thread overview]
Message-ID: <4006908.X513TT2pbd@diego> (raw)
In-Reply-To: <d3e7dc38bd287aa93a5d6bba87bf3c428ae92ca4.1751307390.git.geraldogabriel@gmail.com>

Am Montag, 30. Juni 2025, 20:22:01 Mitteleuropäische Sommerzeit schrieb Geraldo Nascimento:
> Current code enables only Lane 0 because pwr_cnt will be incremented on
> first call to the function. Let's reorder the enablement code to enable
> all 4 lanes through GRF.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> 
> Signed-off-by: Valmantas Paliksa <walmis@gmail.com>
> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>

hmm, if Valmantas is the original author you should probably keep that authorship
  git commit --amend --author="Valmantas Paliksa <walmis@gmail.com>"
should do the trick.

The first signed-off should be from the patch author, then your signed-off
indicates you handling the patch later as part of this series.

[or, if you modified the code of the patch heavily, Co-developed-by could
 also be appropriate]

Heiko

> ---
>  drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
> index bd44af36c67a..f22ffb41cdc2 100644
> --- a/drivers/phy/rockchip/phy-rockchip-pcie.c
> +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
> @@ -160,6 +160,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
>  
>  	guard(mutex)(&rk_phy->pcie_mutex);
>  
> +	regmap_write(rk_phy->reg_base,
> +		     rk_phy->phy_data->pcie_laneoff,
> +		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> +				   PHY_LANE_IDLE_MASK,
> +				   PHY_LANE_IDLE_A_SHIFT + inst->index));
> +
>  	if (rk_phy->pwr_cnt++) {
>  		return 0;
>  	}
> @@ -176,12 +182,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
>  				   PHY_CFG_ADDR_MASK,
>  				   PHY_CFG_ADDR_SHIFT));
>  
> -	regmap_write(rk_phy->reg_base,
> -		     rk_phy->phy_data->pcie_laneoff,
> -		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> -				   PHY_LANE_IDLE_MASK,
> -				   PHY_LANE_IDLE_A_SHIFT + inst->index));
> -
>  	/*
>  	 * No documented timeout value for phy operation below,
>  	 * so we make it large enough here. And we use loop-break
> 





-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: linux-rockchip@lists.infradead.org,
	Geraldo Nascimento <geraldogabriel@gmail.com>
Cc: "Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Valmantas Paliksa" <walmis@gmail.com>,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 3/4] phy: rockchip-pcie: Enable all four lanes if required
Date: Mon, 30 Jun 2025 23:33:19 +0200	[thread overview]
Message-ID: <4006908.X513TT2pbd@diego> (raw)
In-Reply-To: <d3e7dc38bd287aa93a5d6bba87bf3c428ae92ca4.1751307390.git.geraldogabriel@gmail.com>

Am Montag, 30. Juni 2025, 20:22:01 Mitteleuropäische Sommerzeit schrieb Geraldo Nascimento:
> Current code enables only Lane 0 because pwr_cnt will be incremented on
> first call to the function. Let's reorder the enablement code to enable
> all 4 lanes through GRF.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> 
> Signed-off-by: Valmantas Paliksa <walmis@gmail.com>
> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>

hmm, if Valmantas is the original author you should probably keep that authorship
  git commit --amend --author="Valmantas Paliksa <walmis@gmail.com>"
should do the trick.

The first signed-off should be from the patch author, then your signed-off
indicates you handling the patch later as part of this series.

[or, if you modified the code of the patch heavily, Co-developed-by could
 also be appropriate]

Heiko

> ---
>  drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
> index bd44af36c67a..f22ffb41cdc2 100644
> --- a/drivers/phy/rockchip/phy-rockchip-pcie.c
> +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
> @@ -160,6 +160,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
>  
>  	guard(mutex)(&rk_phy->pcie_mutex);
>  
> +	regmap_write(rk_phy->reg_base,
> +		     rk_phy->phy_data->pcie_laneoff,
> +		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> +				   PHY_LANE_IDLE_MASK,
> +				   PHY_LANE_IDLE_A_SHIFT + inst->index));
> +
>  	if (rk_phy->pwr_cnt++) {
>  		return 0;
>  	}
> @@ -176,12 +182,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
>  				   PHY_CFG_ADDR_MASK,
>  				   PHY_CFG_ADDR_SHIFT));
>  
> -	regmap_write(rk_phy->reg_base,
> -		     rk_phy->phy_data->pcie_laneoff,
> -		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> -				   PHY_LANE_IDLE_MASK,
> -				   PHY_LANE_IDLE_A_SHIFT + inst->index));
> -
>  	/*
>  	 * No documented timeout value for phy operation below,
>  	 * so we make it large enough here. And we use loop-break
> 





_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

  reply	other threads:[~2025-06-30 22:50 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-30 18:21 [PATCH v8 0/4] PCI: rockchip: Improve driver quality Geraldo Nascimento
2025-06-30 18:21 ` Geraldo Nascimento
2025-06-30 18:21 ` Geraldo Nascimento
2025-06-30 18:21 ` [PATCH v8 1/4] PCI: rockchip: Use standard PCIe defines Geraldo Nascimento
2025-06-30 18:21   ` Geraldo Nascimento
2025-06-30 18:21   ` Geraldo Nascimento
2025-06-30 18:21 ` [PATCH v8 2/4] PCI: rockchip: Set Target Link Speed before retraining Geraldo Nascimento
2025-06-30 18:21   ` Geraldo Nascimento
2025-06-30 18:21   ` Geraldo Nascimento
2025-06-30 18:22 ` [PATCH v8 3/4] phy: rockchip-pcie: Enable all four lanes if required Geraldo Nascimento
2025-06-30 18:22   ` Geraldo Nascimento
2025-06-30 18:22   ` Geraldo Nascimento
2025-06-30 21:33   ` Heiko Stübner [this message]
2025-06-30 21:33     ` Heiko Stübner
2025-06-30 21:33     ` Heiko Stübner
2025-06-30 21:43     ` Geraldo Nascimento
2025-06-30 21:43       ` Geraldo Nascimento
2025-06-30 21:43       ` Geraldo Nascimento
2025-06-30 22:28     ` Geraldo Nascimento
2025-06-30 22:28       ` Geraldo Nascimento
2025-06-30 22:28       ` Geraldo Nascimento
2025-06-30 18:22 ` [PATCH v8 4/4] phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal Geraldo Nascimento
2025-06-30 18:22   ` Geraldo Nascimento
2025-06-30 18:22   ` Geraldo Nascimento

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