* [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP
@ 2025-11-06 2:06 ` Chaoyi Chen
0 siblings, 0 replies; 71+ messages in thread
From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sandy Huang,
Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-rockchip, linux-phy, Chaoyi Chen
From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
The VOP on rk3506:
- Support 2 lane MIPI DSI interface, 1.5Gbps/lane.
- Support RGB interface.
- Max output resolution is 1280x1280@60fps.
- WIN1 layer support RGB888/ARGB8888/RGB565.
- Support Gamma LUT.
This series adds basic support for rk3506 VOP. And tested on the
rk3506g-evb1-v10 board with a Wanchanglong W552946AAA DSI panel.
Chaoyi Chen (9):
dt-bindings: ili9881c: Add compatible string for Wanchanglong
w552946aaa
dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506
dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506
dt-bindings: display: rockchip,vop: Add compatible for rk3506
drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA
panel
phy: rockchip: inno-dsidphy: Add support for rk3506
drm/rockchip: dsi: Add support for rk3506
drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP
drm/rockchip: vop: Add support for rk3506
.../display/panel/ilitek,ili9881c.yaml | 1 +
.../rockchip/rockchip,dw-mipi-dsi.yaml | 1 +
.../display/rockchip/rockchip-vop.yaml | 1 +
.../bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 +
drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 225 ++++++++++++++++++
drivers/gpu/drm/rockchip/Kconfig | 3 +-
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 ++
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 57 +++++
drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 14 ++
.../phy/rockchip/phy-rockchip-inno-dsidphy.c | 91 ++++++-
10 files changed, 410 insertions(+), 4 deletions(-)
--
2.51.1
^ permalink raw reply [flat|nested] 71+ messages in thread* [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The VOP on rk3506: - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. - Support RGB interface. - Max output resolution is 1280x1280@60fps. - WIN1 layer support RGB888/ARGB8888/RGB565. - Support Gamma LUT. This series adds basic support for rk3506 VOP. And tested on the rk3506g-evb1-v10 board with a Wanchanglong W552946AAA DSI panel. Chaoyi Chen (9): dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 dt-bindings: display: rockchip,vop: Add compatible for rk3506 drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel phy: rockchip: inno-dsidphy: Add support for rk3506 drm/rockchip: dsi: Add support for rk3506 drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP drm/rockchip: vop: Add support for rk3506 .../display/panel/ilitek,ili9881c.yaml | 1 + .../rockchip/rockchip,dw-mipi-dsi.yaml | 1 + .../display/rockchip/rockchip-vop.yaml | 1 + .../bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 225 ++++++++++++++++++ drivers/gpu/drm/rockchip/Kconfig | 3 +- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 ++ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 57 +++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 14 ++ .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 91 ++++++- 10 files changed, 410 insertions(+), 4 deletions(-) -- 2.51.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The VOP on rk3506: - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. - Support RGB interface. - Max output resolution is 1280x1280@60fps. - WIN1 layer support RGB888/ARGB8888/RGB565. - Support Gamma LUT. This series adds basic support for rk3506 VOP. And tested on the rk3506g-evb1-v10 board with a Wanchanglong W552946AAA DSI panel. Chaoyi Chen (9): dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 dt-bindings: display: rockchip,vop: Add compatible for rk3506 drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel phy: rockchip: inno-dsidphy: Add support for rk3506 drm/rockchip: dsi: Add support for rk3506 drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP drm/rockchip: vop: Add support for rk3506 .../display/panel/ilitek,ili9881c.yaml | 1 + .../rockchip/rockchip,dw-mipi-dsi.yaml | 1 + .../display/rockchip/rockchip-vop.yaml | 1 + .../bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 225 ++++++++++++++++++ drivers/gpu/drm/rockchip/Kconfig | 3 +- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 ++ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 57 +++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 14 ++ .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 91 ++++++- 10 files changed, 410 insertions(+), 4 deletions(-) -- 2.51.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 1/9] dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 2:06 ` Chaoyi Chen -1 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> Like w552946aba, w552946aaa uses the Ilitek ILI9881D controller chip, and it supports up to 2 lanes. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../devicetree/bindings/display/panel/ilitek,ili9881c.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml index 434cc6af9c95..f331a47cc759 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml @@ -23,6 +23,7 @@ properties: - raspberrypi,dsi-7inch - startek,kd050hdfia020 - tdo,tl050hdv35 + - wanchanglong,w552946aaa - wanchanglong,w552946aba - const: ilitek,ili9881c -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 1/9] dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> Like w552946aba, w552946aaa uses the Ilitek ILI9881D controller chip, and it supports up to 2 lanes. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../devicetree/bindings/display/panel/ilitek,ili9881c.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml index 434cc6af9c95..f331a47cc759 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml @@ -23,6 +23,7 @@ properties: - raspberrypi,dsi-7inch - startek,kd050hdfia020 - tdo,tl050hdv35 + - wanchanglong,w552946aaa - wanchanglong,w552946aba - const: ilitek,ili9881c -- 2.51.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 1/9] dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> Like w552946aba, w552946aaa uses the Ilitek ILI9881D controller chip, and it supports up to 2 lanes. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../devicetree/bindings/display/panel/ilitek,ili9881c.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml index 434cc6af9c95..f331a47cc759 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml @@ -23,6 +23,7 @@ properties: - raspberrypi,dsi-7inch - startek,kd050hdfia020 - tdo,tl050hdv35 + - wanchanglong,w552946aaa - wanchanglong,w552946aba - const: ilitek,ili9881c -- 2.51.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 1/9] dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 17:28 ` Conor Dooley -1 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:28 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 1/9] dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa @ 2025-11-06 17:28 ` Conor Dooley 0 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:28 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1.1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 170 bytes --] _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 1/9] dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa @ 2025-11-06 17:28 ` Conor Dooley 0 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:28 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1.1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 112 bytes --] -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 2/9] dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 2:06 ` Chaoyi Chen -1 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> Document a compatible string for the rk3506 dsi-dphy. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml index 46e64fa293d5..83e7c825860c 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -18,6 +18,7 @@ properties: - rockchip,px30-dsi-dphy - rockchip,rk3128-dsi-dphy - rockchip,rk3368-dsi-dphy + - rockchip,rk3506-dsi-dphy - rockchip,rk3568-dsi-dphy - rockchip,rv1126-dsi-dphy -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 2/9] dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> Document a compatible string for the rk3506 dsi-dphy. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml index 46e64fa293d5..83e7c825860c 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -18,6 +18,7 @@ properties: - rockchip,px30-dsi-dphy - rockchip,rk3128-dsi-dphy - rockchip,rk3368-dsi-dphy + - rockchip,rk3506-dsi-dphy - rockchip,rk3568-dsi-dphy - rockchip,rv1126-dsi-dphy -- 2.51.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 2/9] dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> Document a compatible string for the rk3506 dsi-dphy. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml index 46e64fa293d5..83e7c825860c 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -18,6 +18,7 @@ properties: - rockchip,px30-dsi-dphy - rockchip,rk3128-dsi-dphy - rockchip,rk3368-dsi-dphy + - rockchip,rk3506-dsi-dphy - rockchip,rk3568-dsi-dphy - rockchip,rv1126-dsi-dphy -- 2.51.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 2/9] dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 17:27 ` Conor Dooley -1 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:27 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 2/9] dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 @ 2025-11-06 17:27 ` Conor Dooley 0 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:27 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1.1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 170 bytes --] _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 2/9] dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 @ 2025-11-06 17:27 ` Conor Dooley 0 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:27 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1.1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 112 bytes --] -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 3/9] dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 2025-11-06 2:06 ` Chaoyi Chen (?) (?) @ 2025-11-06 2:06 ` Chaoyi Chen -1 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> Document a compatible string for the rk3506 mipi-dsi. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml index c59df3c1a3f7..d949750a3afd 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -73,6 +73,7 @@ allOf: enum: - rockchip,px30-mipi-dsi - rockchip,rk3128-mipi-dsi + - rockchip,rk3506-mipi-dsi - rockchip,rk3568-mipi-dsi - rockchip,rv1126-mipi-dsi -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 3/9] dt-bindings: display: rockchip, dw-mipi-dsi: Add compatible for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> Document a compatible string for the rk3506 mipi-dsi. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml index c59df3c1a3f7..d949750a3afd 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -73,6 +73,7 @@ allOf: enum: - rockchip,px30-mipi-dsi - rockchip,rk3128-mipi-dsi + - rockchip,rk3506-mipi-dsi - rockchip,rk3568-mipi-dsi - rockchip,rv1126-mipi-dsi -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 3/9] dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> Document a compatible string for the rk3506 mipi-dsi. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml index c59df3c1a3f7..d949750a3afd 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -73,6 +73,7 @@ allOf: enum: - rockchip,px30-mipi-dsi - rockchip,rk3128-mipi-dsi + - rockchip,rk3506-mipi-dsi - rockchip,rk3568-mipi-dsi - rockchip,rv1126-mipi-dsi -- 2.51.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 3/9] dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> Document a compatible string for the rk3506 mipi-dsi. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml index c59df3c1a3f7..d949750a3afd 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -73,6 +73,7 @@ allOf: enum: - rockchip,px30-mipi-dsi - rockchip,rk3128-mipi-dsi + - rockchip,rk3506-mipi-dsi - rockchip,rk3568-mipi-dsi - rockchip,rv1126-mipi-dsi -- 2.51.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 3/9] dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 17:27 ` Conor Dooley -1 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:27 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/9] dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 @ 2025-11-06 17:27 ` Conor Dooley 0 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:27 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1.1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 170 bytes --] _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 3/9] dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 @ 2025-11-06 17:27 ` Conor Dooley 0 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:27 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1.1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 112 bytes --] -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 4/9] dt-bindings: display: rockchip,vop: Add compatible for rk3506 2025-11-06 2:06 ` Chaoyi Chen (?) (?) @ 2025-11-06 2:06 ` Chaoyi Chen -1 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The rk3506 VOP has adopted a new implementation. Add a new compatible string for it. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../devicetree/bindings/display/rockchip/rockchip-vop.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml index 8b5f58103dda..fdf4b1109da2 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml @@ -31,6 +31,7 @@ properties: - rockchip,rk3368-vop - rockchip,rk3399-vop-big - rockchip,rk3399-vop-lit + - rockchip,rk3506-vop - rockchip,rv1126-vop reg: -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 4/9] dt-bindings: display: rockchip, vop: Add compatible for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The rk3506 VOP has adopted a new implementation. Add a new compatible string for it. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../devicetree/bindings/display/rockchip/rockchip-vop.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml index 8b5f58103dda..fdf4b1109da2 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml @@ -31,6 +31,7 @@ properties: - rockchip,rk3368-vop - rockchip,rk3399-vop-big - rockchip,rk3399-vop-lit + - rockchip,rk3506-vop - rockchip,rv1126-vop reg: -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 4/9] dt-bindings: display: rockchip,vop: Add compatible for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The rk3506 VOP has adopted a new implementation. Add a new compatible string for it. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../devicetree/bindings/display/rockchip/rockchip-vop.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml index 8b5f58103dda..fdf4b1109da2 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml @@ -31,6 +31,7 @@ properties: - rockchip,rk3368-vop - rockchip,rk3399-vop-big - rockchip,rk3399-vop-lit + - rockchip,rk3506-vop - rockchip,rv1126-vop reg: -- 2.51.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 4/9] dt-bindings: display: rockchip,vop: Add compatible for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The rk3506 VOP has adopted a new implementation. Add a new compatible string for it. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../devicetree/bindings/display/rockchip/rockchip-vop.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml index 8b5f58103dda..fdf4b1109da2 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml @@ -31,6 +31,7 @@ properties: - rockchip,rk3368-vop - rockchip,rk3399-vop-big - rockchip,rk3399-vop-lit + - rockchip,rk3506-vop - rockchip,rv1126-vop reg: -- 2.51.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 4/9] dt-bindings: display: rockchip,vop: Add compatible for rk3506 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 17:27 ` Conor Dooley -1 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:27 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 4/9] dt-bindings: display: rockchip,vop: Add compatible for rk3506 @ 2025-11-06 17:27 ` Conor Dooley 0 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:27 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1.1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 170 bytes --] _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 4/9] dt-bindings: display: rockchip,vop: Add compatible for rk3506 @ 2025-11-06 17:27 ` Conor Dooley 0 siblings, 0 replies; 71+ messages in thread From: Conor Dooley @ 2025-11-06 17:27 UTC (permalink / raw) To: Chaoyi Chen Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen [-- Attachment #1.1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 112 bytes --] -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 5/9] drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 2:06 ` Chaoyi Chen -1 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> W552946AAA is a panel by Wanchanglong. This panel utilizes the Ilitek ILI9881D controller. W552946AAA is similar to W552946ABA, but the W552946AAA only uses 2 lanes. Tested on rk3506g-evb1-v10. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 225 ++++++++++++++++++ 1 file changed, 225 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c index ad4993b2f92a..9b3e9450808d 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c @@ -820,6 +820,204 @@ static const struct ili9881c_instr tl050hdv35_init[] = { ILI9881C_COMMAND_INSTR(0xd3, 0x39), }; +static const struct ili9881c_instr w552946aaa_init[] = { + ILI9881C_SWITCH_PAGE_INSTR(3), + ILI9881C_COMMAND_INSTR(0x01, 0x00), + ILI9881C_COMMAND_INSTR(0x02, 0x00), + ILI9881C_COMMAND_INSTR(0x03, 0x53), + ILI9881C_COMMAND_INSTR(0x04, 0x53), + ILI9881C_COMMAND_INSTR(0x05, 0x13), + ILI9881C_COMMAND_INSTR(0x06, 0x04), + ILI9881C_COMMAND_INSTR(0x07, 0x02), + ILI9881C_COMMAND_INSTR(0x08, 0x02), + ILI9881C_COMMAND_INSTR(0x09, 0x00), + ILI9881C_COMMAND_INSTR(0x0a, 0x00), + ILI9881C_COMMAND_INSTR(0x0b, 0x00), + ILI9881C_COMMAND_INSTR(0x0c, 0x00), + ILI9881C_COMMAND_INSTR(0x0d, 0x00), + ILI9881C_COMMAND_INSTR(0x0e, 0x00), + ILI9881C_COMMAND_INSTR(0x0f, 0x00), + ILI9881C_COMMAND_INSTR(0x10, 0x00), + ILI9881C_COMMAND_INSTR(0x11, 0x00), + ILI9881C_COMMAND_INSTR(0x12, 0x00), + ILI9881C_COMMAND_INSTR(0x13, 0x00), + ILI9881C_COMMAND_INSTR(0x14, 0x00), + ILI9881C_COMMAND_INSTR(0x15, 0x08), + ILI9881C_COMMAND_INSTR(0x16, 0x10), + ILI9881C_COMMAND_INSTR(0x17, 0x00), + ILI9881C_COMMAND_INSTR(0x18, 0x08), + ILI9881C_COMMAND_INSTR(0x19, 0x00), + ILI9881C_COMMAND_INSTR(0x1a, 0x00), + ILI9881C_COMMAND_INSTR(0x1b, 0x00), + ILI9881C_COMMAND_INSTR(0x1c, 0x00), + ILI9881C_COMMAND_INSTR(0x1d, 0x00), + ILI9881C_COMMAND_INSTR(0x1e, 0xc0), + ILI9881C_COMMAND_INSTR(0x1f, 0x80), + ILI9881C_COMMAND_INSTR(0x20, 0x02), + ILI9881C_COMMAND_INSTR(0x21, 0x09), + ILI9881C_COMMAND_INSTR(0x22, 0x00), + ILI9881C_COMMAND_INSTR(0x23, 0x00), + ILI9881C_COMMAND_INSTR(0x24, 0x00), + ILI9881C_COMMAND_INSTR(0x25, 0x00), + ILI9881C_COMMAND_INSTR(0x26, 0x00), + ILI9881C_COMMAND_INSTR(0x27, 0x00), + ILI9881C_COMMAND_INSTR(0x28, 0x55), + ILI9881C_COMMAND_INSTR(0x29, 0x03), + ILI9881C_COMMAND_INSTR(0x2a, 0x00), + ILI9881C_COMMAND_INSTR(0x2b, 0x00), + ILI9881C_COMMAND_INSTR(0x2c, 0x00), + ILI9881C_COMMAND_INSTR(0x2d, 0x00), + ILI9881C_COMMAND_INSTR(0x2e, 0x00), + ILI9881C_COMMAND_INSTR(0x2f, 0x00), + ILI9881C_COMMAND_INSTR(0x30, 0x00), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x32, 0x00), + ILI9881C_COMMAND_INSTR(0x33, 0x00), + ILI9881C_COMMAND_INSTR(0x34, 0x04), + ILI9881C_COMMAND_INSTR(0x35, 0x05), + ILI9881C_COMMAND_INSTR(0x36, 0x05), + ILI9881C_COMMAND_INSTR(0x37, 0x00), + ILI9881C_COMMAND_INSTR(0x38, 0x3c), + ILI9881C_COMMAND_INSTR(0x39, 0x35), + ILI9881C_COMMAND_INSTR(0x3a, 0x00), + ILI9881C_COMMAND_INSTR(0x3b, 0x40), + ILI9881C_COMMAND_INSTR(0x3c, 0x00), + ILI9881C_COMMAND_INSTR(0x3d, 0x00), + ILI9881C_COMMAND_INSTR(0x3e, 0x00), + ILI9881C_COMMAND_INSTR(0x3f, 0x00), + ILI9881C_COMMAND_INSTR(0x40, 0x00), + ILI9881C_COMMAND_INSTR(0x41, 0x88), + ILI9881C_COMMAND_INSTR(0x42, 0x00), + ILI9881C_COMMAND_INSTR(0x43, 0x00), + ILI9881C_COMMAND_INSTR(0x44, 0x1f), + ILI9881C_COMMAND_INSTR(0x50, 0x01), + ILI9881C_COMMAND_INSTR(0x51, 0x23), + ILI9881C_COMMAND_INSTR(0x52, 0x45), + ILI9881C_COMMAND_INSTR(0x53, 0x67), + ILI9881C_COMMAND_INSTR(0x54, 0x89), + ILI9881C_COMMAND_INSTR(0x55, 0xab), + ILI9881C_COMMAND_INSTR(0x56, 0x01), + ILI9881C_COMMAND_INSTR(0x57, 0x23), + ILI9881C_COMMAND_INSTR(0x58, 0x45), + ILI9881C_COMMAND_INSTR(0x59, 0x67), + ILI9881C_COMMAND_INSTR(0x5a, 0x89), + ILI9881C_COMMAND_INSTR(0x5b, 0xab), + ILI9881C_COMMAND_INSTR(0x5c, 0xcd), + ILI9881C_COMMAND_INSTR(0x5d, 0xef), + ILI9881C_COMMAND_INSTR(0x5e, 0x03), + ILI9881C_COMMAND_INSTR(0x5f, 0x14), + ILI9881C_COMMAND_INSTR(0x60, 0x15), + ILI9881C_COMMAND_INSTR(0x61, 0x0c), + ILI9881C_COMMAND_INSTR(0x62, 0x0d), + ILI9881C_COMMAND_INSTR(0x63, 0x0e), + ILI9881C_COMMAND_INSTR(0x64, 0x0f), + ILI9881C_COMMAND_INSTR(0x65, 0x10), + ILI9881C_COMMAND_INSTR(0x66, 0x11), + ILI9881C_COMMAND_INSTR(0x67, 0x08), + ILI9881C_COMMAND_INSTR(0x68, 0x02), + ILI9881C_COMMAND_INSTR(0x69, 0x0a), + ILI9881C_COMMAND_INSTR(0x6a, 0x02), + ILI9881C_COMMAND_INSTR(0x6b, 0x02), + ILI9881C_COMMAND_INSTR(0x6c, 0x02), + ILI9881C_COMMAND_INSTR(0x6d, 0x02), + ILI9881C_COMMAND_INSTR(0x6e, 0x02), + ILI9881C_COMMAND_INSTR(0x6f, 0x02), + ILI9881C_COMMAND_INSTR(0x70, 0x02), + ILI9881C_COMMAND_INSTR(0x71, 0x02), + ILI9881C_COMMAND_INSTR(0x72, 0x06), + ILI9881C_COMMAND_INSTR(0x73, 0x02), + ILI9881C_COMMAND_INSTR(0x74, 0x02), + ILI9881C_COMMAND_INSTR(0x75, 0x14), + ILI9881C_COMMAND_INSTR(0x76, 0x15), + ILI9881C_COMMAND_INSTR(0x77, 0x0f), + ILI9881C_COMMAND_INSTR(0x78, 0x0e), + ILI9881C_COMMAND_INSTR(0x79, 0x0d), + ILI9881C_COMMAND_INSTR(0x7a, 0x0c), + ILI9881C_COMMAND_INSTR(0x7b, 0x11), + ILI9881C_COMMAND_INSTR(0x7c, 0x10), + ILI9881C_COMMAND_INSTR(0x7d, 0x06), + ILI9881C_COMMAND_INSTR(0x7e, 0x02), + ILI9881C_COMMAND_INSTR(0x7f, 0x0a), + ILI9881C_COMMAND_INSTR(0x80, 0x02), + ILI9881C_COMMAND_INSTR(0x81, 0x02), + ILI9881C_COMMAND_INSTR(0x82, 0x02), + ILI9881C_COMMAND_INSTR(0x83, 0x02), + ILI9881C_COMMAND_INSTR(0x84, 0x02), + ILI9881C_COMMAND_INSTR(0x85, 0x02), + ILI9881C_COMMAND_INSTR(0x86, 0x02), + ILI9881C_COMMAND_INSTR(0x87, 0x02), + ILI9881C_COMMAND_INSTR(0x88, 0x08), + ILI9881C_COMMAND_INSTR(0x89, 0x02), + ILI9881C_COMMAND_INSTR(0x8a, 0x02), + ILI9881C_SWITCH_PAGE_INSTR(4), + ILI9881C_COMMAND_INSTR(0x00, 0x80), + ILI9881C_COMMAND_INSTR(0x70, 0x00), + ILI9881C_COMMAND_INSTR(0x71, 0x00), + ILI9881C_COMMAND_INSTR(0x66, 0xfe), + ILI9881C_COMMAND_INSTR(0x82, 0x15), + ILI9881C_COMMAND_INSTR(0x84, 0x15), + ILI9881C_COMMAND_INSTR(0x85, 0x15), + ILI9881C_COMMAND_INSTR(0x3a, 0x24), + ILI9881C_COMMAND_INSTR(0x32, 0xac), + ILI9881C_COMMAND_INSTR(0x8c, 0x80), + ILI9881C_COMMAND_INSTR(0x3c, 0xf5), + ILI9881C_COMMAND_INSTR(0x88, 0x33), + ILI9881C_SWITCH_PAGE_INSTR(1), + ILI9881C_COMMAND_INSTR(0x22, 0x0a), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x53, 0x78), + ILI9881C_COMMAND_INSTR(0x55, 0x7b), + ILI9881C_COMMAND_INSTR(0x60, 0x20), + ILI9881C_COMMAND_INSTR(0x61, 0x00), + ILI9881C_COMMAND_INSTR(0x62, 0x0d), + ILI9881C_COMMAND_INSTR(0x63, 0x00), + ILI9881C_COMMAND_INSTR(0xa0, 0x00), + ILI9881C_COMMAND_INSTR(0xa1, 0x10), + ILI9881C_COMMAND_INSTR(0xa2, 0x1c), + ILI9881C_COMMAND_INSTR(0xa3, 0x13), + ILI9881C_COMMAND_INSTR(0xa4, 0x15), + ILI9881C_COMMAND_INSTR(0xa5, 0x26), + ILI9881C_COMMAND_INSTR(0xa6, 0x1a), + ILI9881C_COMMAND_INSTR(0xa7, 0x1d), + ILI9881C_COMMAND_INSTR(0xa8, 0x67), + ILI9881C_COMMAND_INSTR(0xa9, 0x1c), + ILI9881C_COMMAND_INSTR(0xaa, 0x29), + ILI9881C_COMMAND_INSTR(0xab, 0x5b), + ILI9881C_COMMAND_INSTR(0xac, 0x26), + ILI9881C_COMMAND_INSTR(0xad, 0x28), + ILI9881C_COMMAND_INSTR(0xae, 0x5c), + ILI9881C_COMMAND_INSTR(0xaf, 0x30), + ILI9881C_COMMAND_INSTR(0xb0, 0x31), + ILI9881C_COMMAND_INSTR(0xb1, 0x32), + ILI9881C_COMMAND_INSTR(0xb2, 0x00), + ILI9881C_COMMAND_INSTR(0xb1, 0x2e), + ILI9881C_COMMAND_INSTR(0xb2, 0x32), + ILI9881C_COMMAND_INSTR(0xb3, 0x00), + ILI9881C_COMMAND_INSTR(0xb6, 0x02), + ILI9881C_COMMAND_INSTR(0xb7, 0x03), + ILI9881C_COMMAND_INSTR(0xc0, 0x00), + ILI9881C_COMMAND_INSTR(0xc1, 0x10), + ILI9881C_COMMAND_INSTR(0xc2, 0x1c), + ILI9881C_COMMAND_INSTR(0xc3, 0x13), + ILI9881C_COMMAND_INSTR(0xc4, 0x15), + ILI9881C_COMMAND_INSTR(0xc5, 0x26), + ILI9881C_COMMAND_INSTR(0xc6, 0x1a), + ILI9881C_COMMAND_INSTR(0xc7, 0x1d), + ILI9881C_COMMAND_INSTR(0xc8, 0x67), + ILI9881C_COMMAND_INSTR(0xc9, 0x1c), + ILI9881C_COMMAND_INSTR(0xca, 0x29), + ILI9881C_COMMAND_INSTR(0xcb, 0x5b), + ILI9881C_COMMAND_INSTR(0xcc, 0x26), + ILI9881C_COMMAND_INSTR(0xcd, 0x28), + ILI9881C_COMMAND_INSTR(0xce, 0x5c), + ILI9881C_COMMAND_INSTR(0xcf, 0x30), + ILI9881C_COMMAND_INSTR(0xd0, 0x31), + ILI9881C_COMMAND_INSTR(0xd1, 0x2e), + ILI9881C_COMMAND_INSTR(0xd2, 0x32), + ILI9881C_COMMAND_INSTR(0xd3, 0x00), + ILI9881C_SWITCH_PAGE_INSTR(0), +}; + static const struct ili9881c_instr w552946ab_init[] = { ILI9881C_SWITCH_PAGE_INSTR(3), ILI9881C_COMMAND_INSTR(0x01, 0x00), @@ -1772,6 +1970,23 @@ static const struct drm_display_mode tl050hdv35_default_mode = { .height_mm = 110, }; +static const struct drm_display_mode w552946aaa_default_mode = { + .clock = 65000, + + .hdisplay = 720, + .hsync_start = 720 + 52, + .hsync_end = 720 + 52 + 8, + .htotal = 720 + 52 + 8 + 48, + + .vdisplay = 1280, + .vsync_start = 1280 + 16, + .vsync_end = 1280 + 16 + 6, + .vtotal = 1280 + 16 + 6 + 15, + + .width_mm = 68, + .height_mm = 121, +}; + static const struct drm_display_mode w552946aba_default_mode = { .clock = 64000, @@ -1983,6 +2198,15 @@ static const struct ili9881c_desc tl050hdv35_desc = { .default_address_mode = 0x03, }; +static const struct ili9881c_desc w552946aaa_desc = { + .init = w552946aaa_init, + .init_length = ARRAY_SIZE(w552946aaa_init), + .mode = &w552946aaa_default_mode, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET, + .lanes = 2, +}; + static const struct ili9881c_desc w552946aba_desc = { .init = w552946ab_init, .init_length = ARRAY_SIZE(w552946ab_init), @@ -2023,6 +2247,7 @@ static const struct of_device_id ili9881c_of_match[] = { { .compatible = "feixin,k101-im2byl02", .data = &k101_im2byl02_desc }, { .compatible = "startek,kd050hdfia020", .data = &kd050hdfia020_desc }, { .compatible = "tdo,tl050hdv35", .data = &tl050hdv35_desc }, + { .compatible = "wanchanglong,w552946aaa", .data = &w552946aaa_desc }, { .compatible = "wanchanglong,w552946aba", .data = &w552946aba_desc }, { .compatible = "ampire,am8001280g", .data = &am8001280g_desc }, { .compatible = "raspberrypi,dsi-7inch", &rpi_7inch_desc }, -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 5/9] drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> W552946AAA is a panel by Wanchanglong. This panel utilizes the Ilitek ILI9881D controller. W552946AAA is similar to W552946ABA, but the W552946AAA only uses 2 lanes. Tested on rk3506g-evb1-v10. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 225 ++++++++++++++++++ 1 file changed, 225 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c index ad4993b2f92a..9b3e9450808d 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c @@ -820,6 +820,204 @@ static const struct ili9881c_instr tl050hdv35_init[] = { ILI9881C_COMMAND_INSTR(0xd3, 0x39), }; +static const struct ili9881c_instr w552946aaa_init[] = { + ILI9881C_SWITCH_PAGE_INSTR(3), + ILI9881C_COMMAND_INSTR(0x01, 0x00), + ILI9881C_COMMAND_INSTR(0x02, 0x00), + ILI9881C_COMMAND_INSTR(0x03, 0x53), + ILI9881C_COMMAND_INSTR(0x04, 0x53), + ILI9881C_COMMAND_INSTR(0x05, 0x13), + ILI9881C_COMMAND_INSTR(0x06, 0x04), + ILI9881C_COMMAND_INSTR(0x07, 0x02), + ILI9881C_COMMAND_INSTR(0x08, 0x02), + ILI9881C_COMMAND_INSTR(0x09, 0x00), + ILI9881C_COMMAND_INSTR(0x0a, 0x00), + ILI9881C_COMMAND_INSTR(0x0b, 0x00), + ILI9881C_COMMAND_INSTR(0x0c, 0x00), + ILI9881C_COMMAND_INSTR(0x0d, 0x00), + ILI9881C_COMMAND_INSTR(0x0e, 0x00), + ILI9881C_COMMAND_INSTR(0x0f, 0x00), + ILI9881C_COMMAND_INSTR(0x10, 0x00), + ILI9881C_COMMAND_INSTR(0x11, 0x00), + ILI9881C_COMMAND_INSTR(0x12, 0x00), + ILI9881C_COMMAND_INSTR(0x13, 0x00), + ILI9881C_COMMAND_INSTR(0x14, 0x00), + ILI9881C_COMMAND_INSTR(0x15, 0x08), + ILI9881C_COMMAND_INSTR(0x16, 0x10), + ILI9881C_COMMAND_INSTR(0x17, 0x00), + ILI9881C_COMMAND_INSTR(0x18, 0x08), + ILI9881C_COMMAND_INSTR(0x19, 0x00), + ILI9881C_COMMAND_INSTR(0x1a, 0x00), + ILI9881C_COMMAND_INSTR(0x1b, 0x00), + ILI9881C_COMMAND_INSTR(0x1c, 0x00), + ILI9881C_COMMAND_INSTR(0x1d, 0x00), + ILI9881C_COMMAND_INSTR(0x1e, 0xc0), + ILI9881C_COMMAND_INSTR(0x1f, 0x80), + ILI9881C_COMMAND_INSTR(0x20, 0x02), + ILI9881C_COMMAND_INSTR(0x21, 0x09), + ILI9881C_COMMAND_INSTR(0x22, 0x00), + ILI9881C_COMMAND_INSTR(0x23, 0x00), + ILI9881C_COMMAND_INSTR(0x24, 0x00), + ILI9881C_COMMAND_INSTR(0x25, 0x00), + ILI9881C_COMMAND_INSTR(0x26, 0x00), + ILI9881C_COMMAND_INSTR(0x27, 0x00), + ILI9881C_COMMAND_INSTR(0x28, 0x55), + ILI9881C_COMMAND_INSTR(0x29, 0x03), + ILI9881C_COMMAND_INSTR(0x2a, 0x00), + ILI9881C_COMMAND_INSTR(0x2b, 0x00), + ILI9881C_COMMAND_INSTR(0x2c, 0x00), + ILI9881C_COMMAND_INSTR(0x2d, 0x00), + ILI9881C_COMMAND_INSTR(0x2e, 0x00), + ILI9881C_COMMAND_INSTR(0x2f, 0x00), + ILI9881C_COMMAND_INSTR(0x30, 0x00), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x32, 0x00), + ILI9881C_COMMAND_INSTR(0x33, 0x00), + ILI9881C_COMMAND_INSTR(0x34, 0x04), + ILI9881C_COMMAND_INSTR(0x35, 0x05), + ILI9881C_COMMAND_INSTR(0x36, 0x05), + ILI9881C_COMMAND_INSTR(0x37, 0x00), + ILI9881C_COMMAND_INSTR(0x38, 0x3c), + ILI9881C_COMMAND_INSTR(0x39, 0x35), + ILI9881C_COMMAND_INSTR(0x3a, 0x00), + ILI9881C_COMMAND_INSTR(0x3b, 0x40), + ILI9881C_COMMAND_INSTR(0x3c, 0x00), + ILI9881C_COMMAND_INSTR(0x3d, 0x00), + ILI9881C_COMMAND_INSTR(0x3e, 0x00), + ILI9881C_COMMAND_INSTR(0x3f, 0x00), + ILI9881C_COMMAND_INSTR(0x40, 0x00), + ILI9881C_COMMAND_INSTR(0x41, 0x88), + ILI9881C_COMMAND_INSTR(0x42, 0x00), + ILI9881C_COMMAND_INSTR(0x43, 0x00), + ILI9881C_COMMAND_INSTR(0x44, 0x1f), + ILI9881C_COMMAND_INSTR(0x50, 0x01), + ILI9881C_COMMAND_INSTR(0x51, 0x23), + ILI9881C_COMMAND_INSTR(0x52, 0x45), + ILI9881C_COMMAND_INSTR(0x53, 0x67), + ILI9881C_COMMAND_INSTR(0x54, 0x89), + ILI9881C_COMMAND_INSTR(0x55, 0xab), + ILI9881C_COMMAND_INSTR(0x56, 0x01), + ILI9881C_COMMAND_INSTR(0x57, 0x23), + ILI9881C_COMMAND_INSTR(0x58, 0x45), + ILI9881C_COMMAND_INSTR(0x59, 0x67), + ILI9881C_COMMAND_INSTR(0x5a, 0x89), + ILI9881C_COMMAND_INSTR(0x5b, 0xab), + ILI9881C_COMMAND_INSTR(0x5c, 0xcd), + ILI9881C_COMMAND_INSTR(0x5d, 0xef), + ILI9881C_COMMAND_INSTR(0x5e, 0x03), + ILI9881C_COMMAND_INSTR(0x5f, 0x14), + ILI9881C_COMMAND_INSTR(0x60, 0x15), + ILI9881C_COMMAND_INSTR(0x61, 0x0c), + ILI9881C_COMMAND_INSTR(0x62, 0x0d), + ILI9881C_COMMAND_INSTR(0x63, 0x0e), + ILI9881C_COMMAND_INSTR(0x64, 0x0f), + ILI9881C_COMMAND_INSTR(0x65, 0x10), + ILI9881C_COMMAND_INSTR(0x66, 0x11), + ILI9881C_COMMAND_INSTR(0x67, 0x08), + ILI9881C_COMMAND_INSTR(0x68, 0x02), + ILI9881C_COMMAND_INSTR(0x69, 0x0a), + ILI9881C_COMMAND_INSTR(0x6a, 0x02), + ILI9881C_COMMAND_INSTR(0x6b, 0x02), + ILI9881C_COMMAND_INSTR(0x6c, 0x02), + ILI9881C_COMMAND_INSTR(0x6d, 0x02), + ILI9881C_COMMAND_INSTR(0x6e, 0x02), + ILI9881C_COMMAND_INSTR(0x6f, 0x02), + ILI9881C_COMMAND_INSTR(0x70, 0x02), + ILI9881C_COMMAND_INSTR(0x71, 0x02), + ILI9881C_COMMAND_INSTR(0x72, 0x06), + ILI9881C_COMMAND_INSTR(0x73, 0x02), + ILI9881C_COMMAND_INSTR(0x74, 0x02), + ILI9881C_COMMAND_INSTR(0x75, 0x14), + ILI9881C_COMMAND_INSTR(0x76, 0x15), + ILI9881C_COMMAND_INSTR(0x77, 0x0f), + ILI9881C_COMMAND_INSTR(0x78, 0x0e), + ILI9881C_COMMAND_INSTR(0x79, 0x0d), + ILI9881C_COMMAND_INSTR(0x7a, 0x0c), + ILI9881C_COMMAND_INSTR(0x7b, 0x11), + ILI9881C_COMMAND_INSTR(0x7c, 0x10), + ILI9881C_COMMAND_INSTR(0x7d, 0x06), + ILI9881C_COMMAND_INSTR(0x7e, 0x02), + ILI9881C_COMMAND_INSTR(0x7f, 0x0a), + ILI9881C_COMMAND_INSTR(0x80, 0x02), + ILI9881C_COMMAND_INSTR(0x81, 0x02), + ILI9881C_COMMAND_INSTR(0x82, 0x02), + ILI9881C_COMMAND_INSTR(0x83, 0x02), + ILI9881C_COMMAND_INSTR(0x84, 0x02), + ILI9881C_COMMAND_INSTR(0x85, 0x02), + ILI9881C_COMMAND_INSTR(0x86, 0x02), + ILI9881C_COMMAND_INSTR(0x87, 0x02), + ILI9881C_COMMAND_INSTR(0x88, 0x08), + ILI9881C_COMMAND_INSTR(0x89, 0x02), + ILI9881C_COMMAND_INSTR(0x8a, 0x02), + ILI9881C_SWITCH_PAGE_INSTR(4), + ILI9881C_COMMAND_INSTR(0x00, 0x80), + ILI9881C_COMMAND_INSTR(0x70, 0x00), + ILI9881C_COMMAND_INSTR(0x71, 0x00), + ILI9881C_COMMAND_INSTR(0x66, 0xfe), + ILI9881C_COMMAND_INSTR(0x82, 0x15), + ILI9881C_COMMAND_INSTR(0x84, 0x15), + ILI9881C_COMMAND_INSTR(0x85, 0x15), + ILI9881C_COMMAND_INSTR(0x3a, 0x24), + ILI9881C_COMMAND_INSTR(0x32, 0xac), + ILI9881C_COMMAND_INSTR(0x8c, 0x80), + ILI9881C_COMMAND_INSTR(0x3c, 0xf5), + ILI9881C_COMMAND_INSTR(0x88, 0x33), + ILI9881C_SWITCH_PAGE_INSTR(1), + ILI9881C_COMMAND_INSTR(0x22, 0x0a), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x53, 0x78), + ILI9881C_COMMAND_INSTR(0x55, 0x7b), + ILI9881C_COMMAND_INSTR(0x60, 0x20), + ILI9881C_COMMAND_INSTR(0x61, 0x00), + ILI9881C_COMMAND_INSTR(0x62, 0x0d), + ILI9881C_COMMAND_INSTR(0x63, 0x00), + ILI9881C_COMMAND_INSTR(0xa0, 0x00), + ILI9881C_COMMAND_INSTR(0xa1, 0x10), + ILI9881C_COMMAND_INSTR(0xa2, 0x1c), + ILI9881C_COMMAND_INSTR(0xa3, 0x13), + ILI9881C_COMMAND_INSTR(0xa4, 0x15), + ILI9881C_COMMAND_INSTR(0xa5, 0x26), + ILI9881C_COMMAND_INSTR(0xa6, 0x1a), + ILI9881C_COMMAND_INSTR(0xa7, 0x1d), + ILI9881C_COMMAND_INSTR(0xa8, 0x67), + ILI9881C_COMMAND_INSTR(0xa9, 0x1c), + ILI9881C_COMMAND_INSTR(0xaa, 0x29), + ILI9881C_COMMAND_INSTR(0xab, 0x5b), + ILI9881C_COMMAND_INSTR(0xac, 0x26), + ILI9881C_COMMAND_INSTR(0xad, 0x28), + ILI9881C_COMMAND_INSTR(0xae, 0x5c), + ILI9881C_COMMAND_INSTR(0xaf, 0x30), + ILI9881C_COMMAND_INSTR(0xb0, 0x31), + ILI9881C_COMMAND_INSTR(0xb1, 0x32), + ILI9881C_COMMAND_INSTR(0xb2, 0x00), + ILI9881C_COMMAND_INSTR(0xb1, 0x2e), + ILI9881C_COMMAND_INSTR(0xb2, 0x32), + ILI9881C_COMMAND_INSTR(0xb3, 0x00), + ILI9881C_COMMAND_INSTR(0xb6, 0x02), + ILI9881C_COMMAND_INSTR(0xb7, 0x03), + ILI9881C_COMMAND_INSTR(0xc0, 0x00), + ILI9881C_COMMAND_INSTR(0xc1, 0x10), + ILI9881C_COMMAND_INSTR(0xc2, 0x1c), + ILI9881C_COMMAND_INSTR(0xc3, 0x13), + ILI9881C_COMMAND_INSTR(0xc4, 0x15), + ILI9881C_COMMAND_INSTR(0xc5, 0x26), + ILI9881C_COMMAND_INSTR(0xc6, 0x1a), + ILI9881C_COMMAND_INSTR(0xc7, 0x1d), + ILI9881C_COMMAND_INSTR(0xc8, 0x67), + ILI9881C_COMMAND_INSTR(0xc9, 0x1c), + ILI9881C_COMMAND_INSTR(0xca, 0x29), + ILI9881C_COMMAND_INSTR(0xcb, 0x5b), + ILI9881C_COMMAND_INSTR(0xcc, 0x26), + ILI9881C_COMMAND_INSTR(0xcd, 0x28), + ILI9881C_COMMAND_INSTR(0xce, 0x5c), + ILI9881C_COMMAND_INSTR(0xcf, 0x30), + ILI9881C_COMMAND_INSTR(0xd0, 0x31), + ILI9881C_COMMAND_INSTR(0xd1, 0x2e), + ILI9881C_COMMAND_INSTR(0xd2, 0x32), + ILI9881C_COMMAND_INSTR(0xd3, 0x00), + ILI9881C_SWITCH_PAGE_INSTR(0), +}; + static const struct ili9881c_instr w552946ab_init[] = { ILI9881C_SWITCH_PAGE_INSTR(3), ILI9881C_COMMAND_INSTR(0x01, 0x00), @@ -1772,6 +1970,23 @@ static const struct drm_display_mode tl050hdv35_default_mode = { .height_mm = 110, }; +static const struct drm_display_mode w552946aaa_default_mode = { + .clock = 65000, + + .hdisplay = 720, + .hsync_start = 720 + 52, + .hsync_end = 720 + 52 + 8, + .htotal = 720 + 52 + 8 + 48, + + .vdisplay = 1280, + .vsync_start = 1280 + 16, + .vsync_end = 1280 + 16 + 6, + .vtotal = 1280 + 16 + 6 + 15, + + .width_mm = 68, + .height_mm = 121, +}; + static const struct drm_display_mode w552946aba_default_mode = { .clock = 64000, @@ -1983,6 +2198,15 @@ static const struct ili9881c_desc tl050hdv35_desc = { .default_address_mode = 0x03, }; +static const struct ili9881c_desc w552946aaa_desc = { + .init = w552946aaa_init, + .init_length = ARRAY_SIZE(w552946aaa_init), + .mode = &w552946aaa_default_mode, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET, + .lanes = 2, +}; + static const struct ili9881c_desc w552946aba_desc = { .init = w552946ab_init, .init_length = ARRAY_SIZE(w552946ab_init), @@ -2023,6 +2247,7 @@ static const struct of_device_id ili9881c_of_match[] = { { .compatible = "feixin,k101-im2byl02", .data = &k101_im2byl02_desc }, { .compatible = "startek,kd050hdfia020", .data = &kd050hdfia020_desc }, { .compatible = "tdo,tl050hdv35", .data = &tl050hdv35_desc }, + { .compatible = "wanchanglong,w552946aaa", .data = &w552946aaa_desc }, { .compatible = "wanchanglong,w552946aba", .data = &w552946aba_desc }, { .compatible = "ampire,am8001280g", .data = &am8001280g_desc }, { .compatible = "raspberrypi,dsi-7inch", &rpi_7inch_desc }, -- 2.51.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 5/9] drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> W552946AAA is a panel by Wanchanglong. This panel utilizes the Ilitek ILI9881D controller. W552946AAA is similar to W552946ABA, but the W552946AAA only uses 2 lanes. Tested on rk3506g-evb1-v10. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 225 ++++++++++++++++++ 1 file changed, 225 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c index ad4993b2f92a..9b3e9450808d 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c @@ -820,6 +820,204 @@ static const struct ili9881c_instr tl050hdv35_init[] = { ILI9881C_COMMAND_INSTR(0xd3, 0x39), }; +static const struct ili9881c_instr w552946aaa_init[] = { + ILI9881C_SWITCH_PAGE_INSTR(3), + ILI9881C_COMMAND_INSTR(0x01, 0x00), + ILI9881C_COMMAND_INSTR(0x02, 0x00), + ILI9881C_COMMAND_INSTR(0x03, 0x53), + ILI9881C_COMMAND_INSTR(0x04, 0x53), + ILI9881C_COMMAND_INSTR(0x05, 0x13), + ILI9881C_COMMAND_INSTR(0x06, 0x04), + ILI9881C_COMMAND_INSTR(0x07, 0x02), + ILI9881C_COMMAND_INSTR(0x08, 0x02), + ILI9881C_COMMAND_INSTR(0x09, 0x00), + ILI9881C_COMMAND_INSTR(0x0a, 0x00), + ILI9881C_COMMAND_INSTR(0x0b, 0x00), + ILI9881C_COMMAND_INSTR(0x0c, 0x00), + ILI9881C_COMMAND_INSTR(0x0d, 0x00), + ILI9881C_COMMAND_INSTR(0x0e, 0x00), + ILI9881C_COMMAND_INSTR(0x0f, 0x00), + ILI9881C_COMMAND_INSTR(0x10, 0x00), + ILI9881C_COMMAND_INSTR(0x11, 0x00), + ILI9881C_COMMAND_INSTR(0x12, 0x00), + ILI9881C_COMMAND_INSTR(0x13, 0x00), + ILI9881C_COMMAND_INSTR(0x14, 0x00), + ILI9881C_COMMAND_INSTR(0x15, 0x08), + ILI9881C_COMMAND_INSTR(0x16, 0x10), + ILI9881C_COMMAND_INSTR(0x17, 0x00), + ILI9881C_COMMAND_INSTR(0x18, 0x08), + ILI9881C_COMMAND_INSTR(0x19, 0x00), + ILI9881C_COMMAND_INSTR(0x1a, 0x00), + ILI9881C_COMMAND_INSTR(0x1b, 0x00), + ILI9881C_COMMAND_INSTR(0x1c, 0x00), + ILI9881C_COMMAND_INSTR(0x1d, 0x00), + ILI9881C_COMMAND_INSTR(0x1e, 0xc0), + ILI9881C_COMMAND_INSTR(0x1f, 0x80), + ILI9881C_COMMAND_INSTR(0x20, 0x02), + ILI9881C_COMMAND_INSTR(0x21, 0x09), + ILI9881C_COMMAND_INSTR(0x22, 0x00), + ILI9881C_COMMAND_INSTR(0x23, 0x00), + ILI9881C_COMMAND_INSTR(0x24, 0x00), + ILI9881C_COMMAND_INSTR(0x25, 0x00), + ILI9881C_COMMAND_INSTR(0x26, 0x00), + ILI9881C_COMMAND_INSTR(0x27, 0x00), + ILI9881C_COMMAND_INSTR(0x28, 0x55), + ILI9881C_COMMAND_INSTR(0x29, 0x03), + ILI9881C_COMMAND_INSTR(0x2a, 0x00), + ILI9881C_COMMAND_INSTR(0x2b, 0x00), + ILI9881C_COMMAND_INSTR(0x2c, 0x00), + ILI9881C_COMMAND_INSTR(0x2d, 0x00), + ILI9881C_COMMAND_INSTR(0x2e, 0x00), + ILI9881C_COMMAND_INSTR(0x2f, 0x00), + ILI9881C_COMMAND_INSTR(0x30, 0x00), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x32, 0x00), + ILI9881C_COMMAND_INSTR(0x33, 0x00), + ILI9881C_COMMAND_INSTR(0x34, 0x04), + ILI9881C_COMMAND_INSTR(0x35, 0x05), + ILI9881C_COMMAND_INSTR(0x36, 0x05), + ILI9881C_COMMAND_INSTR(0x37, 0x00), + ILI9881C_COMMAND_INSTR(0x38, 0x3c), + ILI9881C_COMMAND_INSTR(0x39, 0x35), + ILI9881C_COMMAND_INSTR(0x3a, 0x00), + ILI9881C_COMMAND_INSTR(0x3b, 0x40), + ILI9881C_COMMAND_INSTR(0x3c, 0x00), + ILI9881C_COMMAND_INSTR(0x3d, 0x00), + ILI9881C_COMMAND_INSTR(0x3e, 0x00), + ILI9881C_COMMAND_INSTR(0x3f, 0x00), + ILI9881C_COMMAND_INSTR(0x40, 0x00), + ILI9881C_COMMAND_INSTR(0x41, 0x88), + ILI9881C_COMMAND_INSTR(0x42, 0x00), + ILI9881C_COMMAND_INSTR(0x43, 0x00), + ILI9881C_COMMAND_INSTR(0x44, 0x1f), + ILI9881C_COMMAND_INSTR(0x50, 0x01), + ILI9881C_COMMAND_INSTR(0x51, 0x23), + ILI9881C_COMMAND_INSTR(0x52, 0x45), + ILI9881C_COMMAND_INSTR(0x53, 0x67), + ILI9881C_COMMAND_INSTR(0x54, 0x89), + ILI9881C_COMMAND_INSTR(0x55, 0xab), + ILI9881C_COMMAND_INSTR(0x56, 0x01), + ILI9881C_COMMAND_INSTR(0x57, 0x23), + ILI9881C_COMMAND_INSTR(0x58, 0x45), + ILI9881C_COMMAND_INSTR(0x59, 0x67), + ILI9881C_COMMAND_INSTR(0x5a, 0x89), + ILI9881C_COMMAND_INSTR(0x5b, 0xab), + ILI9881C_COMMAND_INSTR(0x5c, 0xcd), + ILI9881C_COMMAND_INSTR(0x5d, 0xef), + ILI9881C_COMMAND_INSTR(0x5e, 0x03), + ILI9881C_COMMAND_INSTR(0x5f, 0x14), + ILI9881C_COMMAND_INSTR(0x60, 0x15), + ILI9881C_COMMAND_INSTR(0x61, 0x0c), + ILI9881C_COMMAND_INSTR(0x62, 0x0d), + ILI9881C_COMMAND_INSTR(0x63, 0x0e), + ILI9881C_COMMAND_INSTR(0x64, 0x0f), + ILI9881C_COMMAND_INSTR(0x65, 0x10), + ILI9881C_COMMAND_INSTR(0x66, 0x11), + ILI9881C_COMMAND_INSTR(0x67, 0x08), + ILI9881C_COMMAND_INSTR(0x68, 0x02), + ILI9881C_COMMAND_INSTR(0x69, 0x0a), + ILI9881C_COMMAND_INSTR(0x6a, 0x02), + ILI9881C_COMMAND_INSTR(0x6b, 0x02), + ILI9881C_COMMAND_INSTR(0x6c, 0x02), + ILI9881C_COMMAND_INSTR(0x6d, 0x02), + ILI9881C_COMMAND_INSTR(0x6e, 0x02), + ILI9881C_COMMAND_INSTR(0x6f, 0x02), + ILI9881C_COMMAND_INSTR(0x70, 0x02), + ILI9881C_COMMAND_INSTR(0x71, 0x02), + ILI9881C_COMMAND_INSTR(0x72, 0x06), + ILI9881C_COMMAND_INSTR(0x73, 0x02), + ILI9881C_COMMAND_INSTR(0x74, 0x02), + ILI9881C_COMMAND_INSTR(0x75, 0x14), + ILI9881C_COMMAND_INSTR(0x76, 0x15), + ILI9881C_COMMAND_INSTR(0x77, 0x0f), + ILI9881C_COMMAND_INSTR(0x78, 0x0e), + ILI9881C_COMMAND_INSTR(0x79, 0x0d), + ILI9881C_COMMAND_INSTR(0x7a, 0x0c), + ILI9881C_COMMAND_INSTR(0x7b, 0x11), + ILI9881C_COMMAND_INSTR(0x7c, 0x10), + ILI9881C_COMMAND_INSTR(0x7d, 0x06), + ILI9881C_COMMAND_INSTR(0x7e, 0x02), + ILI9881C_COMMAND_INSTR(0x7f, 0x0a), + ILI9881C_COMMAND_INSTR(0x80, 0x02), + ILI9881C_COMMAND_INSTR(0x81, 0x02), + ILI9881C_COMMAND_INSTR(0x82, 0x02), + ILI9881C_COMMAND_INSTR(0x83, 0x02), + ILI9881C_COMMAND_INSTR(0x84, 0x02), + ILI9881C_COMMAND_INSTR(0x85, 0x02), + ILI9881C_COMMAND_INSTR(0x86, 0x02), + ILI9881C_COMMAND_INSTR(0x87, 0x02), + ILI9881C_COMMAND_INSTR(0x88, 0x08), + ILI9881C_COMMAND_INSTR(0x89, 0x02), + ILI9881C_COMMAND_INSTR(0x8a, 0x02), + ILI9881C_SWITCH_PAGE_INSTR(4), + ILI9881C_COMMAND_INSTR(0x00, 0x80), + ILI9881C_COMMAND_INSTR(0x70, 0x00), + ILI9881C_COMMAND_INSTR(0x71, 0x00), + ILI9881C_COMMAND_INSTR(0x66, 0xfe), + ILI9881C_COMMAND_INSTR(0x82, 0x15), + ILI9881C_COMMAND_INSTR(0x84, 0x15), + ILI9881C_COMMAND_INSTR(0x85, 0x15), + ILI9881C_COMMAND_INSTR(0x3a, 0x24), + ILI9881C_COMMAND_INSTR(0x32, 0xac), + ILI9881C_COMMAND_INSTR(0x8c, 0x80), + ILI9881C_COMMAND_INSTR(0x3c, 0xf5), + ILI9881C_COMMAND_INSTR(0x88, 0x33), + ILI9881C_SWITCH_PAGE_INSTR(1), + ILI9881C_COMMAND_INSTR(0x22, 0x0a), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x53, 0x78), + ILI9881C_COMMAND_INSTR(0x55, 0x7b), + ILI9881C_COMMAND_INSTR(0x60, 0x20), + ILI9881C_COMMAND_INSTR(0x61, 0x00), + ILI9881C_COMMAND_INSTR(0x62, 0x0d), + ILI9881C_COMMAND_INSTR(0x63, 0x00), + ILI9881C_COMMAND_INSTR(0xa0, 0x00), + ILI9881C_COMMAND_INSTR(0xa1, 0x10), + ILI9881C_COMMAND_INSTR(0xa2, 0x1c), + ILI9881C_COMMAND_INSTR(0xa3, 0x13), + ILI9881C_COMMAND_INSTR(0xa4, 0x15), + ILI9881C_COMMAND_INSTR(0xa5, 0x26), + ILI9881C_COMMAND_INSTR(0xa6, 0x1a), + ILI9881C_COMMAND_INSTR(0xa7, 0x1d), + ILI9881C_COMMAND_INSTR(0xa8, 0x67), + ILI9881C_COMMAND_INSTR(0xa9, 0x1c), + ILI9881C_COMMAND_INSTR(0xaa, 0x29), + ILI9881C_COMMAND_INSTR(0xab, 0x5b), + ILI9881C_COMMAND_INSTR(0xac, 0x26), + ILI9881C_COMMAND_INSTR(0xad, 0x28), + ILI9881C_COMMAND_INSTR(0xae, 0x5c), + ILI9881C_COMMAND_INSTR(0xaf, 0x30), + ILI9881C_COMMAND_INSTR(0xb0, 0x31), + ILI9881C_COMMAND_INSTR(0xb1, 0x32), + ILI9881C_COMMAND_INSTR(0xb2, 0x00), + ILI9881C_COMMAND_INSTR(0xb1, 0x2e), + ILI9881C_COMMAND_INSTR(0xb2, 0x32), + ILI9881C_COMMAND_INSTR(0xb3, 0x00), + ILI9881C_COMMAND_INSTR(0xb6, 0x02), + ILI9881C_COMMAND_INSTR(0xb7, 0x03), + ILI9881C_COMMAND_INSTR(0xc0, 0x00), + ILI9881C_COMMAND_INSTR(0xc1, 0x10), + ILI9881C_COMMAND_INSTR(0xc2, 0x1c), + ILI9881C_COMMAND_INSTR(0xc3, 0x13), + ILI9881C_COMMAND_INSTR(0xc4, 0x15), + ILI9881C_COMMAND_INSTR(0xc5, 0x26), + ILI9881C_COMMAND_INSTR(0xc6, 0x1a), + ILI9881C_COMMAND_INSTR(0xc7, 0x1d), + ILI9881C_COMMAND_INSTR(0xc8, 0x67), + ILI9881C_COMMAND_INSTR(0xc9, 0x1c), + ILI9881C_COMMAND_INSTR(0xca, 0x29), + ILI9881C_COMMAND_INSTR(0xcb, 0x5b), + ILI9881C_COMMAND_INSTR(0xcc, 0x26), + ILI9881C_COMMAND_INSTR(0xcd, 0x28), + ILI9881C_COMMAND_INSTR(0xce, 0x5c), + ILI9881C_COMMAND_INSTR(0xcf, 0x30), + ILI9881C_COMMAND_INSTR(0xd0, 0x31), + ILI9881C_COMMAND_INSTR(0xd1, 0x2e), + ILI9881C_COMMAND_INSTR(0xd2, 0x32), + ILI9881C_COMMAND_INSTR(0xd3, 0x00), + ILI9881C_SWITCH_PAGE_INSTR(0), +}; + static const struct ili9881c_instr w552946ab_init[] = { ILI9881C_SWITCH_PAGE_INSTR(3), ILI9881C_COMMAND_INSTR(0x01, 0x00), @@ -1772,6 +1970,23 @@ static const struct drm_display_mode tl050hdv35_default_mode = { .height_mm = 110, }; +static const struct drm_display_mode w552946aaa_default_mode = { + .clock = 65000, + + .hdisplay = 720, + .hsync_start = 720 + 52, + .hsync_end = 720 + 52 + 8, + .htotal = 720 + 52 + 8 + 48, + + .vdisplay = 1280, + .vsync_start = 1280 + 16, + .vsync_end = 1280 + 16 + 6, + .vtotal = 1280 + 16 + 6 + 15, + + .width_mm = 68, + .height_mm = 121, +}; + static const struct drm_display_mode w552946aba_default_mode = { .clock = 64000, @@ -1983,6 +2198,15 @@ static const struct ili9881c_desc tl050hdv35_desc = { .default_address_mode = 0x03, }; +static const struct ili9881c_desc w552946aaa_desc = { + .init = w552946aaa_init, + .init_length = ARRAY_SIZE(w552946aaa_init), + .mode = &w552946aaa_default_mode, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET, + .lanes = 2, +}; + static const struct ili9881c_desc w552946aba_desc = { .init = w552946ab_init, .init_length = ARRAY_SIZE(w552946ab_init), @@ -2023,6 +2247,7 @@ static const struct of_device_id ili9881c_of_match[] = { { .compatible = "feixin,k101-im2byl02", .data = &k101_im2byl02_desc }, { .compatible = "startek,kd050hdfia020", .data = &kd050hdfia020_desc }, { .compatible = "tdo,tl050hdv35", .data = &tl050hdv35_desc }, + { .compatible = "wanchanglong,w552946aaa", .data = &w552946aaa_desc }, { .compatible = "wanchanglong,w552946aba", .data = &w552946aba_desc }, { .compatible = "ampire,am8001280g", .data = &am8001280g_desc }, { .compatible = "raspberrypi,dsi-7inch", &rpi_7inch_desc }, -- 2.51.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 5/9] drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-18 13:50 ` Neil Armstrong -1 siblings, 0 replies; 71+ messages in thread From: Neil Armstrong @ 2025-11-18 13:50 UTC (permalink / raw) To: Chaoyi Chen, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On 11/6/25 03:06, Chaoyi Chen wrote: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > W552946AAA is a panel by Wanchanglong. This panel utilizes the > Ilitek ILI9881D controller. > > W552946AAA is similar to W552946ABA, but the W552946AAA only > uses 2 lanes. > > Tested on rk3506g-evb1-v10. > > Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > --- > drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 225 ++++++++++++++++++ > 1 file changed, 225 insertions(+) > > diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c > index ad4993b2f92a..9b3e9450808d 100644 > --- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c > +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c > @@ -820,6 +820,204 @@ static const struct ili9881c_instr tl050hdv35_init[] = { > ILI9881C_COMMAND_INSTR(0xd3, 0x39), > }; > > +static const struct ili9881c_instr w552946aaa_init[] = { > + ILI9881C_SWITCH_PAGE_INSTR(3), > + ILI9881C_COMMAND_INSTR(0x01, 0x00), > + ILI9881C_COMMAND_INSTR(0x02, 0x00), > + ILI9881C_COMMAND_INSTR(0x03, 0x53), > + ILI9881C_COMMAND_INSTR(0x04, 0x53), > + ILI9881C_COMMAND_INSTR(0x05, 0x13), > + ILI9881C_COMMAND_INSTR(0x06, 0x04), > + ILI9881C_COMMAND_INSTR(0x07, 0x02), > + ILI9881C_COMMAND_INSTR(0x08, 0x02), > + ILI9881C_COMMAND_INSTR(0x09, 0x00), > + ILI9881C_COMMAND_INSTR(0x0a, 0x00), > + ILI9881C_COMMAND_INSTR(0x0b, 0x00), > + ILI9881C_COMMAND_INSTR(0x0c, 0x00), > + ILI9881C_COMMAND_INSTR(0x0d, 0x00), > + ILI9881C_COMMAND_INSTR(0x0e, 0x00), > + ILI9881C_COMMAND_INSTR(0x0f, 0x00), > + ILI9881C_COMMAND_INSTR(0x10, 0x00), > + ILI9881C_COMMAND_INSTR(0x11, 0x00), > + ILI9881C_COMMAND_INSTR(0x12, 0x00), > + ILI9881C_COMMAND_INSTR(0x13, 0x00), > + ILI9881C_COMMAND_INSTR(0x14, 0x00), > + ILI9881C_COMMAND_INSTR(0x15, 0x08), > + ILI9881C_COMMAND_INSTR(0x16, 0x10), > + ILI9881C_COMMAND_INSTR(0x17, 0x00), > + ILI9881C_COMMAND_INSTR(0x18, 0x08), > + ILI9881C_COMMAND_INSTR(0x19, 0x00), > + ILI9881C_COMMAND_INSTR(0x1a, 0x00), > + ILI9881C_COMMAND_INSTR(0x1b, 0x00), > + ILI9881C_COMMAND_INSTR(0x1c, 0x00), > + ILI9881C_COMMAND_INSTR(0x1d, 0x00), > + ILI9881C_COMMAND_INSTR(0x1e, 0xc0), > + ILI9881C_COMMAND_INSTR(0x1f, 0x80), > + ILI9881C_COMMAND_INSTR(0x20, 0x02), > + ILI9881C_COMMAND_INSTR(0x21, 0x09), > + ILI9881C_COMMAND_INSTR(0x22, 0x00), > + ILI9881C_COMMAND_INSTR(0x23, 0x00), > + ILI9881C_COMMAND_INSTR(0x24, 0x00), > + ILI9881C_COMMAND_INSTR(0x25, 0x00), > + ILI9881C_COMMAND_INSTR(0x26, 0x00), > + ILI9881C_COMMAND_INSTR(0x27, 0x00), > + ILI9881C_COMMAND_INSTR(0x28, 0x55), > + ILI9881C_COMMAND_INSTR(0x29, 0x03), > + ILI9881C_COMMAND_INSTR(0x2a, 0x00), > + ILI9881C_COMMAND_INSTR(0x2b, 0x00), > + ILI9881C_COMMAND_INSTR(0x2c, 0x00), > + ILI9881C_COMMAND_INSTR(0x2d, 0x00), > + ILI9881C_COMMAND_INSTR(0x2e, 0x00), > + ILI9881C_COMMAND_INSTR(0x2f, 0x00), > + ILI9881C_COMMAND_INSTR(0x30, 0x00), > + ILI9881C_COMMAND_INSTR(0x31, 0x00), > + ILI9881C_COMMAND_INSTR(0x32, 0x00), > + ILI9881C_COMMAND_INSTR(0x33, 0x00), > + ILI9881C_COMMAND_INSTR(0x34, 0x04), > + ILI9881C_COMMAND_INSTR(0x35, 0x05), > + ILI9881C_COMMAND_INSTR(0x36, 0x05), > + ILI9881C_COMMAND_INSTR(0x37, 0x00), > + ILI9881C_COMMAND_INSTR(0x38, 0x3c), > + ILI9881C_COMMAND_INSTR(0x39, 0x35), > + ILI9881C_COMMAND_INSTR(0x3a, 0x00), > + ILI9881C_COMMAND_INSTR(0x3b, 0x40), > + ILI9881C_COMMAND_INSTR(0x3c, 0x00), > + ILI9881C_COMMAND_INSTR(0x3d, 0x00), > + ILI9881C_COMMAND_INSTR(0x3e, 0x00), > + ILI9881C_COMMAND_INSTR(0x3f, 0x00), > + ILI9881C_COMMAND_INSTR(0x40, 0x00), > + ILI9881C_COMMAND_INSTR(0x41, 0x88), > + ILI9881C_COMMAND_INSTR(0x42, 0x00), > + ILI9881C_COMMAND_INSTR(0x43, 0x00), > + ILI9881C_COMMAND_INSTR(0x44, 0x1f), > + ILI9881C_COMMAND_INSTR(0x50, 0x01), > + ILI9881C_COMMAND_INSTR(0x51, 0x23), > + ILI9881C_COMMAND_INSTR(0x52, 0x45), > + ILI9881C_COMMAND_INSTR(0x53, 0x67), > + ILI9881C_COMMAND_INSTR(0x54, 0x89), > + ILI9881C_COMMAND_INSTR(0x55, 0xab), > + ILI9881C_COMMAND_INSTR(0x56, 0x01), > + ILI9881C_COMMAND_INSTR(0x57, 0x23), > + ILI9881C_COMMAND_INSTR(0x58, 0x45), > + ILI9881C_COMMAND_INSTR(0x59, 0x67), > + ILI9881C_COMMAND_INSTR(0x5a, 0x89), > + ILI9881C_COMMAND_INSTR(0x5b, 0xab), > + ILI9881C_COMMAND_INSTR(0x5c, 0xcd), > + ILI9881C_COMMAND_INSTR(0x5d, 0xef), > + ILI9881C_COMMAND_INSTR(0x5e, 0x03), > + ILI9881C_COMMAND_INSTR(0x5f, 0x14), > + ILI9881C_COMMAND_INSTR(0x60, 0x15), > + ILI9881C_COMMAND_INSTR(0x61, 0x0c), > + ILI9881C_COMMAND_INSTR(0x62, 0x0d), > + ILI9881C_COMMAND_INSTR(0x63, 0x0e), > + ILI9881C_COMMAND_INSTR(0x64, 0x0f), > + ILI9881C_COMMAND_INSTR(0x65, 0x10), > + ILI9881C_COMMAND_INSTR(0x66, 0x11), > + ILI9881C_COMMAND_INSTR(0x67, 0x08), > + ILI9881C_COMMAND_INSTR(0x68, 0x02), > + ILI9881C_COMMAND_INSTR(0x69, 0x0a), > + ILI9881C_COMMAND_INSTR(0x6a, 0x02), > + ILI9881C_COMMAND_INSTR(0x6b, 0x02), > + ILI9881C_COMMAND_INSTR(0x6c, 0x02), > + ILI9881C_COMMAND_INSTR(0x6d, 0x02), > + ILI9881C_COMMAND_INSTR(0x6e, 0x02), > + ILI9881C_COMMAND_INSTR(0x6f, 0x02), > + ILI9881C_COMMAND_INSTR(0x70, 0x02), > + ILI9881C_COMMAND_INSTR(0x71, 0x02), > + ILI9881C_COMMAND_INSTR(0x72, 0x06), > + ILI9881C_COMMAND_INSTR(0x73, 0x02), > + ILI9881C_COMMAND_INSTR(0x74, 0x02), > + ILI9881C_COMMAND_INSTR(0x75, 0x14), > + ILI9881C_COMMAND_INSTR(0x76, 0x15), > + ILI9881C_COMMAND_INSTR(0x77, 0x0f), > + ILI9881C_COMMAND_INSTR(0x78, 0x0e), > + ILI9881C_COMMAND_INSTR(0x79, 0x0d), > + ILI9881C_COMMAND_INSTR(0x7a, 0x0c), > + ILI9881C_COMMAND_INSTR(0x7b, 0x11), > + ILI9881C_COMMAND_INSTR(0x7c, 0x10), > + ILI9881C_COMMAND_INSTR(0x7d, 0x06), > + ILI9881C_COMMAND_INSTR(0x7e, 0x02), > + ILI9881C_COMMAND_INSTR(0x7f, 0x0a), > + ILI9881C_COMMAND_INSTR(0x80, 0x02), > + ILI9881C_COMMAND_INSTR(0x81, 0x02), > + ILI9881C_COMMAND_INSTR(0x82, 0x02), > + ILI9881C_COMMAND_INSTR(0x83, 0x02), > + ILI9881C_COMMAND_INSTR(0x84, 0x02), > + ILI9881C_COMMAND_INSTR(0x85, 0x02), > + ILI9881C_COMMAND_INSTR(0x86, 0x02), > + ILI9881C_COMMAND_INSTR(0x87, 0x02), > + ILI9881C_COMMAND_INSTR(0x88, 0x08), > + ILI9881C_COMMAND_INSTR(0x89, 0x02), > + ILI9881C_COMMAND_INSTR(0x8a, 0x02), > + ILI9881C_SWITCH_PAGE_INSTR(4), > + ILI9881C_COMMAND_INSTR(0x00, 0x80), > + ILI9881C_COMMAND_INSTR(0x70, 0x00), > + ILI9881C_COMMAND_INSTR(0x71, 0x00), > + ILI9881C_COMMAND_INSTR(0x66, 0xfe), > + ILI9881C_COMMAND_INSTR(0x82, 0x15), > + ILI9881C_COMMAND_INSTR(0x84, 0x15), > + ILI9881C_COMMAND_INSTR(0x85, 0x15), > + ILI9881C_COMMAND_INSTR(0x3a, 0x24), > + ILI9881C_COMMAND_INSTR(0x32, 0xac), > + ILI9881C_COMMAND_INSTR(0x8c, 0x80), > + ILI9881C_COMMAND_INSTR(0x3c, 0xf5), > + ILI9881C_COMMAND_INSTR(0x88, 0x33), > + ILI9881C_SWITCH_PAGE_INSTR(1), > + ILI9881C_COMMAND_INSTR(0x22, 0x0a), > + ILI9881C_COMMAND_INSTR(0x31, 0x00), > + ILI9881C_COMMAND_INSTR(0x53, 0x78), > + ILI9881C_COMMAND_INSTR(0x55, 0x7b), > + ILI9881C_COMMAND_INSTR(0x60, 0x20), > + ILI9881C_COMMAND_INSTR(0x61, 0x00), > + ILI9881C_COMMAND_INSTR(0x62, 0x0d), > + ILI9881C_COMMAND_INSTR(0x63, 0x00), > + ILI9881C_COMMAND_INSTR(0xa0, 0x00), > + ILI9881C_COMMAND_INSTR(0xa1, 0x10), > + ILI9881C_COMMAND_INSTR(0xa2, 0x1c), > + ILI9881C_COMMAND_INSTR(0xa3, 0x13), > + ILI9881C_COMMAND_INSTR(0xa4, 0x15), > + ILI9881C_COMMAND_INSTR(0xa5, 0x26), > + ILI9881C_COMMAND_INSTR(0xa6, 0x1a), > + ILI9881C_COMMAND_INSTR(0xa7, 0x1d), > + ILI9881C_COMMAND_INSTR(0xa8, 0x67), > + ILI9881C_COMMAND_INSTR(0xa9, 0x1c), > + ILI9881C_COMMAND_INSTR(0xaa, 0x29), > + ILI9881C_COMMAND_INSTR(0xab, 0x5b), > + ILI9881C_COMMAND_INSTR(0xac, 0x26), > + ILI9881C_COMMAND_INSTR(0xad, 0x28), > + ILI9881C_COMMAND_INSTR(0xae, 0x5c), > + ILI9881C_COMMAND_INSTR(0xaf, 0x30), > + ILI9881C_COMMAND_INSTR(0xb0, 0x31), > + ILI9881C_COMMAND_INSTR(0xb1, 0x32), > + ILI9881C_COMMAND_INSTR(0xb2, 0x00), > + ILI9881C_COMMAND_INSTR(0xb1, 0x2e), > + ILI9881C_COMMAND_INSTR(0xb2, 0x32), > + ILI9881C_COMMAND_INSTR(0xb3, 0x00), > + ILI9881C_COMMAND_INSTR(0xb6, 0x02), > + ILI9881C_COMMAND_INSTR(0xb7, 0x03), > + ILI9881C_COMMAND_INSTR(0xc0, 0x00), > + ILI9881C_COMMAND_INSTR(0xc1, 0x10), > + ILI9881C_COMMAND_INSTR(0xc2, 0x1c), > + ILI9881C_COMMAND_INSTR(0xc3, 0x13), > + ILI9881C_COMMAND_INSTR(0xc4, 0x15), > + ILI9881C_COMMAND_INSTR(0xc5, 0x26), > + ILI9881C_COMMAND_INSTR(0xc6, 0x1a), > + ILI9881C_COMMAND_INSTR(0xc7, 0x1d), > + ILI9881C_COMMAND_INSTR(0xc8, 0x67), > + ILI9881C_COMMAND_INSTR(0xc9, 0x1c), > + ILI9881C_COMMAND_INSTR(0xca, 0x29), > + ILI9881C_COMMAND_INSTR(0xcb, 0x5b), > + ILI9881C_COMMAND_INSTR(0xcc, 0x26), > + ILI9881C_COMMAND_INSTR(0xcd, 0x28), > + ILI9881C_COMMAND_INSTR(0xce, 0x5c), > + ILI9881C_COMMAND_INSTR(0xcf, 0x30), > + ILI9881C_COMMAND_INSTR(0xd0, 0x31), > + ILI9881C_COMMAND_INSTR(0xd1, 0x2e), > + ILI9881C_COMMAND_INSTR(0xd2, 0x32), > + ILI9881C_COMMAND_INSTR(0xd3, 0x00), > + ILI9881C_SWITCH_PAGE_INSTR(0), > +}; > + > static const struct ili9881c_instr w552946ab_init[] = { > ILI9881C_SWITCH_PAGE_INSTR(3), > ILI9881C_COMMAND_INSTR(0x01, 0x00), > @@ -1772,6 +1970,23 @@ static const struct drm_display_mode tl050hdv35_default_mode = { > .height_mm = 110, > }; > > +static const struct drm_display_mode w552946aaa_default_mode = { > + .clock = 65000, > + > + .hdisplay = 720, > + .hsync_start = 720 + 52, > + .hsync_end = 720 + 52 + 8, > + .htotal = 720 + 52 + 8 + 48, > + > + .vdisplay = 1280, > + .vsync_start = 1280 + 16, > + .vsync_end = 1280 + 16 + 6, > + .vtotal = 1280 + 16 + 6 + 15, > + > + .width_mm = 68, > + .height_mm = 121, > +}; > + > static const struct drm_display_mode w552946aba_default_mode = { > .clock = 64000, > > @@ -1983,6 +2198,15 @@ static const struct ili9881c_desc tl050hdv35_desc = { > .default_address_mode = 0x03, > }; > > +static const struct ili9881c_desc w552946aaa_desc = { > + .init = w552946aaa_init, > + .init_length = ARRAY_SIZE(w552946aaa_init), > + .mode = &w552946aaa_default_mode, > + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | > + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET, > + .lanes = 2, > +}; > + > static const struct ili9881c_desc w552946aba_desc = { > .init = w552946ab_init, > .init_length = ARRAY_SIZE(w552946ab_init), > @@ -2023,6 +2247,7 @@ static const struct of_device_id ili9881c_of_match[] = { > { .compatible = "feixin,k101-im2byl02", .data = &k101_im2byl02_desc }, > { .compatible = "startek,kd050hdfia020", .data = &kd050hdfia020_desc }, > { .compatible = "tdo,tl050hdv35", .data = &tl050hdv35_desc }, > + { .compatible = "wanchanglong,w552946aaa", .data = &w552946aaa_desc }, > { .compatible = "wanchanglong,w552946aba", .data = &w552946aba_desc }, > { .compatible = "ampire,am8001280g", .data = &am8001280g_desc }, > { .compatible = "raspberrypi,dsi-7inch", &rpi_7inch_desc }, Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 5/9] drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel @ 2025-11-18 13:50 ` Neil Armstrong 0 siblings, 0 replies; 71+ messages in thread From: Neil Armstrong @ 2025-11-18 13:50 UTC (permalink / raw) To: Chaoyi Chen, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On 11/6/25 03:06, Chaoyi Chen wrote: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > W552946AAA is a panel by Wanchanglong. This panel utilizes the > Ilitek ILI9881D controller. > > W552946AAA is similar to W552946ABA, but the W552946AAA only > uses 2 lanes. > > Tested on rk3506g-evb1-v10. > > Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > --- > drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 225 ++++++++++++++++++ > 1 file changed, 225 insertions(+) > > diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c > index ad4993b2f92a..9b3e9450808d 100644 > --- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c > +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c > @@ -820,6 +820,204 @@ static const struct ili9881c_instr tl050hdv35_init[] = { > ILI9881C_COMMAND_INSTR(0xd3, 0x39), > }; > > +static const struct ili9881c_instr w552946aaa_init[] = { > + ILI9881C_SWITCH_PAGE_INSTR(3), > + ILI9881C_COMMAND_INSTR(0x01, 0x00), > + ILI9881C_COMMAND_INSTR(0x02, 0x00), > + ILI9881C_COMMAND_INSTR(0x03, 0x53), > + ILI9881C_COMMAND_INSTR(0x04, 0x53), > + ILI9881C_COMMAND_INSTR(0x05, 0x13), > + ILI9881C_COMMAND_INSTR(0x06, 0x04), > + ILI9881C_COMMAND_INSTR(0x07, 0x02), > + ILI9881C_COMMAND_INSTR(0x08, 0x02), > + ILI9881C_COMMAND_INSTR(0x09, 0x00), > + ILI9881C_COMMAND_INSTR(0x0a, 0x00), > + ILI9881C_COMMAND_INSTR(0x0b, 0x00), > + ILI9881C_COMMAND_INSTR(0x0c, 0x00), > + ILI9881C_COMMAND_INSTR(0x0d, 0x00), > + ILI9881C_COMMAND_INSTR(0x0e, 0x00), > + ILI9881C_COMMAND_INSTR(0x0f, 0x00), > + ILI9881C_COMMAND_INSTR(0x10, 0x00), > + ILI9881C_COMMAND_INSTR(0x11, 0x00), > + ILI9881C_COMMAND_INSTR(0x12, 0x00), > + ILI9881C_COMMAND_INSTR(0x13, 0x00), > + ILI9881C_COMMAND_INSTR(0x14, 0x00), > + ILI9881C_COMMAND_INSTR(0x15, 0x08), > + ILI9881C_COMMAND_INSTR(0x16, 0x10), > + ILI9881C_COMMAND_INSTR(0x17, 0x00), > + ILI9881C_COMMAND_INSTR(0x18, 0x08), > + ILI9881C_COMMAND_INSTR(0x19, 0x00), > + ILI9881C_COMMAND_INSTR(0x1a, 0x00), > + ILI9881C_COMMAND_INSTR(0x1b, 0x00), > + ILI9881C_COMMAND_INSTR(0x1c, 0x00), > + ILI9881C_COMMAND_INSTR(0x1d, 0x00), > + ILI9881C_COMMAND_INSTR(0x1e, 0xc0), > + ILI9881C_COMMAND_INSTR(0x1f, 0x80), > + ILI9881C_COMMAND_INSTR(0x20, 0x02), > + ILI9881C_COMMAND_INSTR(0x21, 0x09), > + ILI9881C_COMMAND_INSTR(0x22, 0x00), > + ILI9881C_COMMAND_INSTR(0x23, 0x00), > + ILI9881C_COMMAND_INSTR(0x24, 0x00), > + ILI9881C_COMMAND_INSTR(0x25, 0x00), > + ILI9881C_COMMAND_INSTR(0x26, 0x00), > + ILI9881C_COMMAND_INSTR(0x27, 0x00), > + ILI9881C_COMMAND_INSTR(0x28, 0x55), > + ILI9881C_COMMAND_INSTR(0x29, 0x03), > + ILI9881C_COMMAND_INSTR(0x2a, 0x00), > + ILI9881C_COMMAND_INSTR(0x2b, 0x00), > + ILI9881C_COMMAND_INSTR(0x2c, 0x00), > + ILI9881C_COMMAND_INSTR(0x2d, 0x00), > + ILI9881C_COMMAND_INSTR(0x2e, 0x00), > + ILI9881C_COMMAND_INSTR(0x2f, 0x00), > + ILI9881C_COMMAND_INSTR(0x30, 0x00), > + ILI9881C_COMMAND_INSTR(0x31, 0x00), > + ILI9881C_COMMAND_INSTR(0x32, 0x00), > + ILI9881C_COMMAND_INSTR(0x33, 0x00), > + ILI9881C_COMMAND_INSTR(0x34, 0x04), > + ILI9881C_COMMAND_INSTR(0x35, 0x05), > + ILI9881C_COMMAND_INSTR(0x36, 0x05), > + ILI9881C_COMMAND_INSTR(0x37, 0x00), > + ILI9881C_COMMAND_INSTR(0x38, 0x3c), > + ILI9881C_COMMAND_INSTR(0x39, 0x35), > + ILI9881C_COMMAND_INSTR(0x3a, 0x00), > + ILI9881C_COMMAND_INSTR(0x3b, 0x40), > + ILI9881C_COMMAND_INSTR(0x3c, 0x00), > + ILI9881C_COMMAND_INSTR(0x3d, 0x00), > + ILI9881C_COMMAND_INSTR(0x3e, 0x00), > + ILI9881C_COMMAND_INSTR(0x3f, 0x00), > + ILI9881C_COMMAND_INSTR(0x40, 0x00), > + ILI9881C_COMMAND_INSTR(0x41, 0x88), > + ILI9881C_COMMAND_INSTR(0x42, 0x00), > + ILI9881C_COMMAND_INSTR(0x43, 0x00), > + ILI9881C_COMMAND_INSTR(0x44, 0x1f), > + ILI9881C_COMMAND_INSTR(0x50, 0x01), > + ILI9881C_COMMAND_INSTR(0x51, 0x23), > + ILI9881C_COMMAND_INSTR(0x52, 0x45), > + ILI9881C_COMMAND_INSTR(0x53, 0x67), > + ILI9881C_COMMAND_INSTR(0x54, 0x89), > + ILI9881C_COMMAND_INSTR(0x55, 0xab), > + ILI9881C_COMMAND_INSTR(0x56, 0x01), > + ILI9881C_COMMAND_INSTR(0x57, 0x23), > + ILI9881C_COMMAND_INSTR(0x58, 0x45), > + ILI9881C_COMMAND_INSTR(0x59, 0x67), > + ILI9881C_COMMAND_INSTR(0x5a, 0x89), > + ILI9881C_COMMAND_INSTR(0x5b, 0xab), > + ILI9881C_COMMAND_INSTR(0x5c, 0xcd), > + ILI9881C_COMMAND_INSTR(0x5d, 0xef), > + ILI9881C_COMMAND_INSTR(0x5e, 0x03), > + ILI9881C_COMMAND_INSTR(0x5f, 0x14), > + ILI9881C_COMMAND_INSTR(0x60, 0x15), > + ILI9881C_COMMAND_INSTR(0x61, 0x0c), > + ILI9881C_COMMAND_INSTR(0x62, 0x0d), > + ILI9881C_COMMAND_INSTR(0x63, 0x0e), > + ILI9881C_COMMAND_INSTR(0x64, 0x0f), > + ILI9881C_COMMAND_INSTR(0x65, 0x10), > + ILI9881C_COMMAND_INSTR(0x66, 0x11), > + ILI9881C_COMMAND_INSTR(0x67, 0x08), > + ILI9881C_COMMAND_INSTR(0x68, 0x02), > + ILI9881C_COMMAND_INSTR(0x69, 0x0a), > + ILI9881C_COMMAND_INSTR(0x6a, 0x02), > + ILI9881C_COMMAND_INSTR(0x6b, 0x02), > + ILI9881C_COMMAND_INSTR(0x6c, 0x02), > + ILI9881C_COMMAND_INSTR(0x6d, 0x02), > + ILI9881C_COMMAND_INSTR(0x6e, 0x02), > + ILI9881C_COMMAND_INSTR(0x6f, 0x02), > + ILI9881C_COMMAND_INSTR(0x70, 0x02), > + ILI9881C_COMMAND_INSTR(0x71, 0x02), > + ILI9881C_COMMAND_INSTR(0x72, 0x06), > + ILI9881C_COMMAND_INSTR(0x73, 0x02), > + ILI9881C_COMMAND_INSTR(0x74, 0x02), > + ILI9881C_COMMAND_INSTR(0x75, 0x14), > + ILI9881C_COMMAND_INSTR(0x76, 0x15), > + ILI9881C_COMMAND_INSTR(0x77, 0x0f), > + ILI9881C_COMMAND_INSTR(0x78, 0x0e), > + ILI9881C_COMMAND_INSTR(0x79, 0x0d), > + ILI9881C_COMMAND_INSTR(0x7a, 0x0c), > + ILI9881C_COMMAND_INSTR(0x7b, 0x11), > + ILI9881C_COMMAND_INSTR(0x7c, 0x10), > + ILI9881C_COMMAND_INSTR(0x7d, 0x06), > + ILI9881C_COMMAND_INSTR(0x7e, 0x02), > + ILI9881C_COMMAND_INSTR(0x7f, 0x0a), > + ILI9881C_COMMAND_INSTR(0x80, 0x02), > + ILI9881C_COMMAND_INSTR(0x81, 0x02), > + ILI9881C_COMMAND_INSTR(0x82, 0x02), > + ILI9881C_COMMAND_INSTR(0x83, 0x02), > + ILI9881C_COMMAND_INSTR(0x84, 0x02), > + ILI9881C_COMMAND_INSTR(0x85, 0x02), > + ILI9881C_COMMAND_INSTR(0x86, 0x02), > + ILI9881C_COMMAND_INSTR(0x87, 0x02), > + ILI9881C_COMMAND_INSTR(0x88, 0x08), > + ILI9881C_COMMAND_INSTR(0x89, 0x02), > + ILI9881C_COMMAND_INSTR(0x8a, 0x02), > + ILI9881C_SWITCH_PAGE_INSTR(4), > + ILI9881C_COMMAND_INSTR(0x00, 0x80), > + ILI9881C_COMMAND_INSTR(0x70, 0x00), > + ILI9881C_COMMAND_INSTR(0x71, 0x00), > + ILI9881C_COMMAND_INSTR(0x66, 0xfe), > + ILI9881C_COMMAND_INSTR(0x82, 0x15), > + ILI9881C_COMMAND_INSTR(0x84, 0x15), > + ILI9881C_COMMAND_INSTR(0x85, 0x15), > + ILI9881C_COMMAND_INSTR(0x3a, 0x24), > + ILI9881C_COMMAND_INSTR(0x32, 0xac), > + ILI9881C_COMMAND_INSTR(0x8c, 0x80), > + ILI9881C_COMMAND_INSTR(0x3c, 0xf5), > + ILI9881C_COMMAND_INSTR(0x88, 0x33), > + ILI9881C_SWITCH_PAGE_INSTR(1), > + ILI9881C_COMMAND_INSTR(0x22, 0x0a), > + ILI9881C_COMMAND_INSTR(0x31, 0x00), > + ILI9881C_COMMAND_INSTR(0x53, 0x78), > + ILI9881C_COMMAND_INSTR(0x55, 0x7b), > + ILI9881C_COMMAND_INSTR(0x60, 0x20), > + ILI9881C_COMMAND_INSTR(0x61, 0x00), > + ILI9881C_COMMAND_INSTR(0x62, 0x0d), > + ILI9881C_COMMAND_INSTR(0x63, 0x00), > + ILI9881C_COMMAND_INSTR(0xa0, 0x00), > + ILI9881C_COMMAND_INSTR(0xa1, 0x10), > + ILI9881C_COMMAND_INSTR(0xa2, 0x1c), > + ILI9881C_COMMAND_INSTR(0xa3, 0x13), > + ILI9881C_COMMAND_INSTR(0xa4, 0x15), > + ILI9881C_COMMAND_INSTR(0xa5, 0x26), > + ILI9881C_COMMAND_INSTR(0xa6, 0x1a), > + ILI9881C_COMMAND_INSTR(0xa7, 0x1d), > + ILI9881C_COMMAND_INSTR(0xa8, 0x67), > + ILI9881C_COMMAND_INSTR(0xa9, 0x1c), > + ILI9881C_COMMAND_INSTR(0xaa, 0x29), > + ILI9881C_COMMAND_INSTR(0xab, 0x5b), > + ILI9881C_COMMAND_INSTR(0xac, 0x26), > + ILI9881C_COMMAND_INSTR(0xad, 0x28), > + ILI9881C_COMMAND_INSTR(0xae, 0x5c), > + ILI9881C_COMMAND_INSTR(0xaf, 0x30), > + ILI9881C_COMMAND_INSTR(0xb0, 0x31), > + ILI9881C_COMMAND_INSTR(0xb1, 0x32), > + ILI9881C_COMMAND_INSTR(0xb2, 0x00), > + ILI9881C_COMMAND_INSTR(0xb1, 0x2e), > + ILI9881C_COMMAND_INSTR(0xb2, 0x32), > + ILI9881C_COMMAND_INSTR(0xb3, 0x00), > + ILI9881C_COMMAND_INSTR(0xb6, 0x02), > + ILI9881C_COMMAND_INSTR(0xb7, 0x03), > + ILI9881C_COMMAND_INSTR(0xc0, 0x00), > + ILI9881C_COMMAND_INSTR(0xc1, 0x10), > + ILI9881C_COMMAND_INSTR(0xc2, 0x1c), > + ILI9881C_COMMAND_INSTR(0xc3, 0x13), > + ILI9881C_COMMAND_INSTR(0xc4, 0x15), > + ILI9881C_COMMAND_INSTR(0xc5, 0x26), > + ILI9881C_COMMAND_INSTR(0xc6, 0x1a), > + ILI9881C_COMMAND_INSTR(0xc7, 0x1d), > + ILI9881C_COMMAND_INSTR(0xc8, 0x67), > + ILI9881C_COMMAND_INSTR(0xc9, 0x1c), > + ILI9881C_COMMAND_INSTR(0xca, 0x29), > + ILI9881C_COMMAND_INSTR(0xcb, 0x5b), > + ILI9881C_COMMAND_INSTR(0xcc, 0x26), > + ILI9881C_COMMAND_INSTR(0xcd, 0x28), > + ILI9881C_COMMAND_INSTR(0xce, 0x5c), > + ILI9881C_COMMAND_INSTR(0xcf, 0x30), > + ILI9881C_COMMAND_INSTR(0xd0, 0x31), > + ILI9881C_COMMAND_INSTR(0xd1, 0x2e), > + ILI9881C_COMMAND_INSTR(0xd2, 0x32), > + ILI9881C_COMMAND_INSTR(0xd3, 0x00), > + ILI9881C_SWITCH_PAGE_INSTR(0), > +}; > + > static const struct ili9881c_instr w552946ab_init[] = { > ILI9881C_SWITCH_PAGE_INSTR(3), > ILI9881C_COMMAND_INSTR(0x01, 0x00), > @@ -1772,6 +1970,23 @@ static const struct drm_display_mode tl050hdv35_default_mode = { > .height_mm = 110, > }; > > +static const struct drm_display_mode w552946aaa_default_mode = { > + .clock = 65000, > + > + .hdisplay = 720, > + .hsync_start = 720 + 52, > + .hsync_end = 720 + 52 + 8, > + .htotal = 720 + 52 + 8 + 48, > + > + .vdisplay = 1280, > + .vsync_start = 1280 + 16, > + .vsync_end = 1280 + 16 + 6, > + .vtotal = 1280 + 16 + 6 + 15, > + > + .width_mm = 68, > + .height_mm = 121, > +}; > + > static const struct drm_display_mode w552946aba_default_mode = { > .clock = 64000, > > @@ -1983,6 +2198,15 @@ static const struct ili9881c_desc tl050hdv35_desc = { > .default_address_mode = 0x03, > }; > > +static const struct ili9881c_desc w552946aaa_desc = { > + .init = w552946aaa_init, > + .init_length = ARRAY_SIZE(w552946aaa_init), > + .mode = &w552946aaa_default_mode, > + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | > + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET, > + .lanes = 2, > +}; > + > static const struct ili9881c_desc w552946aba_desc = { > .init = w552946ab_init, > .init_length = ARRAY_SIZE(w552946ab_init), > @@ -2023,6 +2247,7 @@ static const struct of_device_id ili9881c_of_match[] = { > { .compatible = "feixin,k101-im2byl02", .data = &k101_im2byl02_desc }, > { .compatible = "startek,kd050hdfia020", .data = &kd050hdfia020_desc }, > { .compatible = "tdo,tl050hdv35", .data = &tl050hdv35_desc }, > + { .compatible = "wanchanglong,w552946aaa", .data = &w552946aaa_desc }, > { .compatible = "wanchanglong,w552946aba", .data = &w552946aba_desc }, > { .compatible = "ampire,am8001280g", .data = &am8001280g_desc }, > { .compatible = "raspberrypi,dsi-7inch", &rpi_7inch_desc }, Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 5/9] drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel @ 2025-11-18 13:50 ` Neil Armstrong 0 siblings, 0 replies; 71+ messages in thread From: Neil Armstrong @ 2025-11-18 13:50 UTC (permalink / raw) To: Chaoyi Chen, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On 11/6/25 03:06, Chaoyi Chen wrote: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > W552946AAA is a panel by Wanchanglong. This panel utilizes the > Ilitek ILI9881D controller. > > W552946AAA is similar to W552946ABA, but the W552946AAA only > uses 2 lanes. > > Tested on rk3506g-evb1-v10. > > Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > --- > drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 225 ++++++++++++++++++ > 1 file changed, 225 insertions(+) > > diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c > index ad4993b2f92a..9b3e9450808d 100644 > --- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c > +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c > @@ -820,6 +820,204 @@ static const struct ili9881c_instr tl050hdv35_init[] = { > ILI9881C_COMMAND_INSTR(0xd3, 0x39), > }; > > +static const struct ili9881c_instr w552946aaa_init[] = { > + ILI9881C_SWITCH_PAGE_INSTR(3), > + ILI9881C_COMMAND_INSTR(0x01, 0x00), > + ILI9881C_COMMAND_INSTR(0x02, 0x00), > + ILI9881C_COMMAND_INSTR(0x03, 0x53), > + ILI9881C_COMMAND_INSTR(0x04, 0x53), > + ILI9881C_COMMAND_INSTR(0x05, 0x13), > + ILI9881C_COMMAND_INSTR(0x06, 0x04), > + ILI9881C_COMMAND_INSTR(0x07, 0x02), > + ILI9881C_COMMAND_INSTR(0x08, 0x02), > + ILI9881C_COMMAND_INSTR(0x09, 0x00), > + ILI9881C_COMMAND_INSTR(0x0a, 0x00), > + ILI9881C_COMMAND_INSTR(0x0b, 0x00), > + ILI9881C_COMMAND_INSTR(0x0c, 0x00), > + ILI9881C_COMMAND_INSTR(0x0d, 0x00), > + ILI9881C_COMMAND_INSTR(0x0e, 0x00), > + ILI9881C_COMMAND_INSTR(0x0f, 0x00), > + ILI9881C_COMMAND_INSTR(0x10, 0x00), > + ILI9881C_COMMAND_INSTR(0x11, 0x00), > + ILI9881C_COMMAND_INSTR(0x12, 0x00), > + ILI9881C_COMMAND_INSTR(0x13, 0x00), > + ILI9881C_COMMAND_INSTR(0x14, 0x00), > + ILI9881C_COMMAND_INSTR(0x15, 0x08), > + ILI9881C_COMMAND_INSTR(0x16, 0x10), > + ILI9881C_COMMAND_INSTR(0x17, 0x00), > + ILI9881C_COMMAND_INSTR(0x18, 0x08), > + ILI9881C_COMMAND_INSTR(0x19, 0x00), > + ILI9881C_COMMAND_INSTR(0x1a, 0x00), > + ILI9881C_COMMAND_INSTR(0x1b, 0x00), > + ILI9881C_COMMAND_INSTR(0x1c, 0x00), > + ILI9881C_COMMAND_INSTR(0x1d, 0x00), > + ILI9881C_COMMAND_INSTR(0x1e, 0xc0), > + ILI9881C_COMMAND_INSTR(0x1f, 0x80), > + ILI9881C_COMMAND_INSTR(0x20, 0x02), > + ILI9881C_COMMAND_INSTR(0x21, 0x09), > + ILI9881C_COMMAND_INSTR(0x22, 0x00), > + ILI9881C_COMMAND_INSTR(0x23, 0x00), > + ILI9881C_COMMAND_INSTR(0x24, 0x00), > + ILI9881C_COMMAND_INSTR(0x25, 0x00), > + ILI9881C_COMMAND_INSTR(0x26, 0x00), > + ILI9881C_COMMAND_INSTR(0x27, 0x00), > + ILI9881C_COMMAND_INSTR(0x28, 0x55), > + ILI9881C_COMMAND_INSTR(0x29, 0x03), > + ILI9881C_COMMAND_INSTR(0x2a, 0x00), > + ILI9881C_COMMAND_INSTR(0x2b, 0x00), > + ILI9881C_COMMAND_INSTR(0x2c, 0x00), > + ILI9881C_COMMAND_INSTR(0x2d, 0x00), > + ILI9881C_COMMAND_INSTR(0x2e, 0x00), > + ILI9881C_COMMAND_INSTR(0x2f, 0x00), > + ILI9881C_COMMAND_INSTR(0x30, 0x00), > + ILI9881C_COMMAND_INSTR(0x31, 0x00), > + ILI9881C_COMMAND_INSTR(0x32, 0x00), > + ILI9881C_COMMAND_INSTR(0x33, 0x00), > + ILI9881C_COMMAND_INSTR(0x34, 0x04), > + ILI9881C_COMMAND_INSTR(0x35, 0x05), > + ILI9881C_COMMAND_INSTR(0x36, 0x05), > + ILI9881C_COMMAND_INSTR(0x37, 0x00), > + ILI9881C_COMMAND_INSTR(0x38, 0x3c), > + ILI9881C_COMMAND_INSTR(0x39, 0x35), > + ILI9881C_COMMAND_INSTR(0x3a, 0x00), > + ILI9881C_COMMAND_INSTR(0x3b, 0x40), > + ILI9881C_COMMAND_INSTR(0x3c, 0x00), > + ILI9881C_COMMAND_INSTR(0x3d, 0x00), > + ILI9881C_COMMAND_INSTR(0x3e, 0x00), > + ILI9881C_COMMAND_INSTR(0x3f, 0x00), > + ILI9881C_COMMAND_INSTR(0x40, 0x00), > + ILI9881C_COMMAND_INSTR(0x41, 0x88), > + ILI9881C_COMMAND_INSTR(0x42, 0x00), > + ILI9881C_COMMAND_INSTR(0x43, 0x00), > + ILI9881C_COMMAND_INSTR(0x44, 0x1f), > + ILI9881C_COMMAND_INSTR(0x50, 0x01), > + ILI9881C_COMMAND_INSTR(0x51, 0x23), > + ILI9881C_COMMAND_INSTR(0x52, 0x45), > + ILI9881C_COMMAND_INSTR(0x53, 0x67), > + ILI9881C_COMMAND_INSTR(0x54, 0x89), > + ILI9881C_COMMAND_INSTR(0x55, 0xab), > + ILI9881C_COMMAND_INSTR(0x56, 0x01), > + ILI9881C_COMMAND_INSTR(0x57, 0x23), > + ILI9881C_COMMAND_INSTR(0x58, 0x45), > + ILI9881C_COMMAND_INSTR(0x59, 0x67), > + ILI9881C_COMMAND_INSTR(0x5a, 0x89), > + ILI9881C_COMMAND_INSTR(0x5b, 0xab), > + ILI9881C_COMMAND_INSTR(0x5c, 0xcd), > + ILI9881C_COMMAND_INSTR(0x5d, 0xef), > + ILI9881C_COMMAND_INSTR(0x5e, 0x03), > + ILI9881C_COMMAND_INSTR(0x5f, 0x14), > + ILI9881C_COMMAND_INSTR(0x60, 0x15), > + ILI9881C_COMMAND_INSTR(0x61, 0x0c), > + ILI9881C_COMMAND_INSTR(0x62, 0x0d), > + ILI9881C_COMMAND_INSTR(0x63, 0x0e), > + ILI9881C_COMMAND_INSTR(0x64, 0x0f), > + ILI9881C_COMMAND_INSTR(0x65, 0x10), > + ILI9881C_COMMAND_INSTR(0x66, 0x11), > + ILI9881C_COMMAND_INSTR(0x67, 0x08), > + ILI9881C_COMMAND_INSTR(0x68, 0x02), > + ILI9881C_COMMAND_INSTR(0x69, 0x0a), > + ILI9881C_COMMAND_INSTR(0x6a, 0x02), > + ILI9881C_COMMAND_INSTR(0x6b, 0x02), > + ILI9881C_COMMAND_INSTR(0x6c, 0x02), > + ILI9881C_COMMAND_INSTR(0x6d, 0x02), > + ILI9881C_COMMAND_INSTR(0x6e, 0x02), > + ILI9881C_COMMAND_INSTR(0x6f, 0x02), > + ILI9881C_COMMAND_INSTR(0x70, 0x02), > + ILI9881C_COMMAND_INSTR(0x71, 0x02), > + ILI9881C_COMMAND_INSTR(0x72, 0x06), > + ILI9881C_COMMAND_INSTR(0x73, 0x02), > + ILI9881C_COMMAND_INSTR(0x74, 0x02), > + ILI9881C_COMMAND_INSTR(0x75, 0x14), > + ILI9881C_COMMAND_INSTR(0x76, 0x15), > + ILI9881C_COMMAND_INSTR(0x77, 0x0f), > + ILI9881C_COMMAND_INSTR(0x78, 0x0e), > + ILI9881C_COMMAND_INSTR(0x79, 0x0d), > + ILI9881C_COMMAND_INSTR(0x7a, 0x0c), > + ILI9881C_COMMAND_INSTR(0x7b, 0x11), > + ILI9881C_COMMAND_INSTR(0x7c, 0x10), > + ILI9881C_COMMAND_INSTR(0x7d, 0x06), > + ILI9881C_COMMAND_INSTR(0x7e, 0x02), > + ILI9881C_COMMAND_INSTR(0x7f, 0x0a), > + ILI9881C_COMMAND_INSTR(0x80, 0x02), > + ILI9881C_COMMAND_INSTR(0x81, 0x02), > + ILI9881C_COMMAND_INSTR(0x82, 0x02), > + ILI9881C_COMMAND_INSTR(0x83, 0x02), > + ILI9881C_COMMAND_INSTR(0x84, 0x02), > + ILI9881C_COMMAND_INSTR(0x85, 0x02), > + ILI9881C_COMMAND_INSTR(0x86, 0x02), > + ILI9881C_COMMAND_INSTR(0x87, 0x02), > + ILI9881C_COMMAND_INSTR(0x88, 0x08), > + ILI9881C_COMMAND_INSTR(0x89, 0x02), > + ILI9881C_COMMAND_INSTR(0x8a, 0x02), > + ILI9881C_SWITCH_PAGE_INSTR(4), > + ILI9881C_COMMAND_INSTR(0x00, 0x80), > + ILI9881C_COMMAND_INSTR(0x70, 0x00), > + ILI9881C_COMMAND_INSTR(0x71, 0x00), > + ILI9881C_COMMAND_INSTR(0x66, 0xfe), > + ILI9881C_COMMAND_INSTR(0x82, 0x15), > + ILI9881C_COMMAND_INSTR(0x84, 0x15), > + ILI9881C_COMMAND_INSTR(0x85, 0x15), > + ILI9881C_COMMAND_INSTR(0x3a, 0x24), > + ILI9881C_COMMAND_INSTR(0x32, 0xac), > + ILI9881C_COMMAND_INSTR(0x8c, 0x80), > + ILI9881C_COMMAND_INSTR(0x3c, 0xf5), > + ILI9881C_COMMAND_INSTR(0x88, 0x33), > + ILI9881C_SWITCH_PAGE_INSTR(1), > + ILI9881C_COMMAND_INSTR(0x22, 0x0a), > + ILI9881C_COMMAND_INSTR(0x31, 0x00), > + ILI9881C_COMMAND_INSTR(0x53, 0x78), > + ILI9881C_COMMAND_INSTR(0x55, 0x7b), > + ILI9881C_COMMAND_INSTR(0x60, 0x20), > + ILI9881C_COMMAND_INSTR(0x61, 0x00), > + ILI9881C_COMMAND_INSTR(0x62, 0x0d), > + ILI9881C_COMMAND_INSTR(0x63, 0x00), > + ILI9881C_COMMAND_INSTR(0xa0, 0x00), > + ILI9881C_COMMAND_INSTR(0xa1, 0x10), > + ILI9881C_COMMAND_INSTR(0xa2, 0x1c), > + ILI9881C_COMMAND_INSTR(0xa3, 0x13), > + ILI9881C_COMMAND_INSTR(0xa4, 0x15), > + ILI9881C_COMMAND_INSTR(0xa5, 0x26), > + ILI9881C_COMMAND_INSTR(0xa6, 0x1a), > + ILI9881C_COMMAND_INSTR(0xa7, 0x1d), > + ILI9881C_COMMAND_INSTR(0xa8, 0x67), > + ILI9881C_COMMAND_INSTR(0xa9, 0x1c), > + ILI9881C_COMMAND_INSTR(0xaa, 0x29), > + ILI9881C_COMMAND_INSTR(0xab, 0x5b), > + ILI9881C_COMMAND_INSTR(0xac, 0x26), > + ILI9881C_COMMAND_INSTR(0xad, 0x28), > + ILI9881C_COMMAND_INSTR(0xae, 0x5c), > + ILI9881C_COMMAND_INSTR(0xaf, 0x30), > + ILI9881C_COMMAND_INSTR(0xb0, 0x31), > + ILI9881C_COMMAND_INSTR(0xb1, 0x32), > + ILI9881C_COMMAND_INSTR(0xb2, 0x00), > + ILI9881C_COMMAND_INSTR(0xb1, 0x2e), > + ILI9881C_COMMAND_INSTR(0xb2, 0x32), > + ILI9881C_COMMAND_INSTR(0xb3, 0x00), > + ILI9881C_COMMAND_INSTR(0xb6, 0x02), > + ILI9881C_COMMAND_INSTR(0xb7, 0x03), > + ILI9881C_COMMAND_INSTR(0xc0, 0x00), > + ILI9881C_COMMAND_INSTR(0xc1, 0x10), > + ILI9881C_COMMAND_INSTR(0xc2, 0x1c), > + ILI9881C_COMMAND_INSTR(0xc3, 0x13), > + ILI9881C_COMMAND_INSTR(0xc4, 0x15), > + ILI9881C_COMMAND_INSTR(0xc5, 0x26), > + ILI9881C_COMMAND_INSTR(0xc6, 0x1a), > + ILI9881C_COMMAND_INSTR(0xc7, 0x1d), > + ILI9881C_COMMAND_INSTR(0xc8, 0x67), > + ILI9881C_COMMAND_INSTR(0xc9, 0x1c), > + ILI9881C_COMMAND_INSTR(0xca, 0x29), > + ILI9881C_COMMAND_INSTR(0xcb, 0x5b), > + ILI9881C_COMMAND_INSTR(0xcc, 0x26), > + ILI9881C_COMMAND_INSTR(0xcd, 0x28), > + ILI9881C_COMMAND_INSTR(0xce, 0x5c), > + ILI9881C_COMMAND_INSTR(0xcf, 0x30), > + ILI9881C_COMMAND_INSTR(0xd0, 0x31), > + ILI9881C_COMMAND_INSTR(0xd1, 0x2e), > + ILI9881C_COMMAND_INSTR(0xd2, 0x32), > + ILI9881C_COMMAND_INSTR(0xd3, 0x00), > + ILI9881C_SWITCH_PAGE_INSTR(0), > +}; > + > static const struct ili9881c_instr w552946ab_init[] = { > ILI9881C_SWITCH_PAGE_INSTR(3), > ILI9881C_COMMAND_INSTR(0x01, 0x00), > @@ -1772,6 +1970,23 @@ static const struct drm_display_mode tl050hdv35_default_mode = { > .height_mm = 110, > }; > > +static const struct drm_display_mode w552946aaa_default_mode = { > + .clock = 65000, > + > + .hdisplay = 720, > + .hsync_start = 720 + 52, > + .hsync_end = 720 + 52 + 8, > + .htotal = 720 + 52 + 8 + 48, > + > + .vdisplay = 1280, > + .vsync_start = 1280 + 16, > + .vsync_end = 1280 + 16 + 6, > + .vtotal = 1280 + 16 + 6 + 15, > + > + .width_mm = 68, > + .height_mm = 121, > +}; > + > static const struct drm_display_mode w552946aba_default_mode = { > .clock = 64000, > > @@ -1983,6 +2198,15 @@ static const struct ili9881c_desc tl050hdv35_desc = { > .default_address_mode = 0x03, > }; > > +static const struct ili9881c_desc w552946aaa_desc = { > + .init = w552946aaa_init, > + .init_length = ARRAY_SIZE(w552946aaa_init), > + .mode = &w552946aaa_default_mode, > + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | > + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET, > + .lanes = 2, > +}; > + > static const struct ili9881c_desc w552946aba_desc = { > .init = w552946ab_init, > .init_length = ARRAY_SIZE(w552946ab_init), > @@ -2023,6 +2247,7 @@ static const struct of_device_id ili9881c_of_match[] = { > { .compatible = "feixin,k101-im2byl02", .data = &k101_im2byl02_desc }, > { .compatible = "startek,kd050hdfia020", .data = &kd050hdfia020_desc }, > { .compatible = "tdo,tl050hdv35", .data = &tl050hdv35_desc }, > + { .compatible = "wanchanglong,w552946aaa", .data = &w552946aaa_desc }, > { .compatible = "wanchanglong,w552946aba", .data = &w552946aba_desc }, > { .compatible = "ampire,am8001280g", .data = &am8001280g_desc }, > { .compatible = "raspberrypi,dsi-7inch", &rpi_7inch_desc }, Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 6/9] phy: rockchip: inno-dsidphy: Add support for rk3506 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 2:06 ` Chaoyi Chen -1 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen, Hongming Zou From: Chaoyi Chen <chaoyi.chen@rock-chips.com> For MIPI mode, the inno-dsidphy found on RK3506 supports up to 2 lanes and a maximum data rate of 1.5GHz. Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 91 ++++++++++++++++++- 1 file changed, 88 insertions(+), 3 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index d5b1a4e2f7d3..30d5e5ddff4a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -99,10 +99,30 @@ #define VOD_MID_RANGE 0x3 #define VOD_BIG_RANGE 0x7 #define VOD_MAX_RANGE 0xf +/* Analog Register Part: reg18 */ +#define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6) +#define LANE0_PRE_EMPHASIS_ENABLE BIT(6) +#define LANE0_PRE_EMPHASIS_DISABLE 0 +#define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5) +#define LANE1_PRE_EMPHASIS_ENABLE BIT(5) +#define LANE1_PRE_EMPHASIS_DISABLE 0 +/* Analog Register Part: reg19 */ +#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) /* Analog Register Part: reg1E */ #define PLL_MODE_SEL_MASK GENMASK(6, 5) #define PLL_MODE_SEL_LVDS_MODE 0 #define PLL_MODE_SEL_MIPI_MODE BIT(5) +/* Analog Register Part: reg20 */ +#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) +/* Analog Register Part: reg21 */ +#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) +#define PRE_EMPHASIS_MIN_RANGE 0x0 +#define PRE_EMPHASIS_MID_RANGE 0x1 +#define PRE_EMPHASIS_MAX_RANGE 0x2 +#define PRE_EMPHASIS_RESERVED_RANGE 0x3 /* Digital Register Part: reg00 */ #define REG_DIG_RSTN_MASK BIT(0) #define REG_DIG_RSTN_NORMAL BIT(0) @@ -193,6 +213,7 @@ enum phy_max_rate { MAX_1GHZ, + MAX_1_5GHZ, MAX_2_5GHZ, }; @@ -200,6 +221,7 @@ struct inno_video_phy_plat_data { const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table; const unsigned int num_timings; enum phy_max_rate max_rate; + unsigned int max_lanes; }; struct inno_dsidphy { @@ -258,6 +280,24 @@ struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = { {1000000000, 0x0, 0x09, 0x20, 0x09, 0x27}, }; +static const +struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = { + { 110, 0x02, 0x7f, 0x16, 0x02, 0x02}, + { 150, 0x02, 0x7f, 0x16, 0x03, 0x02}, + { 200, 0x02, 0x7f, 0x17, 0x04, 0x02}, + { 250, 0x02, 0x7f, 0x17, 0x05, 0x04}, + { 300, 0x02, 0x7f, 0x18, 0x06, 0x04}, + { 400, 0x03, 0x7e, 0x19, 0x07, 0x04}, + { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08}, + { 600, 0x03, 0x70, 0x1d, 0x08, 0x10}, + { 700, 0x05, 0x40, 0x1e, 0x08, 0x30}, + { 800, 0x05, 0x02, 0x1f, 0x09, 0x30}, + {1000, 0x05, 0x08, 0x20, 0x09, 0x30}, + {1200, 0x06, 0x03, 0x32, 0x14, 0x0f}, + {1400, 0x09, 0x03, 0x32, 0x14, 0x0f}, + {1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f}, +}; + static const struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = { { 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02}, @@ -372,6 +412,7 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; unsigned int i; + u32 val; timings = inno->pdata->inno_mipi_dphy_timing_table; @@ -393,6 +434,23 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, CLOCK_LANE_VOD_RANGE_SET_MASK, CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); + } else if (inno->pdata->max_rate == MAX_1_5GHZ) { + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, + LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, + LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19, + PRE_EMPHASIS_RANGE_SET_MASK, + PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a, + LANE0_PRE_EMPHASIS_RANGE_SET_MASK, + LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b, + LANE1_PRE_EMPHASIS_RANGE_SET_MASK, + LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, + CLOCK_LANE_VOD_RANGE_SET_MASK, + CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); } /* Enable PLL and LDO */ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, @@ -518,10 +576,25 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) T_TA_WAIT_CNT(ta_wait)); } - /* Enable all lanes on analog part */ + /* Enable lanes on analog part */ + switch (inno->pdata->max_lanes) { + case 1: + val = LANE_EN_0; + break; + case 2: + val = LANE_EN_0 | LANE_EN_1; + break; + case 3: + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2; + break; + case 4: + default: + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2 | LANE_EN_3; + break; + } + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, - LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | - LANE_EN_1 | LANE_EN_0); + LANE_EN_MASK, LANE_EN_CK | val); } static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) @@ -680,12 +753,21 @@ static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), .max_rate = MAX_1GHZ, + .max_lanes = 4, +}; + +static const struct inno_video_phy_plat_data max_1_5ghz_video_phy_plat_data = { + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz), + .max_rate = MAX_1_5GHZ, + .max_lanes = 2, }; static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), .max_rate = MAX_2_5GHZ, + .max_lanes = 4, }; static int inno_dsidphy_probe(struct platform_device *pdev) @@ -767,6 +849,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = { }, { .compatible = "rockchip,rk3368-dsi-dphy", .data = &max_1ghz_video_phy_plat_data, + }, { + .compatible = "rockchip,rk3506-dsi-dphy", + .data = &max_1_5ghz_video_phy_plat_data, }, { .compatible = "rockchip,rk3568-dsi-dphy", .data = &max_2_5ghz_video_phy_plat_data, -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 6/9] phy: rockchip: inno-dsidphy: Add support for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen, Hongming Zou From: Chaoyi Chen <chaoyi.chen@rock-chips.com> For MIPI mode, the inno-dsidphy found on RK3506 supports up to 2 lanes and a maximum data rate of 1.5GHz. Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 91 ++++++++++++++++++- 1 file changed, 88 insertions(+), 3 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index d5b1a4e2f7d3..30d5e5ddff4a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -99,10 +99,30 @@ #define VOD_MID_RANGE 0x3 #define VOD_BIG_RANGE 0x7 #define VOD_MAX_RANGE 0xf +/* Analog Register Part: reg18 */ +#define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6) +#define LANE0_PRE_EMPHASIS_ENABLE BIT(6) +#define LANE0_PRE_EMPHASIS_DISABLE 0 +#define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5) +#define LANE1_PRE_EMPHASIS_ENABLE BIT(5) +#define LANE1_PRE_EMPHASIS_DISABLE 0 +/* Analog Register Part: reg19 */ +#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) /* Analog Register Part: reg1E */ #define PLL_MODE_SEL_MASK GENMASK(6, 5) #define PLL_MODE_SEL_LVDS_MODE 0 #define PLL_MODE_SEL_MIPI_MODE BIT(5) +/* Analog Register Part: reg20 */ +#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) +/* Analog Register Part: reg21 */ +#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) +#define PRE_EMPHASIS_MIN_RANGE 0x0 +#define PRE_EMPHASIS_MID_RANGE 0x1 +#define PRE_EMPHASIS_MAX_RANGE 0x2 +#define PRE_EMPHASIS_RESERVED_RANGE 0x3 /* Digital Register Part: reg00 */ #define REG_DIG_RSTN_MASK BIT(0) #define REG_DIG_RSTN_NORMAL BIT(0) @@ -193,6 +213,7 @@ enum phy_max_rate { MAX_1GHZ, + MAX_1_5GHZ, MAX_2_5GHZ, }; @@ -200,6 +221,7 @@ struct inno_video_phy_plat_data { const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table; const unsigned int num_timings; enum phy_max_rate max_rate; + unsigned int max_lanes; }; struct inno_dsidphy { @@ -258,6 +280,24 @@ struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = { {1000000000, 0x0, 0x09, 0x20, 0x09, 0x27}, }; +static const +struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = { + { 110, 0x02, 0x7f, 0x16, 0x02, 0x02}, + { 150, 0x02, 0x7f, 0x16, 0x03, 0x02}, + { 200, 0x02, 0x7f, 0x17, 0x04, 0x02}, + { 250, 0x02, 0x7f, 0x17, 0x05, 0x04}, + { 300, 0x02, 0x7f, 0x18, 0x06, 0x04}, + { 400, 0x03, 0x7e, 0x19, 0x07, 0x04}, + { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08}, + { 600, 0x03, 0x70, 0x1d, 0x08, 0x10}, + { 700, 0x05, 0x40, 0x1e, 0x08, 0x30}, + { 800, 0x05, 0x02, 0x1f, 0x09, 0x30}, + {1000, 0x05, 0x08, 0x20, 0x09, 0x30}, + {1200, 0x06, 0x03, 0x32, 0x14, 0x0f}, + {1400, 0x09, 0x03, 0x32, 0x14, 0x0f}, + {1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f}, +}; + static const struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = { { 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02}, @@ -372,6 +412,7 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; unsigned int i; + u32 val; timings = inno->pdata->inno_mipi_dphy_timing_table; @@ -393,6 +434,23 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, CLOCK_LANE_VOD_RANGE_SET_MASK, CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); + } else if (inno->pdata->max_rate == MAX_1_5GHZ) { + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, + LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, + LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19, + PRE_EMPHASIS_RANGE_SET_MASK, + PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a, + LANE0_PRE_EMPHASIS_RANGE_SET_MASK, + LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b, + LANE1_PRE_EMPHASIS_RANGE_SET_MASK, + LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, + CLOCK_LANE_VOD_RANGE_SET_MASK, + CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); } /* Enable PLL and LDO */ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, @@ -518,10 +576,25 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) T_TA_WAIT_CNT(ta_wait)); } - /* Enable all lanes on analog part */ + /* Enable lanes on analog part */ + switch (inno->pdata->max_lanes) { + case 1: + val = LANE_EN_0; + break; + case 2: + val = LANE_EN_0 | LANE_EN_1; + break; + case 3: + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2; + break; + case 4: + default: + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2 | LANE_EN_3; + break; + } + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, - LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | - LANE_EN_1 | LANE_EN_0); + LANE_EN_MASK, LANE_EN_CK | val); } static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) @@ -680,12 +753,21 @@ static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), .max_rate = MAX_1GHZ, + .max_lanes = 4, +}; + +static const struct inno_video_phy_plat_data max_1_5ghz_video_phy_plat_data = { + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz), + .max_rate = MAX_1_5GHZ, + .max_lanes = 2, }; static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), .max_rate = MAX_2_5GHZ, + .max_lanes = 4, }; static int inno_dsidphy_probe(struct platform_device *pdev) @@ -767,6 +849,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = { }, { .compatible = "rockchip,rk3368-dsi-dphy", .data = &max_1ghz_video_phy_plat_data, + }, { + .compatible = "rockchip,rk3506-dsi-dphy", + .data = &max_1_5ghz_video_phy_plat_data, }, { .compatible = "rockchip,rk3568-dsi-dphy", .data = &max_2_5ghz_video_phy_plat_data, -- 2.51.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 6/9] phy: rockchip: inno-dsidphy: Add support for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen, Hongming Zou From: Chaoyi Chen <chaoyi.chen@rock-chips.com> For MIPI mode, the inno-dsidphy found on RK3506 supports up to 2 lanes and a maximum data rate of 1.5GHz. Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 91 ++++++++++++++++++- 1 file changed, 88 insertions(+), 3 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c index d5b1a4e2f7d3..30d5e5ddff4a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c @@ -99,10 +99,30 @@ #define VOD_MID_RANGE 0x3 #define VOD_BIG_RANGE 0x7 #define VOD_MAX_RANGE 0xf +/* Analog Register Part: reg18 */ +#define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6) +#define LANE0_PRE_EMPHASIS_ENABLE BIT(6) +#define LANE0_PRE_EMPHASIS_DISABLE 0 +#define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5) +#define LANE1_PRE_EMPHASIS_ENABLE BIT(5) +#define LANE1_PRE_EMPHASIS_DISABLE 0 +/* Analog Register Part: reg19 */ +#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) /* Analog Register Part: reg1E */ #define PLL_MODE_SEL_MASK GENMASK(6, 5) #define PLL_MODE_SEL_LVDS_MODE 0 #define PLL_MODE_SEL_MIPI_MODE BIT(5) +/* Analog Register Part: reg20 */ +#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) +/* Analog Register Part: reg21 */ +#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) +#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) +#define PRE_EMPHASIS_MIN_RANGE 0x0 +#define PRE_EMPHASIS_MID_RANGE 0x1 +#define PRE_EMPHASIS_MAX_RANGE 0x2 +#define PRE_EMPHASIS_RESERVED_RANGE 0x3 /* Digital Register Part: reg00 */ #define REG_DIG_RSTN_MASK BIT(0) #define REG_DIG_RSTN_NORMAL BIT(0) @@ -193,6 +213,7 @@ enum phy_max_rate { MAX_1GHZ, + MAX_1_5GHZ, MAX_2_5GHZ, }; @@ -200,6 +221,7 @@ struct inno_video_phy_plat_data { const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table; const unsigned int num_timings; enum phy_max_rate max_rate; + unsigned int max_lanes; }; struct inno_dsidphy { @@ -258,6 +280,24 @@ struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = { {1000000000, 0x0, 0x09, 0x20, 0x09, 0x27}, }; +static const +struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = { + { 110, 0x02, 0x7f, 0x16, 0x02, 0x02}, + { 150, 0x02, 0x7f, 0x16, 0x03, 0x02}, + { 200, 0x02, 0x7f, 0x17, 0x04, 0x02}, + { 250, 0x02, 0x7f, 0x17, 0x05, 0x04}, + { 300, 0x02, 0x7f, 0x18, 0x06, 0x04}, + { 400, 0x03, 0x7e, 0x19, 0x07, 0x04}, + { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08}, + { 600, 0x03, 0x70, 0x1d, 0x08, 0x10}, + { 700, 0x05, 0x40, 0x1e, 0x08, 0x30}, + { 800, 0x05, 0x02, 0x1f, 0x09, 0x30}, + {1000, 0x05, 0x08, 0x20, 0x09, 0x30}, + {1200, 0x06, 0x03, 0x32, 0x14, 0x0f}, + {1400, 0x09, 0x03, 0x32, 0x14, 0x0f}, + {1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f}, +}; + static const struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = { { 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02}, @@ -372,6 +412,7 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; unsigned int i; + u32 val; timings = inno->pdata->inno_mipi_dphy_timing_table; @@ -393,6 +434,23 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, CLOCK_LANE_VOD_RANGE_SET_MASK, CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); + } else if (inno->pdata->max_rate == MAX_1_5GHZ) { + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, + LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, + LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19, + PRE_EMPHASIS_RANGE_SET_MASK, + PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a, + LANE0_PRE_EMPHASIS_RANGE_SET_MASK, + LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b, + LANE1_PRE_EMPHASIS_RANGE_SET_MASK, + LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, + CLOCK_LANE_VOD_RANGE_SET_MASK, + CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); } /* Enable PLL and LDO */ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, @@ -518,10 +576,25 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) T_TA_WAIT_CNT(ta_wait)); } - /* Enable all lanes on analog part */ + /* Enable lanes on analog part */ + switch (inno->pdata->max_lanes) { + case 1: + val = LANE_EN_0; + break; + case 2: + val = LANE_EN_0 | LANE_EN_1; + break; + case 3: + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2; + break; + case 4: + default: + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2 | LANE_EN_3; + break; + } + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, - LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | - LANE_EN_1 | LANE_EN_0); + LANE_EN_MASK, LANE_EN_CK | val); } static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) @@ -680,12 +753,21 @@ static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), .max_rate = MAX_1GHZ, + .max_lanes = 4, +}; + +static const struct inno_video_phy_plat_data max_1_5ghz_video_phy_plat_data = { + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz, + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz), + .max_rate = MAX_1_5GHZ, + .max_lanes = 2, }; static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = { .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), .max_rate = MAX_2_5GHZ, + .max_lanes = 4, }; static int inno_dsidphy_probe(struct platform_device *pdev) @@ -767,6 +849,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = { }, { .compatible = "rockchip,rk3368-dsi-dphy", .data = &max_1ghz_video_phy_plat_data, + }, { + .compatible = "rockchip,rk3506-dsi-dphy", + .data = &max_1_5ghz_video_phy_plat_data, }, { .compatible = "rockchip,rk3568-dsi-dphy", .data = &max_2_5ghz_video_phy_plat_data, -- 2.51.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 6/9] phy: rockchip: inno-dsidphy: Add support for rk3506 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-18 13:50 ` Neil Armstrong -1 siblings, 0 replies; 71+ messages in thread From: Neil Armstrong @ 2025-11-18 13:50 UTC (permalink / raw) To: Chaoyi Chen, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen, Hongming Zou On 11/6/25 03:06, Chaoyi Chen wrote: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > For MIPI mode, the inno-dsidphy found on RK3506 supports up to 2 lanes > and a maximum data rate of 1.5GHz. > > Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> > Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > --- > .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 91 ++++++++++++++++++- > 1 file changed, 88 insertions(+), 3 deletions(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > index d5b1a4e2f7d3..30d5e5ddff4a 100644 > --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > @@ -99,10 +99,30 @@ > #define VOD_MID_RANGE 0x3 > #define VOD_BIG_RANGE 0x7 > #define VOD_MAX_RANGE 0xf > +/* Analog Register Part: reg18 */ > +#define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6) > +#define LANE0_PRE_EMPHASIS_ENABLE BIT(6) > +#define LANE0_PRE_EMPHASIS_DISABLE 0 > +#define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5) > +#define LANE1_PRE_EMPHASIS_ENABLE BIT(5) > +#define LANE1_PRE_EMPHASIS_DISABLE 0 > +/* Analog Register Part: reg19 */ > +#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) > +#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) > /* Analog Register Part: reg1E */ > #define PLL_MODE_SEL_MASK GENMASK(6, 5) > #define PLL_MODE_SEL_LVDS_MODE 0 > #define PLL_MODE_SEL_MIPI_MODE BIT(5) > +/* Analog Register Part: reg20 */ > +#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) > +#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) > +/* Analog Register Part: reg21 */ > +#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) > +#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) > +#define PRE_EMPHASIS_MIN_RANGE 0x0 > +#define PRE_EMPHASIS_MID_RANGE 0x1 > +#define PRE_EMPHASIS_MAX_RANGE 0x2 > +#define PRE_EMPHASIS_RESERVED_RANGE 0x3 > /* Digital Register Part: reg00 */ > #define REG_DIG_RSTN_MASK BIT(0) > #define REG_DIG_RSTN_NORMAL BIT(0) > @@ -193,6 +213,7 @@ > > enum phy_max_rate { > MAX_1GHZ, > + MAX_1_5GHZ, > MAX_2_5GHZ, > }; > > @@ -200,6 +221,7 @@ struct inno_video_phy_plat_data { > const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table; > const unsigned int num_timings; > enum phy_max_rate max_rate; > + unsigned int max_lanes; > }; > > struct inno_dsidphy { > @@ -258,6 +280,24 @@ struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = { > {1000000000, 0x0, 0x09, 0x20, 0x09, 0x27}, > }; > > +static const > +struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = { > + { 110, 0x02, 0x7f, 0x16, 0x02, 0x02}, > + { 150, 0x02, 0x7f, 0x16, 0x03, 0x02}, > + { 200, 0x02, 0x7f, 0x17, 0x04, 0x02}, > + { 250, 0x02, 0x7f, 0x17, 0x05, 0x04}, > + { 300, 0x02, 0x7f, 0x18, 0x06, 0x04}, > + { 400, 0x03, 0x7e, 0x19, 0x07, 0x04}, > + { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08}, > + { 600, 0x03, 0x70, 0x1d, 0x08, 0x10}, > + { 700, 0x05, 0x40, 0x1e, 0x08, 0x30}, > + { 800, 0x05, 0x02, 0x1f, 0x09, 0x30}, > + {1000, 0x05, 0x08, 0x20, 0x09, 0x30}, > + {1200, 0x06, 0x03, 0x32, 0x14, 0x0f}, > + {1400, 0x09, 0x03, 0x32, 0x14, 0x0f}, > + {1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f}, > +}; > + > static const > struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = { > { 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02}, > @@ -372,6 +412,7 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) > u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; > u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; > unsigned int i; > + u32 val; > > timings = inno->pdata->inno_mipi_dphy_timing_table; > > @@ -393,6 +434,23 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) > phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, > CLOCK_LANE_VOD_RANGE_SET_MASK, > CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); > + } else if (inno->pdata->max_rate == MAX_1_5GHZ) { > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, > + LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, > + LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19, > + PRE_EMPHASIS_RANGE_SET_MASK, > + PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a, > + LANE0_PRE_EMPHASIS_RANGE_SET_MASK, > + LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b, > + LANE1_PRE_EMPHASIS_RANGE_SET_MASK, > + LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, > + CLOCK_LANE_VOD_RANGE_SET_MASK, > + CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); > } > /* Enable PLL and LDO */ > phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, > @@ -518,10 +576,25 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) > T_TA_WAIT_CNT(ta_wait)); > } > > - /* Enable all lanes on analog part */ > + /* Enable lanes on analog part */ > + switch (inno->pdata->max_lanes) { > + case 1: > + val = LANE_EN_0; > + break; > + case 2: > + val = LANE_EN_0 | LANE_EN_1; > + break; > + case 3: > + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2; > + break; > + case 4: > + default: > + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2 | LANE_EN_3; > + break; > + } > + > phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, > - LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | > - LANE_EN_1 | LANE_EN_0); > + LANE_EN_MASK, LANE_EN_CK | val); > } > > static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) > @@ -680,12 +753,21 @@ static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = { > .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, > .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), > .max_rate = MAX_1GHZ, > + .max_lanes = 4, > +}; > + > +static const struct inno_video_phy_plat_data max_1_5ghz_video_phy_plat_data = { > + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz, > + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz), > + .max_rate = MAX_1_5GHZ, > + .max_lanes = 2, > }; > > static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = { > .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, > .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), > .max_rate = MAX_2_5GHZ, > + .max_lanes = 4, > }; > > static int inno_dsidphy_probe(struct platform_device *pdev) > @@ -767,6 +849,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = { > }, { > .compatible = "rockchip,rk3368-dsi-dphy", > .data = &max_1ghz_video_phy_plat_data, > + }, { > + .compatible = "rockchip,rk3506-dsi-dphy", > + .data = &max_1_5ghz_video_phy_plat_data, > }, { > .compatible = "rockchip,rk3568-dsi-dphy", > .data = &max_2_5ghz_video_phy_plat_data, Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 6/9] phy: rockchip: inno-dsidphy: Add support for rk3506 @ 2025-11-18 13:50 ` Neil Armstrong 0 siblings, 0 replies; 71+ messages in thread From: Neil Armstrong @ 2025-11-18 13:50 UTC (permalink / raw) To: Chaoyi Chen, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen, Hongming Zou On 11/6/25 03:06, Chaoyi Chen wrote: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > For MIPI mode, the inno-dsidphy found on RK3506 supports up to 2 lanes > and a maximum data rate of 1.5GHz. > > Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> > Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > --- > .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 91 ++++++++++++++++++- > 1 file changed, 88 insertions(+), 3 deletions(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > index d5b1a4e2f7d3..30d5e5ddff4a 100644 > --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > @@ -99,10 +99,30 @@ > #define VOD_MID_RANGE 0x3 > #define VOD_BIG_RANGE 0x7 > #define VOD_MAX_RANGE 0xf > +/* Analog Register Part: reg18 */ > +#define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6) > +#define LANE0_PRE_EMPHASIS_ENABLE BIT(6) > +#define LANE0_PRE_EMPHASIS_DISABLE 0 > +#define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5) > +#define LANE1_PRE_EMPHASIS_ENABLE BIT(5) > +#define LANE1_PRE_EMPHASIS_DISABLE 0 > +/* Analog Register Part: reg19 */ > +#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) > +#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) > /* Analog Register Part: reg1E */ > #define PLL_MODE_SEL_MASK GENMASK(6, 5) > #define PLL_MODE_SEL_LVDS_MODE 0 > #define PLL_MODE_SEL_MIPI_MODE BIT(5) > +/* Analog Register Part: reg20 */ > +#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) > +#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) > +/* Analog Register Part: reg21 */ > +#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) > +#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) > +#define PRE_EMPHASIS_MIN_RANGE 0x0 > +#define PRE_EMPHASIS_MID_RANGE 0x1 > +#define PRE_EMPHASIS_MAX_RANGE 0x2 > +#define PRE_EMPHASIS_RESERVED_RANGE 0x3 > /* Digital Register Part: reg00 */ > #define REG_DIG_RSTN_MASK BIT(0) > #define REG_DIG_RSTN_NORMAL BIT(0) > @@ -193,6 +213,7 @@ > > enum phy_max_rate { > MAX_1GHZ, > + MAX_1_5GHZ, > MAX_2_5GHZ, > }; > > @@ -200,6 +221,7 @@ struct inno_video_phy_plat_data { > const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table; > const unsigned int num_timings; > enum phy_max_rate max_rate; > + unsigned int max_lanes; > }; > > struct inno_dsidphy { > @@ -258,6 +280,24 @@ struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = { > {1000000000, 0x0, 0x09, 0x20, 0x09, 0x27}, > }; > > +static const > +struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = { > + { 110, 0x02, 0x7f, 0x16, 0x02, 0x02}, > + { 150, 0x02, 0x7f, 0x16, 0x03, 0x02}, > + { 200, 0x02, 0x7f, 0x17, 0x04, 0x02}, > + { 250, 0x02, 0x7f, 0x17, 0x05, 0x04}, > + { 300, 0x02, 0x7f, 0x18, 0x06, 0x04}, > + { 400, 0x03, 0x7e, 0x19, 0x07, 0x04}, > + { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08}, > + { 600, 0x03, 0x70, 0x1d, 0x08, 0x10}, > + { 700, 0x05, 0x40, 0x1e, 0x08, 0x30}, > + { 800, 0x05, 0x02, 0x1f, 0x09, 0x30}, > + {1000, 0x05, 0x08, 0x20, 0x09, 0x30}, > + {1200, 0x06, 0x03, 0x32, 0x14, 0x0f}, > + {1400, 0x09, 0x03, 0x32, 0x14, 0x0f}, > + {1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f}, > +}; > + > static const > struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = { > { 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02}, > @@ -372,6 +412,7 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) > u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; > u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; > unsigned int i; > + u32 val; > > timings = inno->pdata->inno_mipi_dphy_timing_table; > > @@ -393,6 +434,23 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) > phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, > CLOCK_LANE_VOD_RANGE_SET_MASK, > CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); > + } else if (inno->pdata->max_rate == MAX_1_5GHZ) { > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, > + LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, > + LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19, > + PRE_EMPHASIS_RANGE_SET_MASK, > + PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a, > + LANE0_PRE_EMPHASIS_RANGE_SET_MASK, > + LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b, > + LANE1_PRE_EMPHASIS_RANGE_SET_MASK, > + LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, > + CLOCK_LANE_VOD_RANGE_SET_MASK, > + CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); > } > /* Enable PLL and LDO */ > phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, > @@ -518,10 +576,25 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) > T_TA_WAIT_CNT(ta_wait)); > } > > - /* Enable all lanes on analog part */ > + /* Enable lanes on analog part */ > + switch (inno->pdata->max_lanes) { > + case 1: > + val = LANE_EN_0; > + break; > + case 2: > + val = LANE_EN_0 | LANE_EN_1; > + break; > + case 3: > + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2; > + break; > + case 4: > + default: > + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2 | LANE_EN_3; > + break; > + } > + > phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, > - LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | > - LANE_EN_1 | LANE_EN_0); > + LANE_EN_MASK, LANE_EN_CK | val); > } > > static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) > @@ -680,12 +753,21 @@ static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = { > .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, > .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), > .max_rate = MAX_1GHZ, > + .max_lanes = 4, > +}; > + > +static const struct inno_video_phy_plat_data max_1_5ghz_video_phy_plat_data = { > + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz, > + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz), > + .max_rate = MAX_1_5GHZ, > + .max_lanes = 2, > }; > > static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = { > .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, > .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), > .max_rate = MAX_2_5GHZ, > + .max_lanes = 4, > }; > > static int inno_dsidphy_probe(struct platform_device *pdev) > @@ -767,6 +849,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = { > }, { > .compatible = "rockchip,rk3368-dsi-dphy", > .data = &max_1ghz_video_phy_plat_data, > + }, { > + .compatible = "rockchip,rk3506-dsi-dphy", > + .data = &max_1_5ghz_video_phy_plat_data, > }, { > .compatible = "rockchip,rk3568-dsi-dphy", > .data = &max_2_5ghz_video_phy_plat_data, Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 6/9] phy: rockchip: inno-dsidphy: Add support for rk3506 @ 2025-11-18 13:50 ` Neil Armstrong 0 siblings, 0 replies; 71+ messages in thread From: Neil Armstrong @ 2025-11-18 13:50 UTC (permalink / raw) To: Chaoyi Chen, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen, Hongming Zou On 11/6/25 03:06, Chaoyi Chen wrote: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > For MIPI mode, the inno-dsidphy found on RK3506 supports up to 2 lanes > and a maximum data rate of 1.5GHz. > > Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> > Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > --- > .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 91 ++++++++++++++++++- > 1 file changed, 88 insertions(+), 3 deletions(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > index d5b1a4e2f7d3..30d5e5ddff4a 100644 > --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c > @@ -99,10 +99,30 @@ > #define VOD_MID_RANGE 0x3 > #define VOD_BIG_RANGE 0x7 > #define VOD_MAX_RANGE 0xf > +/* Analog Register Part: reg18 */ > +#define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6) > +#define LANE0_PRE_EMPHASIS_ENABLE BIT(6) > +#define LANE0_PRE_EMPHASIS_DISABLE 0 > +#define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5) > +#define LANE1_PRE_EMPHASIS_ENABLE BIT(5) > +#define LANE1_PRE_EMPHASIS_DISABLE 0 > +/* Analog Register Part: reg19 */ > +#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) > +#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) > /* Analog Register Part: reg1E */ > #define PLL_MODE_SEL_MASK GENMASK(6, 5) > #define PLL_MODE_SEL_LVDS_MODE 0 > #define PLL_MODE_SEL_MIPI_MODE BIT(5) > +/* Analog Register Part: reg20 */ > +#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) > +#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) > +/* Analog Register Part: reg21 */ > +#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6) > +#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6) > +#define PRE_EMPHASIS_MIN_RANGE 0x0 > +#define PRE_EMPHASIS_MID_RANGE 0x1 > +#define PRE_EMPHASIS_MAX_RANGE 0x2 > +#define PRE_EMPHASIS_RESERVED_RANGE 0x3 > /* Digital Register Part: reg00 */ > #define REG_DIG_RSTN_MASK BIT(0) > #define REG_DIG_RSTN_NORMAL BIT(0) > @@ -193,6 +213,7 @@ > > enum phy_max_rate { > MAX_1GHZ, > + MAX_1_5GHZ, > MAX_2_5GHZ, > }; > > @@ -200,6 +221,7 @@ struct inno_video_phy_plat_data { > const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table; > const unsigned int num_timings; > enum phy_max_rate max_rate; > + unsigned int max_lanes; > }; > > struct inno_dsidphy { > @@ -258,6 +280,24 @@ struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = { > {1000000000, 0x0, 0x09, 0x20, 0x09, 0x27}, > }; > > +static const > +struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = { > + { 110, 0x02, 0x7f, 0x16, 0x02, 0x02}, > + { 150, 0x02, 0x7f, 0x16, 0x03, 0x02}, > + { 200, 0x02, 0x7f, 0x17, 0x04, 0x02}, > + { 250, 0x02, 0x7f, 0x17, 0x05, 0x04}, > + { 300, 0x02, 0x7f, 0x18, 0x06, 0x04}, > + { 400, 0x03, 0x7e, 0x19, 0x07, 0x04}, > + { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08}, > + { 600, 0x03, 0x70, 0x1d, 0x08, 0x10}, > + { 700, 0x05, 0x40, 0x1e, 0x08, 0x30}, > + { 800, 0x05, 0x02, 0x1f, 0x09, 0x30}, > + {1000, 0x05, 0x08, 0x20, 0x09, 0x30}, > + {1200, 0x06, 0x03, 0x32, 0x14, 0x0f}, > + {1400, 0x09, 0x03, 0x32, 0x14, 0x0f}, > + {1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f}, > +}; > + > static const > struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = { > { 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02}, > @@ -372,6 +412,7 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) > u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; > u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; > unsigned int i; > + u32 val; > > timings = inno->pdata->inno_mipi_dphy_timing_table; > > @@ -393,6 +434,23 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) > phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, > CLOCK_LANE_VOD_RANGE_SET_MASK, > CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); > + } else if (inno->pdata->max_rate == MAX_1_5GHZ) { > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, > + LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18, > + LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19, > + PRE_EMPHASIS_RANGE_SET_MASK, > + PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a, > + LANE0_PRE_EMPHASIS_RANGE_SET_MASK, > + LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b, > + LANE1_PRE_EMPHASIS_RANGE_SET_MASK, > + LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE)); > + phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, > + CLOCK_LANE_VOD_RANGE_SET_MASK, > + CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE)); > } > /* Enable PLL and LDO */ > phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, > @@ -518,10 +576,25 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) > T_TA_WAIT_CNT(ta_wait)); > } > > - /* Enable all lanes on analog part */ > + /* Enable lanes on analog part */ > + switch (inno->pdata->max_lanes) { > + case 1: > + val = LANE_EN_0; > + break; > + case 2: > + val = LANE_EN_0 | LANE_EN_1; > + break; > + case 3: > + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2; > + break; > + case 4: > + default: > + val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2 | LANE_EN_3; > + break; > + } > + > phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, > - LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | > - LANE_EN_1 | LANE_EN_0); > + LANE_EN_MASK, LANE_EN_CK | val); > } > > static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) > @@ -680,12 +753,21 @@ static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = { > .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz, > .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz), > .max_rate = MAX_1GHZ, > + .max_lanes = 4, > +}; > + > +static const struct inno_video_phy_plat_data max_1_5ghz_video_phy_plat_data = { > + .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz, > + .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz), > + .max_rate = MAX_1_5GHZ, > + .max_lanes = 2, > }; > > static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = { > .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz, > .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz), > .max_rate = MAX_2_5GHZ, > + .max_lanes = 4, > }; > > static int inno_dsidphy_probe(struct platform_device *pdev) > @@ -767,6 +849,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = { > }, { > .compatible = "rockchip,rk3368-dsi-dphy", > .data = &max_1ghz_video_phy_plat_data, > + }, { > + .compatible = "rockchip,rk3506-dsi-dphy", > + .data = &max_1_5ghz_video_phy_plat_data, > }, { > .compatible = "rockchip,rk3568-dsi-dphy", > .data = &max_2_5ghz_video_phy_plat_data, Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 7/9] drm/rockchip: dsi: Add support for rk3506 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 2:06 ` Chaoyi Chen -1 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen, Hongming Zou From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The dsi controller found on RK3506 supports up to 2 lanes. Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 5523911b990d..06e58cf287d3 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -192,6 +192,11 @@ #define RK3568_DSI0_TURNDISABLE BIT(2) #define RK3568_DSI0_FORCERXMODE BIT(0) +#define RK3506_SYS_GRF_SOC_CON6 0x0018 +#define RK3506_DSI_FORCETXSTOPMODE (0xf << 4) +#define RK3506_DSI_TURNDISABLE BIT(2) +#define RK3506_DSI_FORCERXMODE BIT(0) + /* * Note these registers do not appear in the datasheet, they are * however present in the BSP driver which is where these values @@ -1643,6 +1648,18 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { { /* sentinel */ } }; +static const struct rockchip_dw_dsi_chip_data rk3506_chip_data[] = { + { + .reg = 0xff640000, + .lanecfg1_grf_reg = RK3506_SYS_GRF_SOC_CON6, + .lanecfg1 = (FIELD_PREP_WM16_CONST(RK3506_DSI_TURNDISABLE, 0) | + FIELD_PREP_WM16_CONST(RK3506_DSI_FORCERXMODE, 0) | + FIELD_PREP_WM16_CONST(RK3506_DSI_FORCETXSTOPMODE, 0)), + .max_data_lanes = 2, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { { .reg = 0xfe060000, @@ -1690,6 +1707,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { }, { .compatible = "rockchip,rk3399-mipi-dsi", .data = &rk3399_chip_data, + }, { + .compatible = "rockchip,rk3506-mipi-dsi", + .data = &rk3506_chip_data, }, { .compatible = "rockchip,rk3568-mipi-dsi", .data = &rk3568_chip_data, -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 7/9] drm/rockchip: dsi: Add support for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen, Hongming Zou From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The dsi controller found on RK3506 supports up to 2 lanes. Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 5523911b990d..06e58cf287d3 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -192,6 +192,11 @@ #define RK3568_DSI0_TURNDISABLE BIT(2) #define RK3568_DSI0_FORCERXMODE BIT(0) +#define RK3506_SYS_GRF_SOC_CON6 0x0018 +#define RK3506_DSI_FORCETXSTOPMODE (0xf << 4) +#define RK3506_DSI_TURNDISABLE BIT(2) +#define RK3506_DSI_FORCERXMODE BIT(0) + /* * Note these registers do not appear in the datasheet, they are * however present in the BSP driver which is where these values @@ -1643,6 +1648,18 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { { /* sentinel */ } }; +static const struct rockchip_dw_dsi_chip_data rk3506_chip_data[] = { + { + .reg = 0xff640000, + .lanecfg1_grf_reg = RK3506_SYS_GRF_SOC_CON6, + .lanecfg1 = (FIELD_PREP_WM16_CONST(RK3506_DSI_TURNDISABLE, 0) | + FIELD_PREP_WM16_CONST(RK3506_DSI_FORCERXMODE, 0) | + FIELD_PREP_WM16_CONST(RK3506_DSI_FORCETXSTOPMODE, 0)), + .max_data_lanes = 2, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { { .reg = 0xfe060000, @@ -1690,6 +1707,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { }, { .compatible = "rockchip,rk3399-mipi-dsi", .data = &rk3399_chip_data, + }, { + .compatible = "rockchip,rk3506-mipi-dsi", + .data = &rk3506_chip_data, }, { .compatible = "rockchip,rk3568-mipi-dsi", .data = &rk3568_chip_data, -- 2.51.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 7/9] drm/rockchip: dsi: Add support for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen, Hongming Zou From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The dsi controller found on RK3506 supports up to 2 lanes. Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 5523911b990d..06e58cf287d3 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -192,6 +192,11 @@ #define RK3568_DSI0_TURNDISABLE BIT(2) #define RK3568_DSI0_FORCERXMODE BIT(0) +#define RK3506_SYS_GRF_SOC_CON6 0x0018 +#define RK3506_DSI_FORCETXSTOPMODE (0xf << 4) +#define RK3506_DSI_TURNDISABLE BIT(2) +#define RK3506_DSI_FORCERXMODE BIT(0) + /* * Note these registers do not appear in the datasheet, they are * however present in the BSP driver which is where these values @@ -1643,6 +1648,18 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { { /* sentinel */ } }; +static const struct rockchip_dw_dsi_chip_data rk3506_chip_data[] = { + { + .reg = 0xff640000, + .lanecfg1_grf_reg = RK3506_SYS_GRF_SOC_CON6, + .lanecfg1 = (FIELD_PREP_WM16_CONST(RK3506_DSI_TURNDISABLE, 0) | + FIELD_PREP_WM16_CONST(RK3506_DSI_FORCERXMODE, 0) | + FIELD_PREP_WM16_CONST(RK3506_DSI_FORCETXSTOPMODE, 0)), + .max_data_lanes = 2, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { { .reg = 0xfe060000, @@ -1690,6 +1707,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { }, { .compatible = "rockchip,rk3399-mipi-dsi", .data = &rk3399_chip_data, + }, { + .compatible = "rockchip,rk3506-mipi-dsi", + .data = &rk3506_chip_data, }, { .compatible = "rockchip,rk3568-mipi-dsi", .data = &rk3568_chip_data, -- 2.51.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 2:06 ` Chaoyi Chen -1 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> On the RK3506 platform, there is no iommu hardware. And even on platform that have iommu hardware, it should be possible to use VOP without enabling iommu. In this case, a contiguous memory space like CMA should be used. So this patch removes the dependency on ROCKCHIP_IOMMU. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- drivers/gpu/drm/rockchip/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index b7b025814e72..a056d419190c 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_ROCKCHIP tristate "DRM Support for Rockchip" - depends on DRM && ROCKCHIP_IOMMU + depends on DRM + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU depends on OF select DRM_CLIENT_SELECTION select DRM_GEM_DMA_HELPER -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> On the RK3506 platform, there is no iommu hardware. And even on platform that have iommu hardware, it should be possible to use VOP without enabling iommu. In this case, a contiguous memory space like CMA should be used. So this patch removes the dependency on ROCKCHIP_IOMMU. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- drivers/gpu/drm/rockchip/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index b7b025814e72..a056d419190c 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_ROCKCHIP tristate "DRM Support for Rockchip" - depends on DRM && ROCKCHIP_IOMMU + depends on DRM + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU depends on OF select DRM_CLIENT_SELECTION select DRM_GEM_DMA_HELPER -- 2.51.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> On the RK3506 platform, there is no iommu hardware. And even on platform that have iommu hardware, it should be possible to use VOP without enabling iommu. In this case, a contiguous memory space like CMA should be used. So this patch removes the dependency on ROCKCHIP_IOMMU. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- drivers/gpu/drm/rockchip/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index b7b025814e72..a056d419190c 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_ROCKCHIP tristate "DRM Support for Rockchip" - depends on DRM && ROCKCHIP_IOMMU + depends on DRM + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU depends on OF select DRM_CLIENT_SELECTION select DRM_GEM_DMA_HELPER -- 2.51.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2026-01-08 19:03 ` Heiko Stuebner -1 siblings, 0 replies; 71+ messages in thread From: Heiko Stuebner @ 2026-01-08 19:03 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen Am Donnerstag, 6. November 2025, 03:06:31 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > On the RK3506 platform, there is no iommu hardware. And even on > platform that have iommu hardware, it should be possible to use > VOP without enabling iommu. In this case, a contiguous memory > space like CMA should be used. > > So this patch removes the dependency on ROCKCHIP_IOMMU. > > Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > --- > drivers/gpu/drm/rockchip/Kconfig | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig > index b7b025814e72..a056d419190c 100644 > --- a/drivers/gpu/drm/rockchip/Kconfig > +++ b/drivers/gpu/drm/rockchip/Kconfig > @@ -1,7 +1,8 @@ > # SPDX-License-Identifier: GPL-2.0-only > config DRM_ROCKCHIP > tristate "DRM Support for Rockchip" > - depends on DRM && ROCKCHIP_IOMMU > + depends on DRM > + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU I don't really understand this yes+no line :-) Can't you just - drop the dependency altogether or - do a depends on ROCKCHIP_IOMMU if ARM64 Heiko > depends on OF > select DRM_CLIENT_SELECTION > select DRM_GEM_DMA_HELPER > ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP @ 2026-01-08 19:03 ` Heiko Stuebner 0 siblings, 0 replies; 71+ messages in thread From: Heiko Stuebner @ 2026-01-08 19:03 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen Am Donnerstag, 6. November 2025, 03:06:31 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > On the RK3506 platform, there is no iommu hardware. And even on > platform that have iommu hardware, it should be possible to use > VOP without enabling iommu. In this case, a contiguous memory > space like CMA should be used. > > So this patch removes the dependency on ROCKCHIP_IOMMU. > > Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > --- > drivers/gpu/drm/rockchip/Kconfig | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig > index b7b025814e72..a056d419190c 100644 > --- a/drivers/gpu/drm/rockchip/Kconfig > +++ b/drivers/gpu/drm/rockchip/Kconfig > @@ -1,7 +1,8 @@ > # SPDX-License-Identifier: GPL-2.0-only > config DRM_ROCKCHIP > tristate "DRM Support for Rockchip" > - depends on DRM && ROCKCHIP_IOMMU > + depends on DRM > + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU I don't really understand this yes+no line :-) Can't you just - drop the dependency altogether or - do a depends on ROCKCHIP_IOMMU if ARM64 Heiko > depends on OF > select DRM_CLIENT_SELECTION > select DRM_GEM_DMA_HELPER > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP @ 2026-01-08 19:03 ` Heiko Stuebner 0 siblings, 0 replies; 71+ messages in thread From: Heiko Stuebner @ 2026-01-08 19:03 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen Am Donnerstag, 6. November 2025, 03:06:31 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > On the RK3506 platform, there is no iommu hardware. And even on > platform that have iommu hardware, it should be possible to use > VOP without enabling iommu. In this case, a contiguous memory > space like CMA should be used. > > So this patch removes the dependency on ROCKCHIP_IOMMU. > > Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > --- > drivers/gpu/drm/rockchip/Kconfig | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig > index b7b025814e72..a056d419190c 100644 > --- a/drivers/gpu/drm/rockchip/Kconfig > +++ b/drivers/gpu/drm/rockchip/Kconfig > @@ -1,7 +1,8 @@ > # SPDX-License-Identifier: GPL-2.0-only > config DRM_ROCKCHIP > tristate "DRM Support for Rockchip" > - depends on DRM && ROCKCHIP_IOMMU > + depends on DRM > + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU I don't really understand this yes+no line :-) Can't you just - drop the dependency altogether or - do a depends on ROCKCHIP_IOMMU if ARM64 Heiko > depends on OF > select DRM_CLIENT_SELECTION > select DRM_GEM_DMA_HELPER > -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP 2026-01-08 19:03 ` Heiko Stuebner (?) @ 2026-01-09 1:26 ` Chaoyi Chen -1 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2026-01-09 1:26 UTC (permalink / raw) To: Heiko Stuebner, Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy Hi Heiko, On 1/9/2026 3:03 AM, Heiko Stuebner wrote: > Am Donnerstag, 6. November 2025, 03:06:31 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: >> From: Chaoyi Chen <chaoyi.chen@rock-chips.com> >> >> On the RK3506 platform, there is no iommu hardware. And even on >> platform that have iommu hardware, it should be possible to use >> VOP without enabling iommu. In this case, a contiguous memory >> space like CMA should be used. >> >> So this patch removes the dependency on ROCKCHIP_IOMMU. >> >> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> >> --- >> drivers/gpu/drm/rockchip/Kconfig | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig >> index b7b025814e72..a056d419190c 100644 >> --- a/drivers/gpu/drm/rockchip/Kconfig >> +++ b/drivers/gpu/drm/rockchip/Kconfig >> @@ -1,7 +1,8 @@ >> # SPDX-License-Identifier: GPL-2.0-only >> config DRM_ROCKCHIP >> tristate "DRM Support for Rockchip" >> - depends on DRM && ROCKCHIP_IOMMU >> + depends on DRM >> + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU > > I don't really understand this yes+no line :-) > > Can't you just > - drop the dependency altogether > or > - do a depends on ROCKCHIP_IOMMU if ARM64 > > This trick is called optional-dependencies [0]. In addition to the familiar depends on ROCKCHIP_IOMMU part, the newly added !ROCKCHIP_IOMMU ensures that DRM_ROCKCHIP can still be built even when ROCKCHIP_IOMMU is not build. [0]: https://docs.kernel.org/kbuild/kconfig-language.html#optional-dependencies If we just: - drop the dependency altogether When IOMMU is enabled, the dependency relationship cannot be handled correctly. For example, the following configuration is possible: ROCKCHIP_IOMMU=m, DRM_ROCKCHIP=y, which leads to a build failure. - do a depends on ROCKCHIP_IOMMU if ARM64 This changes the semantics. On arm64 we should also be able to work without IOMMU being enabled. -- Best, Chaoyi ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP @ 2026-01-09 1:26 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2026-01-09 1:26 UTC (permalink / raw) To: Heiko Stuebner, Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy Hi Heiko, On 1/9/2026 3:03 AM, Heiko Stuebner wrote: > Am Donnerstag, 6. November 2025, 03:06:31 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: >> From: Chaoyi Chen <chaoyi.chen@rock-chips.com> >> >> On the RK3506 platform, there is no iommu hardware. And even on >> platform that have iommu hardware, it should be possible to use >> VOP without enabling iommu. In this case, a contiguous memory >> space like CMA should be used. >> >> So this patch removes the dependency on ROCKCHIP_IOMMU. >> >> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> >> --- >> drivers/gpu/drm/rockchip/Kconfig | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig >> index b7b025814e72..a056d419190c 100644 >> --- a/drivers/gpu/drm/rockchip/Kconfig >> +++ b/drivers/gpu/drm/rockchip/Kconfig >> @@ -1,7 +1,8 @@ >> # SPDX-License-Identifier: GPL-2.0-only >> config DRM_ROCKCHIP >> tristate "DRM Support for Rockchip" >> - depends on DRM && ROCKCHIP_IOMMU >> + depends on DRM >> + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU > > I don't really understand this yes+no line :-) > > Can't you just > - drop the dependency altogether > or > - do a depends on ROCKCHIP_IOMMU if ARM64 > > This trick is called optional-dependencies [0]. In addition to the familiar depends on ROCKCHIP_IOMMU part, the newly added !ROCKCHIP_IOMMU ensures that DRM_ROCKCHIP can still be built even when ROCKCHIP_IOMMU is not build. [0]: https://docs.kernel.org/kbuild/kconfig-language.html#optional-dependencies If we just: - drop the dependency altogether When IOMMU is enabled, the dependency relationship cannot be handled correctly. For example, the following configuration is possible: ROCKCHIP_IOMMU=m, DRM_ROCKCHIP=y, which leads to a build failure. - do a depends on ROCKCHIP_IOMMU if ARM64 This changes the semantics. On arm64 we should also be able to work without IOMMU being enabled. -- Best, Chaoyi _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP @ 2026-01-09 1:26 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2026-01-09 1:26 UTC (permalink / raw) To: Heiko Stuebner, Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy Hi Heiko, On 1/9/2026 3:03 AM, Heiko Stuebner wrote: > Am Donnerstag, 6. November 2025, 03:06:31 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: >> From: Chaoyi Chen <chaoyi.chen@rock-chips.com> >> >> On the RK3506 platform, there is no iommu hardware. And even on >> platform that have iommu hardware, it should be possible to use >> VOP without enabling iommu. In this case, a contiguous memory >> space like CMA should be used. >> >> So this patch removes the dependency on ROCKCHIP_IOMMU. >> >> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> >> --- >> drivers/gpu/drm/rockchip/Kconfig | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig >> index b7b025814e72..a056d419190c 100644 >> --- a/drivers/gpu/drm/rockchip/Kconfig >> +++ b/drivers/gpu/drm/rockchip/Kconfig >> @@ -1,7 +1,8 @@ >> # SPDX-License-Identifier: GPL-2.0-only >> config DRM_ROCKCHIP >> tristate "DRM Support for Rockchip" >> - depends on DRM && ROCKCHIP_IOMMU >> + depends on DRM >> + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU > > I don't really understand this yes+no line :-) > > Can't you just > - drop the dependency altogether > or > - do a depends on ROCKCHIP_IOMMU if ARM64 > > This trick is called optional-dependencies [0]. In addition to the familiar depends on ROCKCHIP_IOMMU part, the newly added !ROCKCHIP_IOMMU ensures that DRM_ROCKCHIP can still be built even when ROCKCHIP_IOMMU is not build. [0]: https://docs.kernel.org/kbuild/kconfig-language.html#optional-dependencies If we just: - drop the dependency altogether When IOMMU is enabled, the dependency relationship cannot be handled correctly. For example, the following configuration is possible: ROCKCHIP_IOMMU=m, DRM_ROCKCHIP=y, which leads to a build failure. - do a depends on ROCKCHIP_IOMMU if ARM64 This changes the semantics. On arm64 we should also be able to work without IOMMU being enabled. -- Best, Chaoyi -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP 2026-01-09 1:26 ` Chaoyi Chen (?) @ 2026-01-09 10:51 ` Heiko Stübner -1 siblings, 0 replies; 71+ messages in thread From: Heiko Stübner @ 2026-01-09 10:51 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy Hi, Am Freitag, 9. Januar 2026, 02:26:00 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: > On 1/9/2026 3:03 AM, Heiko Stuebner wrote: > > Am Donnerstag, 6. November 2025, 03:06:31 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: > >> From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > >> > >> On the RK3506 platform, there is no iommu hardware. And even on > >> platform that have iommu hardware, it should be possible to use > >> VOP without enabling iommu. In this case, a contiguous memory > >> space like CMA should be used. > >> > >> So this patch removes the dependency on ROCKCHIP_IOMMU. > >> > >> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > >> --- > >> drivers/gpu/drm/rockchip/Kconfig | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig > >> index b7b025814e72..a056d419190c 100644 > >> --- a/drivers/gpu/drm/rockchip/Kconfig > >> +++ b/drivers/gpu/drm/rockchip/Kconfig > >> @@ -1,7 +1,8 @@ > >> # SPDX-License-Identifier: GPL-2.0-only > >> config DRM_ROCKCHIP > >> tristate "DRM Support for Rockchip" > >> - depends on DRM && ROCKCHIP_IOMMU > >> + depends on DRM > >> + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU > > > > I don't really understand this yes+no line :-) > > > > Can't you just > > - drop the dependency altogether > > or > > - do a depends on ROCKCHIP_IOMMU if ARM64 > > > > > > This trick is called optional-dependencies [0]. In addition to the > familiar depends on ROCKCHIP_IOMMU part, the newly added !ROCKCHIP_IOMMU > ensures that DRM_ROCKCHIP can still be built even when ROCKCHIP_IOMMU > is not build. > > [0]: https://docs.kernel.org/kbuild/kconfig-language.html#optional-dependencies thanks a lot for pointing me to this nifty feature :-) Heiko ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP @ 2026-01-09 10:51 ` Heiko Stübner 0 siblings, 0 replies; 71+ messages in thread From: Heiko Stübner @ 2026-01-09 10:51 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy Hi, Am Freitag, 9. Januar 2026, 02:26:00 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: > On 1/9/2026 3:03 AM, Heiko Stuebner wrote: > > Am Donnerstag, 6. November 2025, 03:06:31 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: > >> From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > >> > >> On the RK3506 platform, there is no iommu hardware. And even on > >> platform that have iommu hardware, it should be possible to use > >> VOP without enabling iommu. In this case, a contiguous memory > >> space like CMA should be used. > >> > >> So this patch removes the dependency on ROCKCHIP_IOMMU. > >> > >> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > >> --- > >> drivers/gpu/drm/rockchip/Kconfig | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig > >> index b7b025814e72..a056d419190c 100644 > >> --- a/drivers/gpu/drm/rockchip/Kconfig > >> +++ b/drivers/gpu/drm/rockchip/Kconfig > >> @@ -1,7 +1,8 @@ > >> # SPDX-License-Identifier: GPL-2.0-only > >> config DRM_ROCKCHIP > >> tristate "DRM Support for Rockchip" > >> - depends on DRM && ROCKCHIP_IOMMU > >> + depends on DRM > >> + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU > > > > I don't really understand this yes+no line :-) > > > > Can't you just > > - drop the dependency altogether > > or > > - do a depends on ROCKCHIP_IOMMU if ARM64 > > > > > > This trick is called optional-dependencies [0]. In addition to the > familiar depends on ROCKCHIP_IOMMU part, the newly added !ROCKCHIP_IOMMU > ensures that DRM_ROCKCHIP can still be built even when ROCKCHIP_IOMMU > is not build. > > [0]: https://docs.kernel.org/kbuild/kconfig-language.html#optional-dependencies thanks a lot for pointing me to this nifty feature :-) Heiko _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP @ 2026-01-09 10:51 ` Heiko Stübner 0 siblings, 0 replies; 71+ messages in thread From: Heiko Stübner @ 2026-01-09 10:51 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy Hi, Am Freitag, 9. Januar 2026, 02:26:00 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: > On 1/9/2026 3:03 AM, Heiko Stuebner wrote: > > Am Donnerstag, 6. November 2025, 03:06:31 Mitteleuropäische Normalzeit schrieb Chaoyi Chen: > >> From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > >> > >> On the RK3506 platform, there is no iommu hardware. And even on > >> platform that have iommu hardware, it should be possible to use > >> VOP without enabling iommu. In this case, a contiguous memory > >> space like CMA should be used. > >> > >> So this patch removes the dependency on ROCKCHIP_IOMMU. > >> > >> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> > >> --- > >> drivers/gpu/drm/rockchip/Kconfig | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig > >> index b7b025814e72..a056d419190c 100644 > >> --- a/drivers/gpu/drm/rockchip/Kconfig > >> +++ b/drivers/gpu/drm/rockchip/Kconfig > >> @@ -1,7 +1,8 @@ > >> # SPDX-License-Identifier: GPL-2.0-only > >> config DRM_ROCKCHIP > >> tristate "DRM Support for Rockchip" > >> - depends on DRM && ROCKCHIP_IOMMU > >> + depends on DRM > >> + depends on ROCKCHIP_IOMMU || !ROCKCHIP_IOMMU > > > > I don't really understand this yes+no line :-) > > > > Can't you just > > - drop the dependency altogether > > or > > - do a depends on ROCKCHIP_IOMMU if ARM64 > > > > > > This trick is called optional-dependencies [0]. In addition to the > familiar depends on ROCKCHIP_IOMMU part, the newly added !ROCKCHIP_IOMMU > ensures that DRM_ROCKCHIP can still be built even when ROCKCHIP_IOMMU > is not build. > > [0]: https://docs.kernel.org/kbuild/kconfig-language.html#optional-dependencies thanks a lot for pointing me to this nifty feature :-) Heiko -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 9/9] drm/rockchip: vop: Add support for rk3506 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-06 2:06 ` Chaoyi Chen -1 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The VOP on rk3506: - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. - Support RGB interface. - Max output resolution is 1280x1280@60fps. - WIN1 layer support RGB888/ARGB8888/RGB565. - Support Gamma LUT. - ... Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 57 +++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 14 +++++ 2 files changed, 71 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index d1f788763318..6b654b682a94 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -1179,6 +1179,61 @@ static const struct vop_data rk3328_vop = { .max_output = { 4096, 2160 }, }; +static const struct vop_common rk3506_common = { + .standby = VOP_REG_SYNC(RK3506_SYS_CTRL2, 0x1, 1), + .out_mode = VOP_REG(RK3506_DSP_CTRL2, 0xf, 16), + .dsp_blank = VOP_REG(RK3506_DSP_CTRL2, 0x1, 14), + .dither_down_en = VOP_REG(RK3506_DSP_CTRL2, 0x1, 8), + .dither_down_sel = VOP_REG(RK3506_DSP_CTRL2, 0x1, 7), + .dither_down_mode = VOP_REG(RK3506_DSP_CTRL2, 0x1, 6), + .dsp_lut_en = VOP_REG(RK3506_DSP_CTRL2, 0x1, 5), + .dither_up = VOP_REG(RK3506_DSP_CTRL2, 0x1, 2), + .cfg_done = VOP_REG_SYNC(RK3506_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_output rk3506_output = { + .rgb_en = VOP_REG(RK3506_DSP_CTRL0, 0x1, 0), + .rgb_pin_pol = VOP_REG(RK3506_DSP_CTRL0, 0x7, 2), + .mipi_en = VOP_REG(RK3506_DSP_CTRL0, 0x1, 24), + .mipi_dclk_pol = VOP_REG(RK3506_DSP_CTRL0, 0x1, 25), + .mipi_pin_pol = VOP_REG(RK3506_DSP_CTRL0, 0x7, 26), +}; + +static const struct vop_win_phy rk3506_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .format_modifiers = format_modifiers_win_lite, + .enable = VOP_REG(RK3506_WIN1_CTRL0, 0x1, 0), + .format = VOP_REG(RK3506_WIN1_CTRL0, 0x7, 4), + .rb_swap = VOP_REG(RK3506_WIN1_CTRL0, 0x1, 12), + .channel = VOP_REG(RK3506_WIN1_CTRL1, 0xf, 8), + .yrgb_vir = VOP_REG(RK3506_WIN1_VIR, 0x1fff, 0), + .yrgb_mst = VOP_REG(RK3506_WIN1_MST, 0xffffffff, 0), + .dsp_info = VOP_REG(RK3506_WIN1_DSP_INFO, 0xffffffff, 0), + .dsp_st = VOP_REG(RK3506_WIN1_DSP_ST, 0xffffffff, 0), + .alpha_en = VOP_REG(RK3506_WIN1_ALPHA_CTRL, 0x1, 0), + .alpha_mode = VOP_REG(RK3506_WIN1_ALPHA_CTRL, 0x1, 1), + .alpha_pre_mul = VOP_REG(RK3506_WIN1_ALPHA_CTRL, 0x1, 2), +}; + +static const struct vop_win_data rk3506_vop_win_data[] = { + { .base = 0x00, .phy = &rk3506_win1_data, + .type = DRM_PLANE_TYPE_PRIMARY }, +}; + +static const struct vop_data rk3506_vop = { + .version = VOP_VERSION(2, 0xe), + .feature = VOP_FEATURE_INTERNAL_RGB, + .intr = &px30_intr, + .common = &rk3506_common, + .modeset = &px30_modeset, + .output = &rk3506_output, + .win = rk3506_vop_win_data, + .win_size = ARRAY_SIZE(rk3506_vop_win_data), + .lut_size = 256, + .max_output = { 1280, 1280 }, +}; + static const struct vop_common rv1126_common = { .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), @@ -1259,6 +1314,8 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3228_vop }, { .compatible = "rockchip,rk3328-vop", .data = &rk3328_vop }, + { .compatible = "rockchip,rk3506-vop", + .data = &rk3506_vop }, { .compatible = "rockchip,rv1126-vop", .data = &rv1126_vop }, {}, diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index addf8ca085f6..7805533e88bc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1033,4 +1033,18 @@ #define RK3066_DSP_LUT_ADDR 0x800 /* rk3066 register definition end */ +/* rk3506 register definition */ +#define RK3506_REG_CFG_DONE 0x00 +#define RK3506_SYS_CTRL2 0x18 +#define RK3506_DSP_CTRL0 0x20 +#define RK3506_DSP_CTRL2 0x28 +#define RK3506_WIN1_CTRL0 0x90 +#define RK3506_WIN1_CTRL1 0x94 +#define RK3506_WIN1_VIR 0x98 +#define RK3506_WIN1_MST 0xa0 +#define RK3506_WIN1_DSP_INFO 0xa4 +#define RK3506_WIN1_DSP_ST 0xa8 +#define RK3506_WIN1_ALPHA_CTRL 0xbc +/* rk3506 register definition end */ + #endif /* _ROCKCHIP_VOP_REG_H */ -- 2.51.1 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 9/9] drm/rockchip: vop: Add support for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The VOP on rk3506: - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. - Support RGB interface. - Max output resolution is 1280x1280@60fps. - WIN1 layer support RGB888/ARGB8888/RGB565. - Support Gamma LUT. - ... Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 57 +++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 14 +++++ 2 files changed, 71 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index d1f788763318..6b654b682a94 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -1179,6 +1179,61 @@ static const struct vop_data rk3328_vop = { .max_output = { 4096, 2160 }, }; +static const struct vop_common rk3506_common = { + .standby = VOP_REG_SYNC(RK3506_SYS_CTRL2, 0x1, 1), + .out_mode = VOP_REG(RK3506_DSP_CTRL2, 0xf, 16), + .dsp_blank = VOP_REG(RK3506_DSP_CTRL2, 0x1, 14), + .dither_down_en = VOP_REG(RK3506_DSP_CTRL2, 0x1, 8), + .dither_down_sel = VOP_REG(RK3506_DSP_CTRL2, 0x1, 7), + .dither_down_mode = VOP_REG(RK3506_DSP_CTRL2, 0x1, 6), + .dsp_lut_en = VOP_REG(RK3506_DSP_CTRL2, 0x1, 5), + .dither_up = VOP_REG(RK3506_DSP_CTRL2, 0x1, 2), + .cfg_done = VOP_REG_SYNC(RK3506_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_output rk3506_output = { + .rgb_en = VOP_REG(RK3506_DSP_CTRL0, 0x1, 0), + .rgb_pin_pol = VOP_REG(RK3506_DSP_CTRL0, 0x7, 2), + .mipi_en = VOP_REG(RK3506_DSP_CTRL0, 0x1, 24), + .mipi_dclk_pol = VOP_REG(RK3506_DSP_CTRL0, 0x1, 25), + .mipi_pin_pol = VOP_REG(RK3506_DSP_CTRL0, 0x7, 26), +}; + +static const struct vop_win_phy rk3506_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .format_modifiers = format_modifiers_win_lite, + .enable = VOP_REG(RK3506_WIN1_CTRL0, 0x1, 0), + .format = VOP_REG(RK3506_WIN1_CTRL0, 0x7, 4), + .rb_swap = VOP_REG(RK3506_WIN1_CTRL0, 0x1, 12), + .channel = VOP_REG(RK3506_WIN1_CTRL1, 0xf, 8), + .yrgb_vir = VOP_REG(RK3506_WIN1_VIR, 0x1fff, 0), + .yrgb_mst = VOP_REG(RK3506_WIN1_MST, 0xffffffff, 0), + .dsp_info = VOP_REG(RK3506_WIN1_DSP_INFO, 0xffffffff, 0), + .dsp_st = VOP_REG(RK3506_WIN1_DSP_ST, 0xffffffff, 0), + .alpha_en = VOP_REG(RK3506_WIN1_ALPHA_CTRL, 0x1, 0), + .alpha_mode = VOP_REG(RK3506_WIN1_ALPHA_CTRL, 0x1, 1), + .alpha_pre_mul = VOP_REG(RK3506_WIN1_ALPHA_CTRL, 0x1, 2), +}; + +static const struct vop_win_data rk3506_vop_win_data[] = { + { .base = 0x00, .phy = &rk3506_win1_data, + .type = DRM_PLANE_TYPE_PRIMARY }, +}; + +static const struct vop_data rk3506_vop = { + .version = VOP_VERSION(2, 0xe), + .feature = VOP_FEATURE_INTERNAL_RGB, + .intr = &px30_intr, + .common = &rk3506_common, + .modeset = &px30_modeset, + .output = &rk3506_output, + .win = rk3506_vop_win_data, + .win_size = ARRAY_SIZE(rk3506_vop_win_data), + .lut_size = 256, + .max_output = { 1280, 1280 }, +}; + static const struct vop_common rv1126_common = { .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), @@ -1259,6 +1314,8 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3228_vop }, { .compatible = "rockchip,rk3328-vop", .data = &rk3328_vop }, + { .compatible = "rockchip,rk3506-vop", + .data = &rk3506_vop }, { .compatible = "rockchip,rv1126-vop", .data = &rv1126_vop }, {}, diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index addf8ca085f6..7805533e88bc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1033,4 +1033,18 @@ #define RK3066_DSP_LUT_ADDR 0x800 /* rk3066 register definition end */ +/* rk3506 register definition */ +#define RK3506_REG_CFG_DONE 0x00 +#define RK3506_SYS_CTRL2 0x18 +#define RK3506_DSP_CTRL0 0x20 +#define RK3506_DSP_CTRL2 0x28 +#define RK3506_WIN1_CTRL0 0x90 +#define RK3506_WIN1_CTRL1 0x94 +#define RK3506_WIN1_VIR 0x98 +#define RK3506_WIN1_MST 0xa0 +#define RK3506_WIN1_DSP_INFO 0xa4 +#define RK3506_WIN1_DSP_ST 0xa8 +#define RK3506_WIN1_ALPHA_CTRL 0xbc +/* rk3506 register definition end */ + #endif /* _ROCKCHIP_VOP_REG_H */ -- 2.51.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 9/9] drm/rockchip: vop: Add support for rk3506 @ 2025-11-06 2:06 ` Chaoyi Chen 0 siblings, 0 replies; 71+ messages in thread From: Chaoyi Chen @ 2025-11-06 2:06 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen From: Chaoyi Chen <chaoyi.chen@rock-chips.com> The VOP on rk3506: - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. - Support RGB interface. - Max output resolution is 1280x1280@60fps. - WIN1 layer support RGB888/ARGB8888/RGB565. - Support Gamma LUT. - ... Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 57 +++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 14 +++++ 2 files changed, 71 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index d1f788763318..6b654b682a94 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -1179,6 +1179,61 @@ static const struct vop_data rk3328_vop = { .max_output = { 4096, 2160 }, }; +static const struct vop_common rk3506_common = { + .standby = VOP_REG_SYNC(RK3506_SYS_CTRL2, 0x1, 1), + .out_mode = VOP_REG(RK3506_DSP_CTRL2, 0xf, 16), + .dsp_blank = VOP_REG(RK3506_DSP_CTRL2, 0x1, 14), + .dither_down_en = VOP_REG(RK3506_DSP_CTRL2, 0x1, 8), + .dither_down_sel = VOP_REG(RK3506_DSP_CTRL2, 0x1, 7), + .dither_down_mode = VOP_REG(RK3506_DSP_CTRL2, 0x1, 6), + .dsp_lut_en = VOP_REG(RK3506_DSP_CTRL2, 0x1, 5), + .dither_up = VOP_REG(RK3506_DSP_CTRL2, 0x1, 2), + .cfg_done = VOP_REG_SYNC(RK3506_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_output rk3506_output = { + .rgb_en = VOP_REG(RK3506_DSP_CTRL0, 0x1, 0), + .rgb_pin_pol = VOP_REG(RK3506_DSP_CTRL0, 0x7, 2), + .mipi_en = VOP_REG(RK3506_DSP_CTRL0, 0x1, 24), + .mipi_dclk_pol = VOP_REG(RK3506_DSP_CTRL0, 0x1, 25), + .mipi_pin_pol = VOP_REG(RK3506_DSP_CTRL0, 0x7, 26), +}; + +static const struct vop_win_phy rk3506_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .format_modifiers = format_modifiers_win_lite, + .enable = VOP_REG(RK3506_WIN1_CTRL0, 0x1, 0), + .format = VOP_REG(RK3506_WIN1_CTRL0, 0x7, 4), + .rb_swap = VOP_REG(RK3506_WIN1_CTRL0, 0x1, 12), + .channel = VOP_REG(RK3506_WIN1_CTRL1, 0xf, 8), + .yrgb_vir = VOP_REG(RK3506_WIN1_VIR, 0x1fff, 0), + .yrgb_mst = VOP_REG(RK3506_WIN1_MST, 0xffffffff, 0), + .dsp_info = VOP_REG(RK3506_WIN1_DSP_INFO, 0xffffffff, 0), + .dsp_st = VOP_REG(RK3506_WIN1_DSP_ST, 0xffffffff, 0), + .alpha_en = VOP_REG(RK3506_WIN1_ALPHA_CTRL, 0x1, 0), + .alpha_mode = VOP_REG(RK3506_WIN1_ALPHA_CTRL, 0x1, 1), + .alpha_pre_mul = VOP_REG(RK3506_WIN1_ALPHA_CTRL, 0x1, 2), +}; + +static const struct vop_win_data rk3506_vop_win_data[] = { + { .base = 0x00, .phy = &rk3506_win1_data, + .type = DRM_PLANE_TYPE_PRIMARY }, +}; + +static const struct vop_data rk3506_vop = { + .version = VOP_VERSION(2, 0xe), + .feature = VOP_FEATURE_INTERNAL_RGB, + .intr = &px30_intr, + .common = &rk3506_common, + .modeset = &px30_modeset, + .output = &rk3506_output, + .win = rk3506_vop_win_data, + .win_size = ARRAY_SIZE(rk3506_vop_win_data), + .lut_size = 256, + .max_output = { 1280, 1280 }, +}; + static const struct vop_common rv1126_common = { .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), @@ -1259,6 +1314,8 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3228_vop }, { .compatible = "rockchip,rk3328-vop", .data = &rk3328_vop }, + { .compatible = "rockchip,rk3506-vop", + .data = &rk3506_vop }, { .compatible = "rockchip,rv1126-vop", .data = &rv1126_vop }, {}, diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index addf8ca085f6..7805533e88bc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1033,4 +1033,18 @@ #define RK3066_DSP_LUT_ADDR 0x800 /* rk3066 register definition end */ +/* rk3506 register definition */ +#define RK3506_REG_CFG_DONE 0x00 +#define RK3506_SYS_CTRL2 0x18 +#define RK3506_DSP_CTRL0 0x20 +#define RK3506_DSP_CTRL2 0x28 +#define RK3506_WIN1_CTRL0 0x90 +#define RK3506_WIN1_CTRL1 0x94 +#define RK3506_WIN1_VIR 0x98 +#define RK3506_WIN1_MST 0xa0 +#define RK3506_WIN1_DSP_INFO 0xa4 +#define RK3506_WIN1_DSP_ST 0xa8 +#define RK3506_WIN1_ALPHA_CTRL 0xbc +/* rk3506 register definition end */ + #endif /* _ROCKCHIP_VOP_REG_H */ -- 2.51.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-19 16:49 ` Neil Armstrong -1 siblings, 0 replies; 71+ messages in thread From: Neil Armstrong @ 2025-11-19 16:49 UTC (permalink / raw) To: Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen Hi, On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Thanks, Applied to https://gitlab.freedesktop.org/drm/misc/kernel.git (drm-misc-next) [1/9] dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/15e794bcbc9527736d33c96412ce077bd817d9af [5/9] drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/89b34ebed02ee39ae02069dcf2e5728aceec9deb -- Neil ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP @ 2025-11-19 16:49 ` Neil Armstrong 0 siblings, 0 replies; 71+ messages in thread From: Neil Armstrong @ 2025-11-19 16:49 UTC (permalink / raw) To: Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen Hi, On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Thanks, Applied to https://gitlab.freedesktop.org/drm/misc/kernel.git (drm-misc-next) [1/9] dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/15e794bcbc9527736d33c96412ce077bd817d9af [5/9] drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/89b34ebed02ee39ae02069dcf2e5728aceec9deb -- Neil _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP @ 2025-11-19 16:49 ` Neil Armstrong 0 siblings, 0 replies; 71+ messages in thread From: Neil Armstrong @ 2025-11-19 16:49 UTC (permalink / raw) To: Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen Hi, On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > From: Chaoyi Chen <chaoyi.chen@rock-chips.com> > > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Thanks, Applied to https://gitlab.freedesktop.org/drm/misc/kernel.git (drm-misc-next) [1/9] dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/15e794bcbc9527736d33c96412ce077bd817d9af [5/9] drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/89b34ebed02ee39ae02069dcf2e5728aceec9deb -- Neil -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2025-11-20 17:11 ` Vinod Koul -1 siblings, 0 replies; 71+ messages in thread From: Vinod Koul @ 2025-11-20 17:11 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Applied, thanks! [2/9] dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 commit: 323c5c05a0a07b931ede1fa0a3396a1a165ed798 [6/9] phy: rockchip: inno-dsidphy: Add support for rk3506 commit: 785a9d5bb145109558063080ebc9a3e8be86471d Best regards, -- ~Vinod ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP @ 2025-11-20 17:11 ` Vinod Koul 0 siblings, 0 replies; 71+ messages in thread From: Vinod Koul @ 2025-11-20 17:11 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Applied, thanks! [2/9] dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 commit: 323c5c05a0a07b931ede1fa0a3396a1a165ed798 [6/9] phy: rockchip: inno-dsidphy: Add support for rk3506 commit: 785a9d5bb145109558063080ebc9a3e8be86471d Best regards, -- ~Vinod _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP @ 2025-11-20 17:11 ` Vinod Koul 0 siblings, 0 replies; 71+ messages in thread From: Vinod Koul @ 2025-11-20 17:11 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Heiko Stübner, Andy Yan, Kishon Vijay Abraham I, Chaoyi Chen Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Applied, thanks! [2/9] dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 commit: 323c5c05a0a07b931ede1fa0a3396a1a165ed798 [6/9] phy: rockchip: inno-dsidphy: Add support for rk3506 commit: 785a9d5bb145109558063080ebc9a3e8be86471d Best regards, -- ~Vinod -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2026-01-08 19:04 ` Heiko Stuebner -1 siblings, 0 replies; 71+ messages in thread From: Heiko Stuebner @ 2026-01-08 19:04 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: Heiko Stuebner, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Applied, thanks! [3/9] dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 commit: 3af0f4d5d433921fa399bbe6396221c8a9985869 [4/9] dt-bindings: display: rockchip,vop: Add compatible for rk3506 commit: 7919273e495b9154cc7e5f7713f002290f4d9597 [7/9] drm/rockchip: dsi: Add support for rk3506 commit: cabeacc7eadc2d0033a2fc7304dfb900f9a32095 [9/9] drm/rockchip: vop: Add support for rk3506 commit: ec27500c8f2b65a3be6ce39a5844d6d246d1b2b0 Best regards, -- Heiko Stuebner <heiko@sntech.de> ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP @ 2026-01-08 19:04 ` Heiko Stuebner 0 siblings, 0 replies; 71+ messages in thread From: Heiko Stuebner @ 2026-01-08 19:04 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: Heiko Stuebner, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Applied, thanks! [3/9] dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 commit: 3af0f4d5d433921fa399bbe6396221c8a9985869 [4/9] dt-bindings: display: rockchip,vop: Add compatible for rk3506 commit: 7919273e495b9154cc7e5f7713f002290f4d9597 [7/9] drm/rockchip: dsi: Add support for rk3506 commit: cabeacc7eadc2d0033a2fc7304dfb900f9a32095 [9/9] drm/rockchip: vop: Add support for rk3506 commit: ec27500c8f2b65a3be6ce39a5844d6d246d1b2b0 Best regards, -- Heiko Stuebner <heiko@sntech.de> _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP @ 2026-01-08 19:04 ` Heiko Stuebner 0 siblings, 0 replies; 71+ messages in thread From: Heiko Stuebner @ 2026-01-08 19:04 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: Heiko Stuebner, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Applied, thanks! [3/9] dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506 commit: 3af0f4d5d433921fa399bbe6396221c8a9985869 [4/9] dt-bindings: display: rockchip,vop: Add compatible for rk3506 commit: 7919273e495b9154cc7e5f7713f002290f4d9597 [7/9] drm/rockchip: dsi: Add support for rk3506 commit: cabeacc7eadc2d0033a2fc7304dfb900f9a32095 [9/9] drm/rockchip: vop: Add support for rk3506 commit: ec27500c8f2b65a3be6ce39a5844d6d246d1b2b0 Best regards, -- Heiko Stuebner <heiko@sntech.de> -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP 2025-11-06 2:06 ` Chaoyi Chen (?) @ 2026-01-09 10:51 ` Heiko Stuebner -1 siblings, 0 replies; 71+ messages in thread From: Heiko Stuebner @ 2026-01-09 10:51 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: Heiko Stuebner, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Applied, thanks! [8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP commit: 0244539f9a4f3b564604dfe4d639f61cecec381a Best regards, -- Heiko Stuebner <heiko@sntech.de> ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP @ 2026-01-09 10:51 ` Heiko Stuebner 0 siblings, 0 replies; 71+ messages in thread From: Heiko Stuebner @ 2026-01-09 10:51 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: Heiko Stuebner, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Applied, thanks! [8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP commit: 0244539f9a4f3b564604dfe4d639f61cecec381a Best regards, -- Heiko Stuebner <heiko@sntech.de> _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP @ 2026-01-09 10:51 ` Heiko Stuebner 0 siblings, 0 replies; 71+ messages in thread From: Heiko Stuebner @ 2026-01-09 10:51 UTC (permalink / raw) To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sandy Huang, Andy Yan, Vinod Koul, Kishon Vijay Abraham I, Chaoyi Chen Cc: Heiko Stuebner, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-rockchip, linux-phy, Chaoyi Chen On Thu, 06 Nov 2025 10:06:23 +0800, Chaoyi Chen wrote: > The VOP on rk3506: > - Support 2 lane MIPI DSI interface, 1.5Gbps/lane. > - Support RGB interface. > - Max output resolution is 1280x1280@60fps. > - WIN1 layer support RGB888/ARGB8888/RGB565. > - Support Gamma LUT. > > [...] Applied, thanks! [8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP commit: 0244539f9a4f3b564604dfe4d639f61cecec381a Best regards, -- Heiko Stuebner <heiko@sntech.de> -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 71+ messages in thread
end of thread, other threads:[~2026-01-09 10:52 UTC | newest] Thread overview: 71+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-11-06 2:06 [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 2:06 ` [PATCH 1/9] dt-bindings: ili9881c: Add compatible string for Wanchanglong w552946aaa Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 17:28 ` Conor Dooley 2025-11-06 17:28 ` Conor Dooley 2025-11-06 17:28 ` Conor Dooley 2025-11-06 2:06 ` [PATCH 2/9] dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506 Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 17:27 ` Conor Dooley 2025-11-06 17:27 ` Conor Dooley 2025-11-06 17:27 ` Conor Dooley 2025-11-06 2:06 ` [PATCH 3/9] dt-bindings: display: rockchip,dw-mipi-dsi: " Chaoyi Chen 2025-11-06 2:06 ` [PATCH 3/9] dt-bindings: display: rockchip, dw-mipi-dsi: " Chaoyi Chen 2025-11-06 2:06 ` [PATCH 3/9] dt-bindings: display: rockchip,dw-mipi-dsi: " Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 17:27 ` Conor Dooley 2025-11-06 17:27 ` Conor Dooley 2025-11-06 17:27 ` Conor Dooley 2025-11-06 2:06 ` [PATCH 4/9] dt-bindings: display: rockchip,vop: " Chaoyi Chen 2025-11-06 2:06 ` [PATCH 4/9] dt-bindings: display: rockchip, vop: " Chaoyi Chen 2025-11-06 2:06 ` [PATCH 4/9] dt-bindings: display: rockchip,vop: " Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 17:27 ` Conor Dooley 2025-11-06 17:27 ` Conor Dooley 2025-11-06 17:27 ` Conor Dooley 2025-11-06 2:06 ` [PATCH 5/9] drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panel Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-18 13:50 ` Neil Armstrong 2025-11-18 13:50 ` Neil Armstrong 2025-11-18 13:50 ` Neil Armstrong 2025-11-06 2:06 ` [PATCH 6/9] phy: rockchip: inno-dsidphy: Add support for rk3506 Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-18 13:50 ` Neil Armstrong 2025-11-18 13:50 ` Neil Armstrong 2025-11-18 13:50 ` Neil Armstrong 2025-11-06 2:06 ` [PATCH 7/9] drm/rockchip: dsi: " Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 2:06 ` [PATCH 8/9] drm/rockchip: Drop ROCKCHIP_IOMMU depend for DRM_ROCKCHIP Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2026-01-08 19:03 ` Heiko Stuebner 2026-01-08 19:03 ` Heiko Stuebner 2026-01-08 19:03 ` Heiko Stuebner 2026-01-09 1:26 ` Chaoyi Chen 2026-01-09 1:26 ` Chaoyi Chen 2026-01-09 1:26 ` Chaoyi Chen 2026-01-09 10:51 ` Heiko Stübner 2026-01-09 10:51 ` Heiko Stübner 2026-01-09 10:51 ` Heiko Stübner 2025-11-06 2:06 ` [PATCH 9/9] drm/rockchip: vop: Add support for rk3506 Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-06 2:06 ` Chaoyi Chen 2025-11-19 16:49 ` (subset) [PATCH 0/9] drm/rockchip: Introduce Rockchip RK3506 VOP Neil Armstrong 2025-11-19 16:49 ` Neil Armstrong 2025-11-19 16:49 ` Neil Armstrong 2025-11-20 17:11 ` Vinod Koul 2025-11-20 17:11 ` Vinod Koul 2025-11-20 17:11 ` Vinod Koul 2026-01-08 19:04 ` Heiko Stuebner 2026-01-08 19:04 ` Heiko Stuebner 2026-01-08 19:04 ` Heiko Stuebner 2026-01-09 10:51 ` Heiko Stuebner 2026-01-09 10:51 ` Heiko Stuebner 2026-01-09 10:51 ` Heiko Stuebner
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.