From: Jeff Garzik <jgarzik@pobox.com>
To: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
Cc: Go Taniguchi <go@turbolinux.co.jp>,
linux-ide@vger.kernel.org, "Nakajima,
Jun" <jun.nakajima@intel.com>
Subject: Re: piix dma setup code
Date: Wed, 19 May 2004 18:31:52 -0400 [thread overview]
Message-ID: <40ABE058.7070705@pobox.com> (raw)
In-Reply-To: <200405191851.06281.bzolnier@elka.pw.edu.pl>
(added Jun to CC)
Bartlomiej Zolnierkiewicz wrote:
> On Tuesday 18 of May 2004 13:19, Go Taniguchi wrote:
>>If speed is XFER_UDMA_6, base clock is set to low base clock.
>>It should be "speed >= XFER_UDMA_5". My ICH6 system reported XFER_UDMA_6,
>
>
> Jeff, does ICH6 support UDMA6?
> ICH5 doesn't but ata_piix.c allows it.
Good question. AFAICS ICH5 and ICH6 are the same such that:
* PATA does not support UDMA6
* internal base clock is 133Mhz for UDMA5
* SATA PCI device exports, but completely ignores, PATA timing registers
So for ata_piix at least, I would prefer to do
* patch1: your patch, based on Go's patch
* patch2: only configure timing registers for PATA port (PATA is only
used when an #ifdef is defined)
* patch3: do not limit SATA to udma5
Jeff
next prev parent reply other threads:[~2004-05-19 22:32 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-05-18 11:19 piix dma setup code Go Taniguchi
2004-05-19 1:34 ` Jeff Garzik
2004-05-19 16:51 ` Bartlomiej Zolnierkiewicz
2004-05-19 22:31 ` Jeff Garzik [this message]
2004-05-19 22:59 ` Bartlomiej Zolnierkiewicz
2004-05-19 23:19 ` Jeff Garzik
2004-05-20 0:10 ` Bartlomiej Zolnierkiewicz
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