Yamon compiling and linking

Yamon compiling and linking

[Roman Mashak]

Hello!

I solved the problem with Yamon compiling I asked recently, but still have
technical related questions about Yamon linking & code allocating in memory.

Here it is.

When I compile little-endian only image, as far as I understood, I got image
without RESET code at the beginning, so according to the memory map and link
script (link_el.xn) - starting entry point is __RESET_HANDLER_END (locating
in init.S) and its address is 0x9fc10000.
So, I don't quite understand, how will be going after CPU reset? As
documentation's saying "following a reset, hardware fetches instructions
starting at the reset exception vector 0xBFC00000". But what is waiting at
this address, because reset code (reset.S) is not compiled and is not
linked?

Could you please make it clear to me?

Thanks in advance!

With best regards, Roman Mashak.  E-mail: mrv@tusur.ru

Yamon compiling and linking

[Roman Mashak]

Hello!

I solved the problem with Yamon compiling I asked recently, but still have
technical related questions about Yamon linking & code allocating in memory.

Here it is.

When I compile little-endian only image, as far as I understood, I got image
without RESET code at the beginning, so according to the memory map and link
script (link_el.xn) - starting entry point is __RESET_HANDLER_END (locating
in init.S) and its address is 0x9fc10000.
So, I don't quite understand, how will be going after CPU reset? As
documentation's saying "following a reset, hardware fetches instructions
starting at the reset exception vector 0xBFC00000". But what is waiting at
this address, because reset code (reset.S) is not compiled and is not
linked?

Could you please make it clear to me?

Thanks in advance!

With best regards, Roman Mashak.  E-mail: mrv@tusur.ru

Re: Yamon compiling and linking

[Chris Dearman]

Roman Mashak wrote:
> When I compile little-endian only image, as far as I understood, I got image
> without RESET code at the beginning, so according to the memory map and link
> script (link_el.xn) - starting entry point is __RESET_HANDLER_END (locating
> in init.S) and its address is 0x9fc10000.
> So, I don't quite understand, how will be going after CPU reset? As
> documentation's saying "following a reset, hardware fetches instructions
> starting at the reset exception vector 0xBFC00000". But what is waiting at
> this address, because reset code (reset.S) is not compiled and is not
> linked?

   I think you are using modified YAMON sources... I can tell you how 
the build process works for the distributed version of YAMON:

   Invoking make in the  yamon/bin directory build two YAMON images (one 
big-endian & one little-endian) in the EB & EL subdirectories.  In 
addition some endianess independent reset code (reset.o) is built in 
yamon/bin. These three images are combined together to make a single 
yamon-02.xx.rec image that can run in either endianess.

   If you're only interested in running little-endian you should be able 
to simply combine the reset-02.xx.rec and EL/yamon-02.xx_el.rec images.

	Chris

-- 
Chris Dearman          The Fruit Farm, Ely Road    voice +44 1223 706206
MIPS Technologies (UK) Chittering, Cambs, CB5 9PH  fax   +44 1223 706250

Re: Yamon compiling and linking

[Roman Mashak]

Hello, Chris!
You wrote to "Roman Mashak" <mrv@tusur.ru> on Tue, 17 Aug 2004 11:45:51
+0100:

 CD>    I think you are using modified YAMON sources... I can tell you how
 CD> the build process works for the distributed version of YAMON:

   Sorry, i didn't mention that  I'm using YAMON source code supplied with
AMD Alchemy  AU1550 dev. board. But I've already sent my questions to AMD
support, and didn't get reply for 3 days, that's why I asked here.
 CD>    Invoking make in the  yamon/bin directory build two YAMON images
 CD> (one big-endian & one little-endian) in the EB & EL subdirectories.  In
    Yes, absolutely correct
 CD> addition some endianess independent reset code (reset.o) is built in
 CD> yamon/bin. These three images are combined together to make a single
 CD> yamon-02.xx.rec image that can run in either endianess.
    In my case - NOT. So, if I invoke 'make srec_el' to build little-endian
only image I get only LE image located in the bin/EL directory and nothing
in the upper directory.
 CD>    If you're only interested in running little-endian you should be
 CD> able to simply combine the reset-02.xx.rec and EL/yamon-02.xx_el.rec
 CD> images.
    So, I have to compile reset code seperately and combine it with LE
according to your device.

With best regards, Roman Mashak.  E-mail: mrv@tusur.ru

Re: Yamon compiling and linking

[Roman Mashak]

Hello, Chris!
You wrote to "Roman Mashak" <mrv@tusur.ru> on Tue, 17 Aug 2004 11:45:51
+0100:

 CD>    I think you are using modified YAMON sources... I can tell you how
 CD> the build process works for the distributed version of YAMON:

   Sorry, i didn't mention that  I'm using YAMON source code supplied with
AMD Alchemy  AU1550 dev. board. But I've already sent my questions to AMD
support, and didn't get reply for 3 days, that's why I asked here.
 CD>    Invoking make in the  yamon/bin directory build two YAMON images
 CD> (one big-endian & one little-endian) in the EB & EL subdirectories.  In
    Yes, absolutely correct
 CD> addition some endianess independent reset code (reset.o) is built in
 CD> yamon/bin. These three images are combined together to make a single
 CD> yamon-02.xx.rec image that can run in either endianess.
    In my case - NOT. So, if I invoke 'make srec_el' to build little-endian
only image I get only LE image located in the bin/EL directory and nothing
in the upper directory.
 CD>    If you're only interested in running little-endian you should be
 CD> able to simply combine the reset-02.xx.rec and EL/yamon-02.xx_el.rec
 CD> images.
    So, I have to compile reset code seperately and combine it with LE
according to your device.

With best regards, Roman Mashak.  E-mail: mrv@tusur.ru

Re: Yamon compiling and linking

[Saugata.Chatterjee]

Reset code (reset.S) IS compiled and linked (at bfc00000 like it should
be), and pretty early on in there YAMON detects endianness and jumps to the
location of the appropriate endian image. Dump the output of make to a log
file and look for the compilation of reset.S.

 Hope that helps,
-Saugata.




                                                                                                                                           
                      "Roman Mashak"                                                                                                       
                      <mrv@tusur.ru>               To:       <linux-mips@linux-mips.org>                                                   
                      Sent by:                     cc:                                                                                     
                      linux-mips-bounce@lin        Subject:  Yamon compiling and linking                                                   
                      ux-mips.org                                                                                                          
                                                                                                                                           
                                                                                                                                           
                      08/16/2004 06:57 PM                                                                                                  
                                                                                                                                           
                                                                                                                                           




Hello!

I solved the problem with Yamon compiling I asked recently, but still have
technical related questions about Yamon linking & code allocating in
memory.

Here it is.

When I compile little-endian only image, as far as I understood, I got
image
without RESET code at the beginning, so according to the memory map and
link
script (link_el.xn) - starting entry point is __RESET_HANDLER_END (locating
in init.S) and its address is 0x9fc10000.
So, I don't quite understand, how will be going after CPU reset? As
documentation's saying "following a reset, hardware fetches instructions
starting at the reset exception vector 0xBFC00000". But what is waiting at
this address, because reset code (reset.S) is not compiled and is not
linked?

Could you please make it clear to me?

Thanks in advance!

With best regards, Roman Mashak.  E-mail: mrv@tusur.ru

Re: Yamon compiling and linking

[Roman Mashak]

Hello, Saugata.Chatterjee@taec.toshiba.com!
You wrote to "Roman Mashak" <mrv@tusur.ru> on Tue, 17 Aug 2004
09:58:57 -0700:

SC> Reset code (reset.S) IS compiled and linked (at bfc00000 like it should
SC> be), and pretty early on in there YAMON detects endianness and jumps to
the
SC> location of the appropriate endian image. Dump the output of make to a
log
SC> file and look for the compilation of reset.S.

I have already investigated the 'makefile' and 'make' dump - and I've found
that reset code is compiled only in one case - when I compile both LE and BE
images.

Yes, I'm using AMD modified code and perhaps this is the reason, but their
support didn't answer yet.

Anyway - thank you for spending time for me.

With best regards, Roman Mashak.  E-mail: mrv@tusur.ru

Re: Yamon compiling and linking

[Roman Mashak]

Hello, Saugata.Chatterjee@taec.toshiba.com!
You wrote to "Roman Mashak" <mrv@tusur.ru> on Tue, 17 Aug 2004
09:58:57 -0700:

SC> Reset code (reset.S) IS compiled and linked (at bfc00000 like it should
SC> be), and pretty early on in there YAMON detects endianness and jumps to
the
SC> location of the appropriate endian image. Dump the output of make to a
log
SC> file and look for the compilation of reset.S.

I have already investigated the 'makefile' and 'make' dump - and I've found
that reset code is compiled only in one case - when I compile both LE and BE
images.

Yes, I'm using AMD modified code and perhaps this is the reason, but their
support didn't answer yet.

Anyway - thank you for spending time for me.

With best regards, Roman Mashak.  E-mail: mrv@tusur.ru