Which board is similar to mine, and how do I build a custom config?

Which board is similar to mine, and how do I build a custom config?

[Peter Asemann]

Well... as you know I need to get that custom board running...

I read the U-BOOT readme and try to write my own config now.
Until now I just copied everything from esteem192e as it seemed most 
similar to my hardware to me, and renamed everything to "esm" which is 
the "codename" of the hardware.

Anyway, I'm not sure if there isn't a board that is more similar to mine 
which I missed, that's why I'm asking you:

The board will have an MPC875 at 133MHz speed.
It'll have an ethernet LXT970A PHY chip and an ISP1301 USB PHY chip for
net/usb, plus a three-pin serial interface connected directly to the CPU.

The RAM will consist of 2x K4S561632E SDRAM chips (2*32MB). The 2 chips 
each take 16bits from the 32bit address bus, chip1 0-15, chip2 16-31. 
For addressing the adress lines A17-A29 connect to both chips' inputs 
A0-A12, address lines A6 and A7 connect to the chips' inputs BA0 and BA1.

The flash will consist of 4x AM29LV160D chips, each getting 8 bits of
the 32bit data bus, all being connected to the 21bit wide adress bus. 
Address bus lines A1 to A20 connect to the chips' inputs A0-A19, the 
chips' inputs called D15/A1 are connected to address bus line A0.

There will be more hardware available on the board, but I won't bother 
with that as it's not important for the task of getting that PowerPC 
subsystem running, I suppose.

I could send you schematic diagrams of the layout as graphics if these 
explanations are not explanatory enough.

The README says of u-boot says for a custom config I'll need a 
u-boot.lds, a flash.c, a board.c and some more things. Do I need to 
change anything about the u-boot.lds, the flash.c or the board.c - I 
hope a custom .../include/configs/ESM.h will suffice?

Enough questions for today.

Peter Asemann

Re: Which board is similar to mine, and how do I build a custom config?

[Wolfgang Denk]

In message <41935E32.3090202@web.de> you wrote:
> Well... as you know I need to get that custom board running...
> 
> I read the U-BOOT readme and try to write my own config now.

Did you? So why don't you DO what you've been told there?  Especially
in the "Where to get help" section?

Your question is completely off topic on _this_ mailing list.

Best regards,

Wolfgang Denk

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about the Open Systems Foundation

PowerPC MMU questions

[Jeff Domogala]

Folks,

I am dealing with a PowerPC 7455.  Here is my understanding regarding the
MMU translation order:  If the address is covered in a BAT, that BAT
translation is in effect.  If there is no BAT entry, then the page tables
are used to translate the address.  If there is no page table entry, an
exception is thrown and the exception handler for the miss needs to add a
new PTE.  So, correct me if I'm wrong in my translation.

Now, The system starts up with BAT entries to get the system off the ground.
I have equivalent BAT entries for the instruction and data sides.  I also
have the L1 I and D caches on as well as the L2 cache (I and D mode).  The
reason for using the BATs is to create non-cached I/O regions until the MMU
PTEs are populated.  Once the MMU PTEs are setup, the caches are flsuhed and
disabled, the MMU is disabled, the BATS disabled, the MMU re-enabled and the
caches re-enabled.  So here are my questions:

1. Is it ok to have the same I and D BAT entries?
2. Is it ok to setup the initial MMU PTEs with the BATs enabled or should
the caches be disabled and MMU disabled during the PTE setup?
3. Is there some other esource out there (mailing list or otherwise) that I
should be addressing these questions to?

Thanks,

Jeff Domogala

Re: PowerPC MMU questions

[Kumar Gala]

On Nov 11, 2004, at 9:36 PM, Jeff Domogala wrote:

> Folks,
>
> I am dealing with a PowerPC 7455.=A0 Here is my understanding =
regarding=20
> the
>  MMU translation order:=A0 If the address is covered in a BAT, that =
BAT
> translation is in effect.=A0 If there is no BAT entry, then the page=20=

> tables
>  are used to translate the address.=A0 If there is no page table =
entry,=20
> an
>  exception is thrown and the exception handler for the miss needs to=20=

> add a
>  new PTE.=A0 So, correct me if I'm wrong in my translation.
>
> Now, The system starts up with BAT entries to get the system off the=20=

> ground.
>  I have equivalent BAT entries for the instruction and data sides.=A0 =
I=20
> also
>  have the L1 I and D caches on as well as the L2 cache (I and D=20
> mode).=A0 The
>  reason for using the BATs is to create non-cached I/O regions until=20=

> the MMU
>  PTEs are populated.=A0 Once the MMU PTEs are setup, the caches are=20
> flsuhed and
>  disabled, the MMU is disabled, the BATS disabled, the MMU re-enabled=20=

> and the
>  caches re-enabled.=A0 So here are my questions:
>
> 1. Is it ok to have the same I and D BAT entries?

Yes, the I-BAT will be used for translations on instruction fetches,=20
the D-BAT will be used on data accesses (ld/st instructions).

>  2. Is it ok to setup the initial MMU PTEs with the BATs enabled or=20
> should
>  the caches be disabled and MMU disabled during the PTE setup?

There should be no harm setting up MMU PTEs with BATs enabled, as you=20
said the BATs will take preference over the PTEs

>  3. Is there some other esource out there (mailing list or otherwise)=20=

> that I
>  should be addressing these questions to?

This is as good as any, assuming your using linux :)  Also, the=20
Freescale website has a number of App Notes on the various PPC MMUs and=20=

an email support address risc10@freescale.com

- kumar