From: Andrei Konovalov <akonovalov@ru.mvista.com>
To: mporter@kernel.crashing.org
Cc: linux-kernel@vger.kernel.org, linuxppc-embedded@ozlabs.org
Subject: [PATCH][PPC32] Move irq_desc[].status, IRQ_LEVEL bit setup to xilinx_pic.c
Date: Mon, 14 Feb 2005 18:47:13 +0300 [thread overview]
Message-ID: <4210C801.2000204@ru.mvista.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 337 bytes --]
This patch applies to the kernel 2.6.11-rc3.
It moves the code that informs the kernel if the particular interrupt is edge triggered
or level sensitive from the board specific file to a "CONFIG_VIRTEX_II_PRO-specific" file.
Using old IRQ numbering in that code is also fixed.
Signed-off-by: Andrei Konovalov <akonovalov@ru.mvista.com>
[-- Attachment #2: xilinx_pic.diff --]
[-- Type: text/plain, Size: 1764 bytes --]
diff -uprN linux-2.5.base/arch/ppc/platforms/4xx/xilinx_ml300.c linux-2.5.cur/arch/ppc/platforms/4xx/xilinx_ml300.c
--- linux-2.5.base/arch/ppc/platforms/4xx/xilinx_ml300.c 2005-02-11 17:19:08.000000000 +0300
+++ linux-2.5.cur/arch/ppc/platforms/4xx/xilinx_ml300.c 2005-02-14 18:37:26.000000000 +0300
@@ -122,25 +122,7 @@ ml300_setup_arch(void)
void __init
ml300_init_irq(void)
{
- unsigned int i;
-
ppc4xx_init_IRQ();
-
- /*
- * For PowerPC 405 cores the default value for NR_IRQS is 32.
- * See include/asm-ppc/irq.h for details.
- * This is just fine for ML300.
- */
-#if (NR_IRQS != 32)
-#error NR_IRQS must be 32 for ML300
-#endif
-
- for (i = 0; i < NR_IRQS; i++) {
- if (XPAR_INTC_0_KIND_OF_INTR & (0x80000000 >> i))
- irq_desc[i].status &= ~IRQ_LEVEL;
- else
- irq_desc[i].status |= IRQ_LEVEL;
- }
}
void __init
diff -uprN linux-2.5.base/arch/ppc/syslib/xilinx_pic.c linux-2.5.cur/arch/ppc/syslib/xilinx_pic.c
--- linux-2.5.base/arch/ppc/syslib/xilinx_pic.c 2005-02-11 17:20:49.000000000 +0300
+++ linux-2.5.cur/arch/ppc/syslib/xilinx_pic.c 2005-02-14 16:57:40.000000000 +0300
@@ -114,6 +114,14 @@ ppc4xx_pic_init(void)
{
int i;
+ /*
+ * NOTE: The assumption here is that NR_IRQS is 32 or less
+ * (NR_IRQS is 32 for PowerPC 405 cores by default).
+ */
+#if (NR_IRQS > 32)
+#error NR_IRQS > 32 not supported
+#endif
+
#if XPAR_XINTC_USE_DCR == 0
intc = ioremap(XPAR_INTC_0_BASEADDR, 32);
@@ -138,6 +146,12 @@ ppc4xx_pic_init(void)
ppc_md.get_irq = xilinx_pic_get_irq;
- for (i = 0; i < NR_IRQS; ++i)
+ for (i = 0; i < NR_IRQS; ++i) {
irq_desc[i].handler = &xilinx_intc;
+
+ if (XPAR_INTC_0_KIND_OF_INTR & (0x00000001 << i))
+ irq_desc[i].status &= ~IRQ_LEVEL;
+ else
+ irq_desc[i].status |= IRQ_LEVEL;
+ }
}
WARNING: multiple messages have this Message-ID (diff)
From: Andrei Konovalov <akonovalov@ru.mvista.com>
To: mporter@kernel.crashing.org
Cc: linuxppc-embedded@ozlabs.org, linux-kernel@vger.kernel.org
Subject: [PATCH][PPC32] Move irq_desc[].status, IRQ_LEVEL bit setup to xilinx_pic.c
Date: Mon, 14 Feb 2005 18:47:13 +0300 [thread overview]
Message-ID: <4210C801.2000204@ru.mvista.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 337 bytes --]
This patch applies to the kernel 2.6.11-rc3.
It moves the code that informs the kernel if the particular interrupt is edge triggered
or level sensitive from the board specific file to a "CONFIG_VIRTEX_II_PRO-specific" file.
Using old IRQ numbering in that code is also fixed.
Signed-off-by: Andrei Konovalov <akonovalov@ru.mvista.com>
[-- Attachment #2: xilinx_pic.diff --]
[-- Type: text/plain, Size: 1764 bytes --]
diff -uprN linux-2.5.base/arch/ppc/platforms/4xx/xilinx_ml300.c linux-2.5.cur/arch/ppc/platforms/4xx/xilinx_ml300.c
--- linux-2.5.base/arch/ppc/platforms/4xx/xilinx_ml300.c 2005-02-11 17:19:08.000000000 +0300
+++ linux-2.5.cur/arch/ppc/platforms/4xx/xilinx_ml300.c 2005-02-14 18:37:26.000000000 +0300
@@ -122,25 +122,7 @@ ml300_setup_arch(void)
void __init
ml300_init_irq(void)
{
- unsigned int i;
-
ppc4xx_init_IRQ();
-
- /*
- * For PowerPC 405 cores the default value for NR_IRQS is 32.
- * See include/asm-ppc/irq.h for details.
- * This is just fine for ML300.
- */
-#if (NR_IRQS != 32)
-#error NR_IRQS must be 32 for ML300
-#endif
-
- for (i = 0; i < NR_IRQS; i++) {
- if (XPAR_INTC_0_KIND_OF_INTR & (0x80000000 >> i))
- irq_desc[i].status &= ~IRQ_LEVEL;
- else
- irq_desc[i].status |= IRQ_LEVEL;
- }
}
void __init
diff -uprN linux-2.5.base/arch/ppc/syslib/xilinx_pic.c linux-2.5.cur/arch/ppc/syslib/xilinx_pic.c
--- linux-2.5.base/arch/ppc/syslib/xilinx_pic.c 2005-02-11 17:20:49.000000000 +0300
+++ linux-2.5.cur/arch/ppc/syslib/xilinx_pic.c 2005-02-14 16:57:40.000000000 +0300
@@ -114,6 +114,14 @@ ppc4xx_pic_init(void)
{
int i;
+ /*
+ * NOTE: The assumption here is that NR_IRQS is 32 or less
+ * (NR_IRQS is 32 for PowerPC 405 cores by default).
+ */
+#if (NR_IRQS > 32)
+#error NR_IRQS > 32 not supported
+#endif
+
#if XPAR_XINTC_USE_DCR == 0
intc = ioremap(XPAR_INTC_0_BASEADDR, 32);
@@ -138,6 +146,12 @@ ppc4xx_pic_init(void)
ppc_md.get_irq = xilinx_pic_get_irq;
- for (i = 0; i < NR_IRQS; ++i)
+ for (i = 0; i < NR_IRQS; ++i) {
irq_desc[i].handler = &xilinx_intc;
+
+ if (XPAR_INTC_0_KIND_OF_INTR & (0x00000001 << i))
+ irq_desc[i].status &= ~IRQ_LEVEL;
+ else
+ irq_desc[i].status |= IRQ_LEVEL;
+ }
}
next reply other threads:[~2005-02-14 15:37 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-02-14 15:47 Andrei Konovalov [this message]
2005-02-14 15:47 ` [PATCH][PPC32] Move irq_desc[].status, IRQ_LEVEL bit setup to xilinx_pic.c Andrei Konovalov
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