* [PATCH] target/riscv/csr.c: Turn off mstatus.vs when misa.v is turned off
@ 2025-01-14 9:20 Evgenii Prokopiev
2025-01-14 13:02 ` Daniel Henrique Barboza
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Evgenii Prokopiev @ 2025-01-14 9:20 UTC (permalink / raw)
To: palmer
Cc: alistair.francis, bmeng.cn, liwei1518, dbarboza, zhiwei_liu,
qemu-riscv, qemu-devel, Evgenii Prokopiev
A behavior of misa.v must be similar as misa.f.
So when this bit's field is turned off, mstatus.vs must be turned off
too. It follows from the privileged manual of RISC-V, paragraph 3.1.1.
"Machine ISA (misa) Register".
Signed-off-by: Evgenii Prokopiev <evgenii.prokopiev@syntacore.com>
---
target/riscv/csr.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index eab8e50012..fca2b1b40f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1537,6 +1537,10 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
env->mstatus &= ~MSTATUS_FS;
}
+ if (!(env->misa_ext & RVV)) {
+ env->mstatus &= ~MSTATUS_VS;
+ }
+
/* flush translation cache */
tb_flush(env_cpu(env));
env->xl = riscv_cpu_mxl(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv/csr.c: Turn off mstatus.vs when misa.v is turned off
2025-01-14 9:20 [PATCH] target/riscv/csr.c: Turn off mstatus.vs when misa.v is turned off Evgenii Prokopiev
@ 2025-01-14 13:02 ` Daniel Henrique Barboza
2025-01-29 1:24 ` Alistair Francis
2025-01-29 1:28 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Daniel Henrique Barboza @ 2025-01-14 13:02 UTC (permalink / raw)
To: Evgenii Prokopiev, palmer
Cc: alistair.francis, bmeng.cn, liwei1518, zhiwei_liu, qemu-riscv,
qemu-devel
On 1/14/25 6:20 AM, Evgenii Prokopiev wrote:
> A behavior of misa.v must be similar as misa.f.
> So when this bit's field is turned off, mstatus.vs must be turned off
> too. It follows from the privileged manual of RISC-V, paragraph 3.1.1.
> "Machine ISA (misa) Register".
>
> Signed-off-by: Evgenii Prokopiev <evgenii.prokopiev@syntacore.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/csr.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index eab8e50012..fca2b1b40f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1537,6 +1537,10 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
> env->mstatus &= ~MSTATUS_FS;
> }
>
> + if (!(env->misa_ext & RVV)) {
> + env->mstatus &= ~MSTATUS_VS;
> + }
> +
> /* flush translation cache */
> tb_flush(env_cpu(env));
> env->xl = riscv_cpu_mxl(env);
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv/csr.c: Turn off mstatus.vs when misa.v is turned off
2025-01-14 9:20 [PATCH] target/riscv/csr.c: Turn off mstatus.vs when misa.v is turned off Evgenii Prokopiev
2025-01-14 13:02 ` Daniel Henrique Barboza
@ 2025-01-29 1:24 ` Alistair Francis
2025-01-29 1:28 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2025-01-29 1:24 UTC (permalink / raw)
To: Evgenii Prokopiev
Cc: palmer, alistair.francis, bmeng.cn, liwei1518, dbarboza,
zhiwei_liu, qemu-riscv, qemu-devel
On Tue, Jan 14, 2025 at 7:33 PM Evgenii Prokopiev
<evgenii.prokopiev@syntacore.com> wrote:
>
> A behavior of misa.v must be similar as misa.f.
> So when this bit's field is turned off, mstatus.vs must be turned off
> too. It follows from the privileged manual of RISC-V, paragraph 3.1.1.
> "Machine ISA (misa) Register".
>
> Signed-off-by: Evgenii Prokopiev <evgenii.prokopiev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index eab8e50012..fca2b1b40f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1537,6 +1537,10 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
> env->mstatus &= ~MSTATUS_FS;
> }
>
> + if (!(env->misa_ext & RVV)) {
> + env->mstatus &= ~MSTATUS_VS;
> + }
> +
> /* flush translation cache */
> tb_flush(env_cpu(env));
> env->xl = riscv_cpu_mxl(env);
> --
> 2.34.1
>
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv/csr.c: Turn off mstatus.vs when misa.v is turned off
2025-01-14 9:20 [PATCH] target/riscv/csr.c: Turn off mstatus.vs when misa.v is turned off Evgenii Prokopiev
2025-01-14 13:02 ` Daniel Henrique Barboza
2025-01-29 1:24 ` Alistair Francis
@ 2025-01-29 1:28 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2025-01-29 1:28 UTC (permalink / raw)
To: Evgenii Prokopiev
Cc: palmer, alistair.francis, bmeng.cn, liwei1518, dbarboza,
zhiwei_liu, qemu-riscv, qemu-devel
On Tue, Jan 14, 2025 at 7:33 PM Evgenii Prokopiev
<evgenii.prokopiev@syntacore.com> wrote:
>
> A behavior of misa.v must be similar as misa.f.
> So when this bit's field is turned off, mstatus.vs must be turned off
> too. It follows from the privileged manual of RISC-V, paragraph 3.1.1.
> "Machine ISA (misa) Register".
>
> Signed-off-by: Evgenii Prokopiev <evgenii.prokopiev@syntacore.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/csr.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index eab8e50012..fca2b1b40f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1537,6 +1537,10 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
> env->mstatus &= ~MSTATUS_FS;
> }
>
> + if (!(env->misa_ext & RVV)) {
> + env->mstatus &= ~MSTATUS_VS;
> + }
> +
> /* flush translation cache */
> tb_flush(env_cpu(env));
> env->xl = riscv_cpu_mxl(env);
> --
> 2.34.1
>
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2025-01-29 1:28 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2025-01-14 9:20 [PATCH] target/riscv/csr.c: Turn off mstatus.vs when misa.v is turned off Evgenii Prokopiev
2025-01-14 13:02 ` Daniel Henrique Barboza
2025-01-29 1:24 ` Alistair Francis
2025-01-29 1:28 ` Alistair Francis
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