From: Philip Prindeville <philipp_subx@redfish-solutions.com>
To: alsa-devel@alsa-project.org
Subject: 96KHz SPDIF output
Date: Thu, 22 Sep 2005 15:50:23 -0600 [thread overview]
Message-ID: <4333271F.1080008@redfish-solutions.com> (raw)
I was reading the datasheet on the VT1617A, that bit 3 (i.e. 0x0008) of
register 0x76 (miscellaneous register) controls the SPDIF_96 mode...
In this mode, the odd samples (N+1) go to SDATA_OUT1 (instead of
SDATA_OUT)... which is supported if bit 1 (0x0002) is set when this
register is read back (EN_DRA).
And was wondering if it was fairly simple/straightforward to add
support for this...
-Philip
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next reply other threads:[~2005-09-22 21:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-09-22 21:50 Philip Prindeville [this message]
2005-09-23 6:53 ` 96KHz SPDIF output Clemens Ladisch
2005-09-23 17:17 ` Philip Prindeville
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