* 96KHz SPDIF output
@ 2005-09-22 21:50 Philip Prindeville
2005-09-23 6:53 ` Clemens Ladisch
0 siblings, 1 reply; 3+ messages in thread
From: Philip Prindeville @ 2005-09-22 21:50 UTC (permalink / raw)
To: alsa-devel
I was reading the datasheet on the VT1617A, that bit 3 (i.e. 0x0008) of
register 0x76 (miscellaneous register) controls the SPDIF_96 mode...
In this mode, the odd samples (N+1) go to SDATA_OUT1 (instead of
SDATA_OUT)... which is supported if bit 1 (0x0002) is set when this
register is read back (EN_DRA).
And was wondering if it was fairly simple/straightforward to add
support for this...
-Philip
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: 96KHz SPDIF output
2005-09-22 21:50 96KHz SPDIF output Philip Prindeville
@ 2005-09-23 6:53 ` Clemens Ladisch
2005-09-23 17:17 ` Philip Prindeville
0 siblings, 1 reply; 3+ messages in thread
From: Clemens Ladisch @ 2005-09-23 6:53 UTC (permalink / raw)
To: Philip Prindeville; +Cc: alsa-devel
Philip Prindeville wrote:
> I was reading the datasheet on the VT1617A, that bit 3 (i.e. 0x0008) of
> register 0x76 (miscellaneous register) controls the SPDIF_96 mode...
>
> In this mode, the odd samples (N+1) go to SDATA_OUT1 (instead of
> SDATA_OUT)... which is supported if bit 1 (0x0002) is set when this
> register is read back (EN_DRA).
>
> And was wondering if it was fairly simple/straightforward to add
> support for this...
Good question. Thank you for volunteering to find out! ;-)
SCNR
Clemens
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: 96KHz SPDIF output
2005-09-23 6:53 ` Clemens Ladisch
@ 2005-09-23 17:17 ` Philip Prindeville
0 siblings, 0 replies; 3+ messages in thread
From: Philip Prindeville @ 2005-09-23 17:17 UTC (permalink / raw)
To: Clemens Ladisch; +Cc: alsa-devel
Clemens Ladisch wrote:
>Philip Prindeville wrote:
>
>
>>I was reading the datasheet on the VT1617A, that bit 3 (i.e. 0x0008) of
>>register 0x76 (miscellaneous register) controls the SPDIF_96 mode...
>>
>>In this mode, the odd samples (N+1) go to SDATA_OUT1 (instead of
>>SDATA_OUT)... which is supported if bit 1 (0x0002) is set when this
>>register is read back (EN_DRA).
>>
>>And was wondering if it was fairly simple/straightforward to add
>>support for this...
>>
>>
>
>Good question. Thank you for volunteering to find out! ;-)
>
>
>SCNR
>Clemens
>
>
>
Unfortunately, none of my hardware supports it, or I might.
-Philip
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^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2005-09-23 17:17 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2005-09-22 21:50 96KHz SPDIF output Philip Prindeville
2005-09-23 6:53 ` Clemens Ladisch
2005-09-23 17:17 ` Philip Prindeville
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