[PATCH 0/2] Add driver support for ESWIN eic7700 SoC reset controller

[PATCH 0/2] Add driver support for ESWIN eic7700 SoC reset controller

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

	Add support for the reset functionality in the Linux kernel.
	The driver provides basic functionality to manage and control
	the reset signals for the eic7700 series chips, which are part of
	the Eswin SoC family.

	The driver integrates with the Linux reset subsystem, allowing kernel
	code to trigger resets on the hardware and ensuring proper handling of
	reset events.

	Features:

	 Implement support for the ESWIN eic7700 SoC reset controller.
	 Provide API to manage reset signals for the eic7700 series SoC.
	 Integrate with the Linux reset subsystem for consistency and
	 scalability.

	Supported chips:
	 ESWIN eic7700 series SoC.

	Test:
	 The tests tested on the Sifive HiFive Premier P550 (which uses the EIC7700 SoC),
	 including system boot, networking, EMMC, display, and other peripherals.
	 The drivers of these modules all use the reset module,
	 so the verifies that this clock driver patch is working properly.

Xuyang Dong (2):
  dt-bindings: reset: eswin: Documentation for eic7700 SoC
  reset: eswin: Add eic7700 reset driver

 .../bindings/reset/eswin,eic7700-reset.yaml   |  57 +++
 drivers/reset/Kconfig                         |   9 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-eic7700.c                 | 249 ++++++++++
 .../dt-bindings/reset/eswin,eic7700-reset.h   | 460 ++++++++++++++++++
 5 files changed, 776 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
 create mode 100644 drivers/reset/reset-eic7700.c
 create mode 100644 include/dt-bindings/reset/eswin,eic7700-reset.h

--
2.17.1

[PATCH 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

Add device tree binding documentation and header file for the ESWIN
eic7700 reset controller module.

Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 .../bindings/reset/eswin,eic7700-reset.yaml   |  47 +++
 .../dt-bindings/reset/eswin,eic7700-reset.h   | 460 ++++++++++++++++++
 2 files changed, 517 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
 create mode 100644 include/dt-bindings/reset/eswin,eic7700-reset.h

diff --git a/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml b/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
new file mode 100644
index 000000000000..1a3c6d230efe
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/eswin,eic7700-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ESWIN EIC7700 SoC reset controller
+
+maintainers:
+  - Yifeng Huang <huangyifeng@eswincomputing.com>
+  - Xuyang Dong <dongxuyang@eswincomputing.com>
+
+description: |
+  The reset controller registers are part of the syscrg block on
+  the EIC7700 SoC.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: eswin,eic7700-reset
+
+  '#reset-cells':
+    description: |
+      Specifies the number of cells needed to encode a reset source.
+      Cell #1 : module id of the reset consumer
+      Cell #2 : bit position of the reset in each reset consumer module
+    const: 2
+
+required:
+  - compatible
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/eswin,eic7700-reset.h>
+
+    sys_crg: sys-crg@51828000 {
+        compatible = "syscon", "simple-mfd";
+        reg = <0x000000 0x51828000 0x000000 0x80000>;
+        reset: reset-controller {
+            compatible = "eswin,eic7700-reset";
+            #reset-cells = <2>;
+        };
+    };
diff --git a/include/dt-bindings/reset/eswin,eic7700-reset.h b/include/dt-bindings/reset/eswin,eic7700-reset.h
new file mode 100644
index 000000000000..fcf004620db9
--- /dev/null
+++ b/include/dt-bindings/reset/eswin,eic7700-reset.h
@@ -0,0 +1,460 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 reset controller.
+ *
+ * Authors:
+ *	Yifeng Huang <huangyifeng@eswincomputing.com>
+ *	Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef __DT_ESWIN_EIC7700_RESET_H__
+#define __DT_ESWIN_EIC7700_RESET_H__
+
+#define SNOC_RST_CTRL 0X00
+#define GPU_RST_CTRL 0X01
+#define DSP_RST_CTRL 0X02
+#define D2D_RST_CTRL 0X03
+#define DDR_RST_CTRL 0X04
+#define TCU_RST_CTRL 0X05
+#define NPU_RST_CTRL 0X06
+#define HSPDMA_RST_CTRL 0X07
+#define PCIE_RST_CTRL 0X08
+#define I2C_RST_CTRL 0X09
+#define FAN_RST_CTRL 0X0A
+#define PVT_RST_CTRL 0X0B
+#define MBOX_RST_CTRL 0X0C
+#define UART_RST_CTRL 0X0D
+#define GPIO_RST_CTRL 0X0E
+#define TIMER_RST_CTRL 0X0F
+#define SSI_RST_CTRL 0X10
+#define WDT_RST_CTRL 0X11
+#define LSP_CFGRST_CTRL 0X12
+#define U84_RST_CTRL 0X13
+#define SCPU_RST_CTRL 0X14
+#define LPCPU_RST_CTRL 0X15
+#define VC_RST_CTRL 0X16
+#define JD_RST_CTRL 0X17
+#define JE_RST_CTRL 0X18
+#define VD_RST_CTRL 0X19
+#define VE_RST_CTRL 0X1A
+#define G2D_RST_CTRL 0X1B
+#define VI_RST_CTRL 0X1C
+#define DVP_RST_CTRL 0X1D
+#define ISP0_RST_CTRL 0X1E
+#define ISP1_RST_CTRL 0X1F
+#define SHUTTER_RST_CTRL 0X20
+#define VO_PHYRST_CTRL 0X21
+#define VO_I2SRST_CTRL 0X22
+#define VO_RST_CTRL 0X23
+#define BOOTSPI_RST_CTRL 0X24
+#define I2C1_RST_CTRL 0X25
+#define I2C0_RST_CTRL 0X26
+#define DMA1_RST_CTRL 0X27
+#define FPRT_RST_CTRL 0X28
+#define HBLOCK_RST_CTRL 0X29
+#define SECSR_RST_CTRL 0X2A
+#define OTP_RST_CTRL 0X2B
+#define PKA_RST_CTRL 0X2C
+#define SPACC_RST_CTRL 0X2D
+#define TRNG_RST_CTRL 0X2E
+#define RESERVED 0X2F
+#define TIMER0_RST_CTRL 0X30
+#define TIMER1_RST_CTRL 0X31
+#define TIMER2_RST_CTRL 0X32
+#define TIMER3_RST_CTRL 0X33
+#define RTC_RST_CTRL 0X34
+#define MNOC_RST_CTRL 0X35
+#define RNOC_RST_CTRL 0X36
+#define CNOC_RST_CTRL 0X37
+#define LNOC_RST_CTRL 0X38
+
+/*
+ * CONSUMER RESET CONTROL BIT
+ */
+/*SNOC*/
+#define SW_NOC_NSP_RSTN (1 << 0)
+#define SW_NOC_CFG_RSTN (1 << 1)
+#define SW_RNOC_NSP_RSTN (1 << 2)
+#define SW_SNOC_TCU_ARSTN (1 << 3)
+#define SW_SNOC_U84_ARSTN (1 << 4)
+#define SW_SNOC_PCIET_XSRSTN (1 << 5)
+#define SW_SNOC_PCIET_XMRSTN (1 << 6)
+#define SW_SNOC_PCIET_PRSTN (1 << 7)
+#define SW_SNOC_NPU_ARSTN (1 << 8)
+#define SW_SNOC_JTAG_ARSTN (1 << 9)
+#define SW_SNOC_DSPT_ARSTN (1 << 10)
+#define SW_SNOC_DDRC1_P2_ARSTN (1 << 11)
+#define SW_SNOC_DDRC1_P1_ARSTN (1 << 12)
+#define SW_SNOC_DDRC0_P2_ARSTN (1 << 13)
+#define SW_SNOC_DDRC0_P1_ARSTN (1 << 14)
+#define SW_SNOC_D2D_ARSTN (1 << 15)
+#define SW_SNOC_AON_ARSTN (1 << 16)
+
+/*GPU*/
+#define SW_GPU_AXI_RSTN (1 << 0)
+#define SW_GPU_CFG_RSTN (1 << 1)
+#define SW_GPU_GRAY_RSTN (1 << 2)
+#define SW_GPU_JONES_RSTN (1 << 3)
+#define SW_GPU_SPU_RSTN (1 << 4)
+
+/*DSP*/
+#define SW_DSP_AXI_RSTN (1 << 0)
+#define SW_DSP_CFG_RSTN (1 << 1)
+#define SW_DSP_DIV4_RSTN (1 << 2)
+#define SW_DSP_DIV_RSTN_0 (1 << 4)
+#define SW_DSP_DIV_RSTN_1 (1 << 5)
+#define SW_DSP_DIV_RSTN_2 (1 << 6)
+#define SW_DSP_DIV_RSTN_3 (1 << 7)
+
+/*D2D*/
+#define SW_D2D_AXI_RSTN (1 << 0)
+#define SW_D2D_CFG_RSTN (1 << 1)
+#define SW_D2D_PRST_N (1 << 2)
+#define SW_D2D_RAW_PCS_RST_N (1 << 4)
+#define SW_D2D_RX_RST_N (1 << 5)
+#define SW_D2D_TX_RST_N (1 << 6)
+#define SW_D2D_CORE_RST_N (1 << 7)
+
+/*TCU*/
+#define SW_TCU_AXI_RSTN (1 << 0)
+#define SW_TCU_CFG_RSTN (1 << 1)
+#define TBU_RSTN_0 (1 << 4)
+#define TBU_RSTN_1 (1 << 5)
+#define TBU_RSTN_2 (1 << 6)
+#define TBU_RSTN_3 (1 << 7)
+#define TBU_RSTN_4 (1 << 8)
+#define TBU_RSTN_5 (1 << 9)
+#define TBU_RSTN_6 (1 << 10)
+#define TBU_RSTN_7 (1 << 11)
+#define TBU_RSTN_8 (1 << 12)
+#define TBU_RSTN_9 (1 << 13)
+#define TBU_RSTN_10 (1 << 14)
+#define TBU_RSTN_11 (1 << 15)
+#define TBU_RSTN_12 (1 << 16)
+#define TBU_RSTN_13 (1 << 17)
+#define TBU_RSTN_14 (1 << 18)
+#define TBU_RSTN_15 (1 << 19)
+#define TBU_RSTN_16 (1 << 20)
+
+/*NPU*/
+#define SW_NPU_AXI_RSTN (1 << 0)
+#define SW_NPU_CFG_RSTN (1 << 1)
+#define SW_NPU_CORE_RSTN (1 << 2)
+#define SW_NPU_E31CORE_RSTN (1 << 3)
+#define SW_NPU_E31BUS_RSTN (1 << 4)
+#define SW_NPU_E31DBG_RSTN (1 << 5)
+#define SW_NPU_LLC_RSTN (1 << 6)
+
+/*HSP DMA*/
+#define SW_HSP_AXI_RSTN (1 << 0)
+#define SW_HSP_CFG_RSTN (1 << 1)
+#define SW_HSP_POR_RSTN (1 << 2)
+#define SW_MSHC0_PHY_RSTN (1 << 3)
+#define SW_MSHC1_PHY_RSTN (1 << 4)
+#define SW_MSHC2_PHY_RSTN (1 << 5)
+#define SW_MSHC0_TXRX_RSTN (1 << 6)
+#define SW_MSHC1_TXRX_RSTN (1 << 7)
+#define SW_MSHC2_TXRX_RSTN (1 << 8)
+#define SW_SATA_ASIC0_RSTN (1 << 9)
+#define SW_SATA_OOB_RSTN (1 << 10)
+#define SW_SATA_PMALIVE_RSTN (1 << 11)
+#define SW_SATA_RBC_RSTN (1 << 12)
+#define SW_DMA0_RST_N (1 << 13)
+#define SW_HSP_DMA0_RSTN (1 << 14)
+#define SW_USB0_VAUX_RSTN (1 << 15)
+#define SW_USB1_VAUX_RSTN (1 << 16)
+#define SW_HSP_SD1_PRSTN (1 << 17)
+#define SW_HSP_SD0_PRSTN (1 << 18)
+#define SW_HSP_EMMC_PRSTN (1 << 19)
+#define SW_HSP_DMA_PRSTN (1 << 20)
+#define SW_HSP_SD1_ARSTN (1 << 21)
+#define SW_HSP_SD0_ARSTN (1 << 22)
+#define SW_HSP_EMMC_ARSTN (1 << 23)
+#define SW_HSP_DMA_ARSTN (1 << 24)
+#define SW_HSP_ETH1_ARSTN (1 << 25)
+#define SW_HSP_ETH0_ARSTN (1 << 26)
+#define SW_HSP_SATA_ARSTN (1 << 27)
+
+/*PCIE*/
+#define SW_PCIE_CFG_RSTN (1 << 0)
+#define SW_PCIE_POWERUP_RSTN (1 << 1)
+#define SW_PCIE_PERST_N (1 << 2)
+
+/*I2C*/
+#define SW_I2C_RST_N_0 (1 << 0)
+#define SW_I2C_RST_N_1 (1 << 1)
+#define SW_I2C_RST_N_2 (1 << 2)
+#define SW_I2C_RST_N_3 (1 << 3)
+#define SW_I2C_RST_N_4 (1 << 4)
+#define SW_I2C_RST_N_5 (1 << 5)
+#define SW_I2C_RST_N_6 (1 << 6)
+#define SW_I2C_RST_N_7 (1 << 7)
+#define SW_I2C_RST_N_8 (1 << 8)
+#define SW_I2C_RST_N_9 (1 << 9)
+
+/*FAN*/
+#define SW_FAN_RST_N (1 << 0)
+
+/*PVT*/
+#define SW_PVT_RST_N_0 (1 << 0)
+#define SW_PVT_RST_N_1 (1 << 1)
+
+/*MBOX*/
+#define SW_MBOX_RST_N_0 (1 << 0)
+#define SW_MBOX_RST_N_1 (1 << 1)
+#define SW_MBOX_RST_N_2 (1 << 2)
+#define SW_MBOX_RST_N_3 (1 << 3)
+#define SW_MBOX_RST_N_4 (1 << 4)
+#define SW_MBOX_RST_N_5 (1 << 5)
+#define SW_MBOX_RST_N_6 (1 << 6)
+#define SW_MBOX_RST_N_7 (1 << 7)
+#define SW_MBOX_RST_N_8 (1 << 8)
+#define SW_MBOX_RST_N_9 (1 << 9)
+#define SW_MBOX_RST_N_10 (1 << 10)
+#define SW_MBOX_RST_N_11 (1 << 11)
+#define SW_MBOX_RST_N_12 (1 << 12)
+#define SW_MBOX_RST_N_13 (1 << 13)
+#define SW_MBOX_RST_N_14 (1 << 14)
+#define SW_MBOX_RST_N_15 (1 << 15)
+
+/*UART*/
+#define SW_UART_RST_N_0 (1 << 0)
+#define SW_UART_RST_N_1 (1 << 1)
+#define SW_UART_RST_N_2 (1 << 2)
+#define SW_UART_RST_N_3 (1 << 3)
+#define SW_UART_RST_N_4 (1 << 4)
+
+/*GPIO*/
+#define SW_GPIO_RST_N_0 (1 << 0)
+#define SW_GPIO_RST_N_1 (1 << 1)
+
+/*TIMER*/
+#define SW_TIMER_RST_N (1 << 0)
+
+/*SSI*/
+#define SW_SSI_RST_N_0 (1 << 0)
+#define SW_SSI_RST_N_1 (1 << 1)
+
+/*WDT*/
+#define SW_WDT_RST_N_0 (1 << 0)
+#define SW_WDT_RST_N_1 (1 << 1)
+#define SW_WDT_RST_N_2 (1 << 2)
+#define SW_WDT_RST_N_3 (1 << 3)
+
+/*LSP CFG*/
+#define SW_LSP_CFG_RSTN (1 << 0)
+
+/*U84 CFG*/
+#define SW_U84_CORE_RSTN_0 (1 << 0)
+#define SW_U84_CORE_RSTN_1 (1 << 1)
+#define SW_U84_CORE_RSTN_2 (1 << 2)
+#define SW_U84_CORE_RSTN_3 (1 << 3)
+#define SW_U84_BUS_RSTN (1 << 4)
+#define SW_U84_DBG_RSTN (1 << 5)
+#define SW_U84_TRACECOM_RSTN (1 << 6)
+#define SW_U84_TRACE_RSTN_0 (1 << 8)
+#define SW_U84_TRACE_RSTN_1 (1 << 9)
+#define SW_U84_TRACE_RSTN_2 (1 << 10)
+#define SW_U84_TRACE_RSTN_3 (1 << 11)
+
+/*SCPU*/
+#define SW_SCPU_CORE_RSTN (1 << 0)
+#define SW_SCPU_BUS_RSTN (1 << 1)
+#define SW_SCPU_DBG_RSTN (1 << 2)
+
+/*LPCPU*/
+#define SW_LPCPU_CORE_RSTN (1 << 0)
+#define SW_LPCPU_BUS_RSTN (1 << 1)
+#define SW_LPCPU_DBG_RSTN (1 << 2)
+
+/*VC*/
+#define SW_VC_CFG_RSTN (1 << 0)
+#define SW_VC_AXI_RSTN (1 << 1)
+#define SW_VC_MONCFG_RSTN (1 << 2)
+
+/*JD*/
+#define SW_JD_CFG_RSTN (1 << 0)
+#define SW_JD_AXI_RSTN (1 << 1)
+
+/*JE*/
+#define SW_JE_CFG_RSTN (1 << 0)
+#define SW_JE_AXI_RSTN (1 << 1)
+
+/*VD*/
+#define SW_VD_CFG_RSTN (1 << 0)
+#define SW_VD_AXI_RSTN (1 << 1)
+
+/*VE*/
+#define SW_VE_AXI_RSTN (1 << 0)
+#define SW_VE_CFG_RSTN (1 << 1)
+
+/*G2D*/
+#define SW_G2D_CORE_RSTN (1 << 0)
+#define SW_G2D_CFG_RSTN (1 << 1)
+#define SW_G2D_AXI_RSTN (1 << 2)
+
+/*VI*/
+#define SW_VI_AXI_RSTN (1 << 0)
+#define SW_VI_CFG_RSTN (1 << 1)
+#define SW_VI_DWE_RSTN (1 << 2)
+
+/*DVP*/
+#define SW_VI_DVP_RSTN (1 << 0)
+
+/*ISP0*/
+#define SW_VI_ISP0_RSTN (1 << 0)
+
+/*ISP1*/
+#define SW_VI_ISP1_RSTN (1 << 0)
+
+/*SHUTTR*/
+#define SW_VI_SHUTTER_RSTN_0 (1 << 0)
+#define SW_VI_SHUTTER_RSTN_1 (1 << 1)
+#define SW_VI_SHUTTER_RSTN_2 (1 << 2)
+#define SW_VI_SHUTTER_RSTN_3 (1 << 3)
+#define SW_VI_SHUTTER_RSTN_4 (1 << 4)
+#define SW_VI_SHUTTER_RSTN_5 (1 << 5)
+
+/*VO PHY*/
+#define SW_VO_MIPI_PRSTN (1 << 0)
+#define SW_VO_PRSTN (1 << 1)
+#define SW_VO_HDMI_PRSTN (1 << 3)
+#define SW_HDMI_PHYCTRL_RSTN (1 << 4)
+#define SW_VO_HDMI_RSTN (1 << 5)
+
+/*VO I2S*/
+#define SW_VO_I2S_RSTN (1 << 0)
+#define SW_VO_I2S_PRSTN (1 << 1)
+
+/*VO*/
+#define SW_VO_AXI_RSTN (1 << 0)
+#define SW_VO_CFG_RSTN (1 << 1)
+#define SW_VO_DC_RSTN (1 << 2)
+#define SW_VO_DC_PRSTN (1 << 3)
+
+/*BOOTSPI*/
+#define SW_BOOTSPI_HRSTN (1 << 0)
+#define SW_BOOTSPI_RSTN (1 << 1)
+
+/*I2C1*/
+#define SW_I2C1_PRSTN (1 << 0)
+
+/*I2C0*/
+#define SW_I2C0_PRSTN (1 << 0)
+
+/*DMA1*/
+#define SW_DMA1_ARSTN (1 << 0)
+#define SW_DMA1_HRSTN (1 << 1)
+
+/*FPRT*/
+#define SW_FP_PRT_HRSTN (1 << 0)
+
+/*HBLOCK*/
+#define SW_HBLOCK_HRSTN (1 << 0)
+
+/*SECSR*/
+#define SW_SECSR_HRSTN (1 << 0)
+
+/*OTP*/
+#define SW_OTP_PRSTN (1 << 0)
+
+/*PKA*/
+#define SW_PKA_HRSTN (1 << 0)
+
+/*SPACC*/
+#define SW_SPACC_RSTN (1 << 0)
+
+/*TRNG*/
+#define SW_TRNG_HRSTN (1 << 0)
+
+/*TIMER0*/
+#define SW_TIMER0_RSTN_0 (1 << 0)
+#define SW_TIMER0_RSTN_1 (1 << 1)
+#define SW_TIMER0_RSTN_2 (1 << 2)
+#define SW_TIMER0_RSTN_3 (1 << 3)
+#define SW_TIMER0_RSTN_4 (1 << 4)
+#define SW_TIMER0_RSTN_5 (1 << 5)
+#define SW_TIMER0_RSTN_6 (1 << 6)
+#define SW_TIMER0_RSTN_7 (1 << 7)
+#define SW_TIMER0_PRSTN (1 << 8)
+
+/*TIMER1*/
+#define SW_TIMER1_RSTN_0 (1 << 0)
+#define SW_TIMER1_RSTN_1 (1 << 1)
+#define SW_TIMER1_RSTN_2 (1 << 2)
+#define SW_TIMER1_RSTN_3 (1 << 3)
+#define SW_TIMER1_RSTN_4 (1 << 4)
+#define SW_TIMER1_RSTN_5 (1 << 5)
+#define SW_TIMER1_RSTN_6 (1 << 6)
+#define SW_TIMER1_RSTN_7 (1 << 7)
+#define SW_TIMER1_PRSTN (1 << 8)
+
+/*TIMER2*/
+#define SW_TIMER2_RSTN_0 (1 << 0)
+#define SW_TIMER2_RSTN_1 (1 << 1)
+#define SW_TIMER2_RSTN_2 (1 << 2)
+#define SW_TIMER2_RSTN_3 (1 << 3)
+#define SW_TIMER2_RSTN_4 (1 << 4)
+#define SW_TIMER2_RSTN_5 (1 << 5)
+#define SW_TIMER2_RSTN_6 (1 << 6)
+#define SW_TIMER2_RSTN_7 (1 << 7)
+#define SW_TIMER2_PRSTN (1 << 8)
+
+/*TIMER3*/
+#define SW_TIMER3_RSTN_0 (1 << 0)
+#define SW_TIMER3_RSTN_1 (1 << 1)
+#define SW_TIMER3_RSTN_2 (1 << 2)
+#define SW_TIMER3_RSTN_3 (1 << 3)
+#define SW_TIMER3_RSTN_4 (1 << 4)
+#define SW_TIMER3_RSTN_5 (1 << 5)
+#define SW_TIMER3_RSTN_6 (1 << 6)
+#define SW_TIMER3_RSTN_7 (1 << 7)
+#define SW_TIMER3_PRSTN (1 << 8)
+
+/*RTC*/
+#define SW_RTC_RSTN (1 << 0)
+
+/*MNOC*/
+#define SW_MNOC_SNOC_NSP_RSTN (1 << 0)
+#define SW_MNOC_VC_ARSTN (1 << 1)
+#define SW_MNOC_CFG_RSTN (1 << 2)
+#define SW_MNOC_HSP_ARSTN (1 << 3)
+#define SW_MNOC_GPU_ARSTN (1 << 4)
+#define SW_MNOC_DDRC1_P3_ARSTN (1 << 5)
+#define SW_MNOC_DDRC0_P3_ARSTN (1 << 6)
+
+/*RNOC*/
+#define SW_RNOC_VO_ARSTN (1 << 0)
+#define SW_RNOC_VI_ARSTN (1 << 1)
+#define SW_RNOC_SNOC_NSP_RSTN (1 << 2)
+#define SW_RNOC_CFG_RSTN (1 << 3)
+#define SW_MNOC_DDRC1_P4_ARSTN (1 << 4)
+#define SW_MNOC_DDRC0_P4_ARSTN (1 << 5)
+
+/*CNOC*/
+#define SW_CNOC_VO_CFG_RSTN (1 << 0)
+#define SW_CNOC_VI_CFG_RSTN (1 << 1)
+#define SW_CNOC_VC_CFG_RSTN (1 << 2)
+#define SW_CNOC_TCU_CFG_RSTN (1 << 3)
+#define SW_CNOC_PCIET_CFG_RSTN (1 << 4)
+#define SW_CNOC_NPU_CFG_RSTN (1 << 5)
+#define SW_CNOC_LSP_CFG_RSTN (1 << 6)
+#define SW_CNOC_HSP_CFG_RSTN (1 << 7)
+#define SW_CNOC_GPU_CFG_RSTN (1 << 8)
+#define SW_CNOC_DSPT_CFG_RSTN (1 << 9)
+#define SW_CNOC_DDRT1_CFG_RSTN (1 << 10)
+#define SW_CNOC_DDRT0_CFG_RSTN (1 << 11)
+#define SW_CNOC_D2D_CFG_RSTN (1 << 12)
+#define SW_CNOC_CFG_RSTN (1 << 13)
+#define SW_CNOC_CLMM_CFG_RSTN (1 << 14)
+#define SW_CNOC_AON_CFG_RSTN (1 << 15)
+
+/*LNOC*/
+#define SW_LNOC_CFG_RSTN (1 << 0)
+#define SW_LNOC_NPU_LLC_ARSTN (1 << 1)
+#define SW_LNOC_DDRC1_P0_ARSTN (1 << 2)
+#define SW_LNOC_DDRC0_P0_ARSTN (1 << 3)
+
+#endif /* __DT_ESWIN_EIC7700_RESET_H__ */
--
2.17.1

[PATCH 2/2] reset: eswin: Add eic7700 reset driver

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

Add support for reset controller in eic7700 series chips.
Provide functionality for asserting and deasserting resets
on the chip.

Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 drivers/reset/Kconfig         |   9 ++
 drivers/reset/Makefile        |   1 +
 drivers/reset/reset-eic7700.c | 249 ++++++++++++++++++++++++++++++++++
 3 files changed, 259 insertions(+)
 create mode 100644 drivers/reset/reset-eic7700.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 99f6f9784e68..d6eef5358e13 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -350,6 +350,15 @@ config RESET_ZYNQMP
 	help
 	  This enables the reset controller driver for Xilinx ZynqMP SoCs.
 
+config RESET_EIC7700
+	bool "Reset controller driver for Eswin SoCs"
+	default ARCH_ESWIN
+	help
+	  This enables the reset controller driver for Eswin SoCs. This driver is
+	  specific to Eswin SoCs and should only be enabled if using such hardware.
+	  The driver supports eic7700 series chips and provides functionality for
+	  asserting and deasserting resets on the chip.
+
 source "drivers/reset/amlogic/Kconfig"
 source "drivers/reset/starfive/Kconfig"
 source "drivers/reset/sti/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 31f9904d13f9..2210c4e55834 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
 obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
 obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
 obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
+obj-$(CONFIG_RESET_EIC7700) += reset-eic7700.o
diff --git a/drivers/reset/reset-eic7700.c b/drivers/reset/reset-eic7700.c
new file mode 100644
index 000000000000..079647280cbc
--- /dev/null
+++ b/drivers/reset/reset-eic7700.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
+ *
+ * ESWIN Reset Driver
+ *
+ * Authors:
+ *	Yifeng Huang <huangyifeng@eswincomputing.com>
+ *	Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#define SYSCRG_CLEAR_BOOT_INFO_OFFSET (0x30C)
+#define CLEAR_BOOT_FLAG_BIT BIT_ULL(0)
+
+#define SYSCRG_RESET_OFFSET (0x400)
+
+/**
+ * struct eswin_reset_data - reset controller information structure
+ * @rcdev: reset controller entity
+ * @dev: reset controller device pointer
+ * @idr: idr structure for mapping ids to reset control structures
+ */
+struct eswin_reset_data {
+	struct reset_controller_dev rcdev;
+	struct device *dev;
+	struct idr idr;
+	struct regmap *regmap;
+};
+
+/**
+ * struct eswin_reset_control - reset control structure
+ * @dev_id: SoC-specific device identifier
+ * @reset_bit: reset mask to use for toggling reset
+ */
+struct eswin_reset_control {
+	u32 dev_id;
+	u32 reset_bit;
+};
+
+#define to_eswin_reset_data(p) container_of((p), struct eswin_reset_data, rcdev)
+
+/**
+ * eswin_reset_set() - program a device's reset
+ * @rcdev: reset controller entity
+ * @id: ID of the reset to toggle
+ * @assert: boolean flag to indicate assert or deassert
+ *
+ * This is a common internal function used to assert or deassert a device's
+ * reset by clear and set the reset bit. The device's reset is asserted if the
+ * @assert argument is true, or deasserted if @assert argument is false.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int eswin_reset_set(struct reset_controller_dev *rcdev, unsigned long id,
+			   bool assert)
+{
+	struct eswin_reset_data *data = to_eswin_reset_data(rcdev);
+	struct eswin_reset_control *control;
+	int ret;
+
+	control = idr_find(&data->idr, id);
+
+	dev_dbg(rcdev->dev, "dev_id 0x%x reset_bit 0x%x assert 0x%x\r\n",
+		control->dev_id, control->reset_bit, assert);
+
+	if (!control)
+		return -EINVAL;
+
+	if (assert) {
+		ret = regmap_clear_bits(data->regmap,
+					SYSCRG_RESET_OFFSET +
+						control->dev_id * sizeof(u32),
+					control->reset_bit);
+	} else {
+		ret = regmap_set_bits(data->regmap,
+				      SYSCRG_RESET_OFFSET +
+					      control->dev_id * sizeof(u32),
+				      control->reset_bit);
+	}
+
+	return ret;
+}
+
+static int eswin_reset_reset(struct reset_controller_dev *rcdev,
+			     unsigned long id)
+{
+	int ret;
+
+	ret = eswin_reset_set(rcdev, id, true);
+	if (ret != 0)
+		return ret;
+
+	usleep_range(10, 15);
+	ret = eswin_reset_set(rcdev, id, false);
+	if (ret != 0)
+		return ret;
+
+	return 0;
+}
+
+static int eswin_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	return eswin_reset_set(rcdev, id, true);
+}
+
+static int eswin_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	return eswin_reset_set(rcdev, id, false);
+}
+
+static const struct reset_control_ops eswin_reset_ops = {
+	.reset = eswin_reset_reset,
+	.assert = eswin_reset_assert,
+	.deassert = eswin_reset_deassert,
+};
+
+static int eswin_reset_of_xlate_lookup_id(int id, void *p, void *data)
+{
+	struct of_phandle_args *reset_spec = (struct of_phandle_args *)data;
+	struct eswin_reset_control *slot_control =
+		(struct eswin_reset_control *)p;
+
+	if (reset_spec->args[0] == slot_control->dev_id &&
+	    reset_spec->args[1] == slot_control->reset_bit)
+		return id;
+	else
+		return 0;
+}
+
+/**
+ * eswin_reset_of_xlate() - translate a set of OF arguments to a reset ID
+ * @rcdev: reset controller entity
+ * @reset_spec: OF reset argument specifier
+ *
+ * This function performs the translation of the reset argument specifier
+ * values defined in a reset consumer device node. The function allocates a
+ * reset control structure for that device reset, and will be used by the
+ * driver for performing any reset functions on that reset. An idr structure
+ * is allocated and used to map to the reset control structure. This idr
+ * is used by the driver to do reset lookups.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int eswin_reset_of_xlate(struct reset_controller_dev *rcdev,
+				const struct of_phandle_args *reset_spec)
+{
+	struct eswin_reset_data *data = to_eswin_reset_data(rcdev);
+	struct eswin_reset_control *control;
+	int ret;
+
+	if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+		return -EINVAL;
+
+	ret = idr_for_each(&data->idr, eswin_reset_of_xlate_lookup_id,
+			   (void *)reset_spec);
+	if (ret != 0)
+		return ret;
+
+	control = devm_kzalloc(data->dev, sizeof(*control), GFP_KERNEL);
+	if (!control)
+		return -ENOMEM;
+
+	control->dev_id = reset_spec->args[0];
+	control->reset_bit = reset_spec->args[1];
+
+	return idr_alloc(&data->idr, control, 0, 0, GFP_KERNEL);
+}
+
+static const struct of_device_id eswin_reset_dt_ids[] = {
+	{
+		.compatible = "eswin,eic7700-reset",
+	},
+	{ /* sentinel */ },
+};
+
+static int eswin_reset_probe(struct platform_device *pdev)
+{
+	struct eswin_reset_data *data;
+	struct device *parent;
+
+	parent = pdev->dev.parent;
+	if (!parent) {
+		dev_err(&pdev->dev, "no parent\n");
+		return -ENODEV;
+	}
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->regmap = syscon_node_to_regmap(parent->of_node);
+	if (IS_ERR(data->regmap)) {
+		dev_err(&pdev->dev, "failed to get parent regmap\n");
+		return PTR_ERR(data->regmap);
+	}
+
+	platform_set_drvdata(pdev, data);
+
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.ops = &eswin_reset_ops;
+	data->rcdev.of_node = pdev->dev.of_node;
+	data->rcdev.of_reset_n_cells = 2;
+	data->rcdev.of_xlate = eswin_reset_of_xlate;
+	data->rcdev.dev = &pdev->dev;
+	data->dev = &pdev->dev;
+	idr_init(&data->idr);
+
+	/*clear boot flag so u84 and scpu could be reseted by software*/
+	regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET,
+			CLEAR_BOOT_FLAG_BIT);
+	msleep(50);
+	platform_set_drvdata(pdev, data);
+
+	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
+}
+
+static void eswin_reset_remove(struct platform_device *pdev)
+{
+	struct eswin_reset_data *data = platform_get_drvdata(pdev);
+
+	idr_destroy(&data->idr);
+}
+
+static struct platform_driver eswin_reset_driver = {
+	.probe	= eswin_reset_probe,
+	.remove = eswin_reset_remove,
+	.driver = {
+		.name		= "eswin-reset",
+		.of_match_table	= eswin_reset_dt_ids,
+	},
+};
+
+static int __init eswin_reset_init(void)
+{
+	return platform_driver_register(&eswin_reset_driver);
+}
+arch_initcall(eswin_reset_init);
-- 
2.17.1

Re: [PATCH 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC

[Rob Herring (Arm)]

On Wed, 14 May 2025 08:31:21 +0800, dongxuyang@eswincomputing.com wrote:
> From: Xuyang Dong <dongxuyang@eswincomputing.com>
> 
> Add device tree binding documentation and header file for the ESWIN
> eic7700 reset controller module.
> 
> Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
> ---
>  .../bindings/reset/eswin,eic7700-reset.yaml   |  47 +++
>  .../dt-bindings/reset/eswin,eic7700-reset.h   | 460 ++++++++++++++++++
>  2 files changed, 517 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
>  create mode 100644 include/dt-bindings/reset/eswin,eic7700-reset.h
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.example.dtb: sys-crg@51828000 (syscon): compatible: ['syscon', 'simple-mfd'] is too short
	from schema $id: http://devicetree.org/schemas/mfd/syscon-common.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.example.dtb: sys-crg@51828000 (syscon): reg: [[0, 1367506944], [0, 524288]] is too long
	from schema $id: http://devicetree.org/schemas/mfd/syscon-common.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250514003121.473-1-dongxuyang@eswincomputing.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC

[Rob Herring]

On Wed, May 14, 2025 at 08:31:21AM +0800, dongxuyang@eswincomputing.com wrote:
> From: Xuyang Dong <dongxuyang@eswincomputing.com>
> 
> Add device tree binding documentation and header file for the ESWIN
> eic7700 reset controller module.
> 
> Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
> ---
>  .../bindings/reset/eswin,eic7700-reset.yaml   |  47 +++
>  .../dt-bindings/reset/eswin,eic7700-reset.h   | 460 ++++++++++++++++++
>  2 files changed, 517 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
>  create mode 100644 include/dt-bindings/reset/eswin,eic7700-reset.h
> 
> diff --git a/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml b/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
> new file mode 100644
> index 000000000000..1a3c6d230efe
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
> @@ -0,0 +1,47 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/eswin,eic7700-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ESWIN EIC7700 SoC reset controller
> +
> +maintainers:
> +  - Yifeng Huang <huangyifeng@eswincomputing.com>
> +  - Xuyang Dong <dongxuyang@eswincomputing.com>
> +
> +description: |
> +  The reset controller registers are part of the syscrg block on
> +  the EIC7700 SoC.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: eswin,eic7700-reset
> +
> +  '#reset-cells':
> +    description: |
> +      Specifies the number of cells needed to encode a reset source.
> +      Cell #1 : module id of the reset consumer
> +      Cell #2 : bit position of the reset in each reset consumer module
> +    const: 2
> +
> +required:
> +  - compatible
> +  - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/eswin,eic7700-reset.h>
> +
> +    sys_crg: sys-crg@51828000 {
> +        compatible = "syscon", "simple-mfd";
> +        reg = <0x000000 0x51828000 0x000000 0x80000>;
> +        reset: reset-controller {
> +            compatible = "eswin,eic7700-reset";
> +            #reset-cells = <2>;

Same comment here as #clock-cells.

This is one h/w block, so there should be 1 binding for it. Make the 
binding for the sys-crg as complete as possible rather than adding 1 
feature at a time.

Rob

Re: [PATCH 2/2] reset: eswin: Add eic7700 reset driver

[Krzysztof Kozlowski]

On 14/05/2025 02:32, dongxuyang@eswincomputing.com wrote:
> From: Xuyang Dong <dongxuyang@eswincomputing.com>
> 
> Add support for reset controller in eic7700 series chips.
> Provide functionality for asserting and deasserting resets
> on the chip.
> 
> Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
> ---
>  drivers/reset/Kconfig         |   9 ++
>  drivers/reset/Makefile        |   1 +
>  drivers/reset/reset-eic7700.c | 249 ++++++++++++++++++++++++++++++++++
>  3 files changed, 259 insertions(+)
>  create mode 100644 drivers/reset/reset-eic7700.c
> 
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 99f6f9784e68..d6eef5358e13 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -350,6 +350,15 @@ config RESET_ZYNQMP
>  	help
>  	  This enables the reset controller driver for Xilinx ZynqMP SoCs.
>  
> +config RESET_EIC7700

E is not after Z. Don't add your entries to the end. This applies to all
your patches.

> +	bool "Reset controller driver for Eswin SoCs"
> +	default ARCH_ESWIN
> +	help
> +	  This enables the reset controller driver for Eswin SoCs. This driver is
> +	  specific to Eswin SoCs and should only be enabled if using such hardware.
> +	  The driver supports eic7700 series chips and provides functionality for
> +	  asserting and deasserting resets on the chip.
> +
>  source "drivers/reset/amlogic/Kconfig"
>  source "drivers/reset/starfive/Kconfig"
>  source "drivers/reset/sti/Kconfig"
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 31f9904d13f9..2210c4e55834 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -44,3 +44,4 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
>  obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
>  obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
>  obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
> +obj-$(CONFIG_RESET_EIC7700) += reset-eic7700.o

E is not after Z.


> +static int eswin_reset_probe(struct platform_device *pdev)
> +{
> +	struct eswin_reset_data *data;
> +	struct device *parent;
> +
> +	parent = pdev->dev.parent;
> +	if (!parent) {
> +		dev_err(&pdev->dev, "no parent\n");

Not possible. Fix your DTS otherwise.

> +		return -ENODEV;
> +	}
> +
> +	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> +	if (!data)
> +		return -ENOMEM;
> +
> +	data->regmap = syscon_node_to_regmap(parent->of_node);
> +	if (IS_ERR(data->regmap)) {
> +		dev_err(&pdev->dev, "failed to get parent regmap\n");
> +		return PTR_ERR(data->regmap);

Syntax is always: return dev_err_probe. You already got such comment.
All your patches repeat the same issues.

> +	}
> +
> +	platform_set_drvdata(pdev, data);
> +
> +	data->rcdev.owner = THIS_MODULE;
> +	data->rcdev.ops = &eswin_reset_ops;
> +	data->rcdev.of_node = pdev->dev.of_node;
> +	data->rcdev.of_reset_n_cells = 2;
> +	data->rcdev.of_xlate = eswin_reset_of_xlate;
> +	data->rcdev.dev = &pdev->dev;
> +	data->dev = &pdev->dev;
> +	idr_init(&data->idr);
> +
> +	/*clear boot flag so u84 and scpu could be reseted by software*/
> +	regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET,
> +			CLEAR_BOOT_FLAG_BIT);
> +	msleep(50);
> +	platform_set_drvdata(pdev, data);

Drop, no need to do it twice.


> +
> +	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
> +}
> +
> +static void eswin_reset_remove(struct platform_device *pdev)
> +{
> +	struct eswin_reset_data *data = platform_get_drvdata(pdev);
> +
> +	idr_destroy(&data->idr);
> +}
> +
> +static struct platform_driver eswin_reset_driver = {
> +	.probe	= eswin_reset_probe,
> +	.remove = eswin_reset_remove,
> +	.driver = {
> +		.name		= "eswin-reset",
> +		.of_match_table	= eswin_reset_dt_ids,
> +	},
> +};
> +
> +static int __init eswin_reset_init(void)
> +{
> +	return platform_driver_register(&eswin_reset_driver);
> +}
> +arch_initcall(eswin_reset_init);


Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC

[Krzysztof Kozlowski]

On 14/05/2025 02:31, dongxuyang@eswincomputing.com wrote:
> diff --git a/include/dt-bindings/reset/eswin,eic7700-reset.h b/include/dt-bindings/reset/eswin,eic7700-reset.h
> new file mode 100644
> index 000000000000..fcf004620db9
> --- /dev/null
> +++ b/include/dt-bindings/reset/eswin,eic7700-reset.h
> @@ -0,0 +1,460 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved.
> + *
> + * Device Tree binding constants for EIC7700 reset controller.
> + *
> + * Authors:
> + *	Yifeng Huang <huangyifeng@eswincomputing.com>
> + *	Xuyang Dong <dongxuyang@eswincomputing.com>
> + */
> +
> +#ifndef __DT_ESWIN_EIC7700_RESET_H__
> +#define __DT_ESWIN_EIC7700_RESET_H__
> +
> +#define SNOC_RST_CTRL 0X00

No, IDs are abstract, decimal numbers going from 0. Not hex.

...

> +#define SW_NOC_NSP_RSTN (1 << 0)

All these are not really bindings IDs either. This all should be 0, 1, 2
etc. Do not treat hardware numbers as bindings, because it is not needed
and it does not bring any benefits.


Best regards,
Krzysztof

Re: [PATCH 2/2] reset: eswin: Add eic7700 reset driver

[Christophe JAILLET]

Le 14/05/2025 à 02:32, 
dongxuyang-sYo9T6QOUuK8M3too/+dENBPR1lH4CV8@public.gmane.org a écrit :
> From: Xuyang Dong <dongxuyang-sYo9T6QOUuK8M3too/+dENBPR1lH4CV8@public.gmane.org>
> 
> Add support for reset controller in eic7700 series chips.
> Provide functionality for asserting and deasserting resets
> on the chip.

...

> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/slab.h>
> +#include <linux/types.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>

Would be better if fully alphabetically ordered.

> +
> +#define SYSCRG_CLEAR_BOOT_INFO_OFFSET (0x30C)

Unneeded ()

> +#define CLEAR_BOOT_FLAG_BIT BIT_ULL(0)

It is only used as a unsigned int parameter with regmap_set_bits(), so 
why ULL?

> +
> +#define SYSCRG_RESET_OFFSET (0x400)

Unneeded ()

...

> +/**
> + * eswin_reset_set() - program a device's reset
> + * @rcdev: reset controller entity
> + * @id: ID of the reset to toggle
> + * @assert: boolean flag to indicate assert or deassert
> + *
> + * This is a common internal function used to assert or deassert a device's
> + * reset by clear and set the reset bit. The device's reset is asserted if the
> + * @assert argument is true, or deasserted if @assert argument is false.
> + *
> + * Return: 0 for successful request, else a corresponding error value
> + */
> +static int eswin_reset_set(struct reset_controller_dev *rcdev, unsigned long id,
> +			   bool assert)
> +{
> +	struct eswin_reset_data *data = to_eswin_reset_data(rcdev);
> +	struct eswin_reset_control *control;
> +	int ret;
> +
> +	control = idr_find(&data->idr, id);
> +
> +	dev_dbg(rcdev->dev, "dev_id 0x%x reset_bit 0x%x assert 0x%x\r\n",
> +		control->dev_id, control->reset_bit, assert);

We test of control is NULL the line after. So if it can happen, it would 
crash here.

> +
> +	if (!control)
> +		return -EINVAL;
> +
> +	if (assert) {
> +		ret = regmap_clear_bits(data->regmap,
> +					SYSCRG_RESET_OFFSET +
> +						control->dev_id * sizeof(u32),
> +					control->reset_bit);
> +	} else {
> +		ret = regmap_set_bits(data->regmap,
> +				      SYSCRG_RESET_OFFSET +
> +					      control->dev_id * sizeof(u32),
> +				      control->reset_bit);
> +	}

No need fo { } around each of these branches.

> +
> +	return ret;
> +}
> +
> +static int eswin_reset_reset(struct reset_controller_dev *rcdev,
> +			     unsigned long id)
> +{
> +	int ret;
> +
> +	ret = eswin_reset_set(rcdev, id, true);

Would it make sense to use eswin_reset_assert()?

> +	if (ret != 0)
> +		return ret;
> +
> +	usleep_range(10, 15);
> +	ret = eswin_reset_set(rcdev, id, false);

Would it make sense to use eswin_reset_deassert()?

> +	if (ret != 0)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static int eswin_reset_assert(struct reset_controller_dev *rcdev,
> +			      unsigned long id)
> +{
> +	return eswin_reset_set(rcdev, id, true);
> +}
> +
> +static int eswin_reset_deassert(struct reset_controller_dev *rcdev,
> +				unsigned long id)
> +{
> +	return eswin_reset_set(rcdev, id, false);
> +}

...

> +static int eswin_reset_of_xlate_lookup_id(int id, void *p, void *data)
> +{
> +	struct of_phandle_args *reset_spec = (struct of_phandle_args *)data;
> +	struct eswin_reset_control *slot_control =
> +		(struct eswin_reset_control *)p;
> +
> +	if (reset_spec->args[0] == slot_control->dev_id &&
> +	    reset_spec->args[1] == slot_control->reset_bit)
> +		return id;
> +	else

Unneeded else.

> +		return 0;
> +}
> +
> +/**
> + * eswin_reset_of_xlate() - translate a set of OF arguments to a reset ID
> + * @rcdev: reset controller entity
> + * @reset_spec: OF reset argument specifier
> + *
> + * This function performs the translation of the reset argument specifier
> + * values defined in a reset consumer device node. The function allocates a
> + * reset control structure for that device reset, and will be used by the
> + * driver for performing any reset functions on that reset. An idr structure
> + * is allocated and used to map to the reset control structure. This idr
> + * is used by the driver to do reset lookups.
> + *
> + * Return: 0 for successful request, else a corresponding error value
> + */
> +static int eswin_reset_of_xlate(struct reset_controller_dev *rcdev,
> +				const struct of_phandle_args *reset_spec)
> +{
> +	struct eswin_reset_data *data = to_eswin_reset_data(rcdev);
> +	struct eswin_reset_control *control;
> +	int ret;
> +
> +	if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
> +		return -EINVAL;
> +
> +	ret = idr_for_each(&data->idr, eswin_reset_of_xlate_lookup_id,
> +			   (void *)reset_spec);
> +	if (ret != 0)

if (ret)

> +		return ret;
> +
> +	control = devm_kzalloc(data->dev, sizeof(*control), GFP_KERNEL);
> +	if (!control)
> +		return -ENOMEM;
> +
> +	control->dev_id = reset_spec->args[0];
> +	control->reset_bit = reset_spec->args[1];
> +
> +	return idr_alloc(&data->idr, control, 0, 0, GFP_KERNEL);
> +}
> +
> +static const struct of_device_id eswin_reset_dt_ids[] = {
> +	{
> +		.compatible = "eswin,eic7700-reset",
> +	},
> +	{ /* sentinel */ },

No need for a trailing , after a terminator.

> +};
> +
> +static int eswin_reset_probe(struct platform_device *pdev)
> +{
> +	struct eswin_reset_data *data;
> +	struct device *parent;
> +
> +	parent = pdev->dev.parent;
> +	if (!parent) {
> +		dev_err(&pdev->dev, "no parent\n");
> +		return -ENODEV;
> +	}
> +
> +	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> +	if (!data)
> +		return -ENOMEM;
> +
> +	data->regmap = syscon_node_to_regmap(parent->of_node);
> +	if (IS_ERR(data->regmap)) {
> +		dev_err(&pdev->dev, "failed to get parent regmap\n");
> +		return PTR_ERR(data->regmap);
> +	}
> +
> +	platform_set_drvdata(pdev, data);
> +
> +	data->rcdev.owner = THIS_MODULE;
> +	data->rcdev.ops = &eswin_reset_ops;
> +	data->rcdev.of_node = pdev->dev.of_node;
> +	data->rcdev.of_reset_n_cells = 2;
> +	data->rcdev.of_xlate = eswin_reset_of_xlate;
> +	data->rcdev.dev = &pdev->dev;
> +	data->dev = &pdev->dev;
> +	idr_init(&data->idr);
> +
> +	/*clear boot flag so u84 and scpu could be reseted by software*/

Missing spaces at the start and the end of the comment.

> +	regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET,
> +			CLEAR_BOOT_FLAG_BIT);
> +	msleep(50);
> +	platform_set_drvdata(pdev, data);
> +
> +	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
> +}

...

CJ