Re: [parisc-linux] Re: 2.6.14-rc2-pa2 ccio patch

Re: [parisc-linux] Re: 2.6.14-rc2-pa2 ccio patch

[Grant Grundler]

On Thu, Sep 29, 2005 at 11:13:45AM -0400, John David Anglin wrote:
> Specifying sr0 will cause fdc to use the space id in sr0.  There's no
> mapping to sr4-7.  This mapping is available when generating PA 2.0
> code with current cvs binutils, but only if you *do not* specify sr0.
> In PA 2.0, there are two different instruction formats for fdc (2 and
> 3-bit space register formats).

Uhm, in my copy of the book, page 7-51 shows two formats, both with
a 2-bit "s" field and clearly indicates a "space_select(s,...)" operation.

>   Only the 2-bit format has the mapping
> to sr4-7.  The 2-bit format is not available when generating PA 1.x code.

page 5-171 of my PA 1.1 book shows only a 2-bit 's' field (and indexed
by register) for FDC. Did you flip to the next page and are by
accident reading the FIC (which only has 3-bit s field) instruction?

> 
> > -	asm volatile("fdc 0(%0)" : : "r" (pdir_ptr));
> > +	asm volatile("fdc %%r0(%%sr0,%0)" : : "r" (pdir_ptr));
> 
> For this to work in PA 1.x, you need to load the space id selected
> by %0 into sr0, or ensure the kernel space id is put in sr0.  Doesn't
> sr4 have the kernel space id in it?

Yes and Yes. But my reading of the PA1.1 arch says it *only* has a 2-bit
s field.

thanks,
grant
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Re: [parisc-linux] Re: 2.6.14-rc2-pa2 ccio patch

[John David Anglin]

> Yes and Yes. But my reading of the PA1.1 arch says it *only* has a 2-bit
> s field.

Oops, my mix up (fic/fdc confusion).  However, don't add sr0 to the
instruction.  Specifying %r0 instead of '0' is the issue.  Strictly,
the immediate form is only allowed in PA 2.0.  However, if the assembler
doesn't accept it let me know.

I'm going to take a crack at trying to fix PA 1.0 to 1.1 promotion
this weekend.  This is currently tied to the the lax matching used
with PA 1.0 instructions.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)
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Re: [parisc-linux] Re: 2.6.14-rc2-pa2 ccio patch

[Grant Grundler]

On Thu, Sep 29, 2005 at 07:21:38PM -0400, John David Anglin wrote:
> > Yes and Yes. But my reading of the PA1.1 arch says it *only* has a 2-bit
> > s field.
> 
> Oops, my mix up (fic/fdc confusion).

no problem - I've done worse.

>   However, don't add sr0 to the instruction.

Why not? I added it because I didn't like assumption the caller
to *io_pdir_entry was passing KERNEL_SPACE argument. If that's going
to forever be true, then we may as well hardcode KERNEL_SPACE
in both ccio and sba io_pdir_entry() routines instead of
taking a space_id parameter. Would save us a few cycles.

>   Specifying %r0 instead of '0' is the issue.  Strictly,
> the immediate form is only allowed in PA 2.0.  However, if the assembler
> doesn't accept it let me know.

That's what it looked like to me too.
It now uses %r0.

> I'm going to take a crack at trying to fix PA 1.0 to 1.1 promotion
> this weekend.  This is currently tied to the the lax matching used
> with PA 1.0 instructions.

Like I said, this isn't a problem that bothers me.

thanks!
grant
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Re: [parisc-linux] Re: 2.6.14-rc2-pa2 ccio patch

[John David Anglin]

> I'm going to take a crack at trying to fix PA 1.0 to 1.1 promotion
> this weekend.  This is currently tied to the the lax matching used
> with PA 1.0 instructions.

I believe that binutils (cvs head) should now correctly handle promotion.
See http://sources.redhat.com/ml/binutils/2005-10/msg00085.html.  The
change also fixes a problem with "fdc" that was introduced when I added
the PA 2.0 immediate form.  It turns out that I broke the PA 1.0 register
immediate form.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)
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Re: [parisc-linux] Re: 2.6.14-rc2-pa2 ccio patch

[John David Anglin]

> > Yes and Yes. But my reading of the PA1.1 arch says it *only* has a 2-bit
> > s field.
> 
> Oops, my mix up (fic/fdc confusion).  However, don't add sr0 to the
> instruction.

I see that the change was committed with the addition of "%sr0" in the
fdc instructions.  Explicitly mentioning %sr0 in instructions with 2-bit
s-fields is discouraged.  It's unnecessary and there could be confusion
regarding its effect.  In instructions with 3-bit s-fields, %sr0 is
treated in the same manner as the other space registers.  I may add
a warning about using %sr0 in instructions with 2-bit s-fields.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)
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Re: [parisc-linux] Re: 2.6.14-rc2-pa2 ccio patch

[Joel Soete]

Grant Grundler wrote:
> On Thu, Sep 29, 2005 at 12:35:54AM -0600, Grant Grundler wrote:
> 
[...]

> -	asm volatile("fdc 0(%0)" : : "r" (pdir_ptr));
> +	asm volatile("fdc %%r0(%%sr0,%0)" : : "r" (pdir_ptr));
>  	asm volatile("sync");
did I well undurstand my reading (pa11_acd.pdf):
the mnemonics 'fdc,cmplt x(s,b)' and 'fic,cmplt x(sr,b)' refer well x as 'the index register'.

So may be have a common writing:
--- arch/parisc/kernel/pacache.S.Orig   2005-09-29 16:09:03.000000000 +0200
+++ arch/parisc/kernel/pacache.S        2005-09-29 18:21:56.000000000 +0200
@@ -227,7 +227,7 @@

  fimanyloop:                                    /* Loop if LOOP >= 2 */
         ADDIB>          -1, %r31, fimanyloop    /* Adjusted inner loop decr */
-       fice            0(%sr1, %arg0)
+       fice            %r0(%sr1, %arg0)
         fice,m          %arg1(%sr1, %arg0)      /* Last fice and addr adjust */
         movb,tr         %arg3, %r31, fimanyloop /* Re-init inner loop count */
         ADDIB<=,n       -1, %arg2, fisync       /* Outer loop decr */
@@ -269,7 +269,7 @@

  fdmanyloop:                                    /* Loop if LOOP >= 2 */
         ADDIB>          -1, %r31, fdmanyloop    /* Adjusted inner loop decr */
-       fdce            0(%sr1, %arg0)
+       fdce            %r0(%sr1, %arg0)
         fdce,m          %arg1(%sr1, %arg0)      /* Last fdce and addr adjust */
         movb,tr         %arg3, %r31, fdmanyloop /* Re-init inner loop count */
         ADDIB<=,n       -1, %arg2, fdsync       /* Outer loop decr */
--- arch/parisc/kernel/signal.c.Orig    2005-09-29 16:02:29.000000000 +0200
+++ arch/parisc/kernel/signal.c 2005-09-29 18:34:32.000000000 +0200
@@ -296,7 +296,7 @@
         struct rt_sigframe __user *frame;
         unsigned long rp, usp;
         unsigned long haddr, sigframe_size;
-       struct siginfo si;
+
         int err = 0;
  #ifdef __LP64__
         compat_int_t compat_val;
@@ -627,9 +627,9 @@

                         /* Stack is 64-byte aligned, and we only
                          * need to flush 1 cache line */
-                       asm("fdc 0(%%sr3, %0)\n"
+                       asm("fdc %%r0(%%sr3, %0)\n"
                             "sync\n"
-                           "fic 0(%%sr3, %0)\n"
+                           "fic %%r0(%%sr3, %0)\n"
                             "sync\n"
                             : : "r"(regs->gr[30]));

====<>====

(this hunk:
-       struct siginfo si;
to get rid of a compiler warning)

Hth,
	Joel
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Re: [parisc-linux] Re: 2.6.14-rc2-pa2 ccio patch

[John David Anglin]

> May I abuse of your presious time: I also recompile the kernel for a d380=
> 
> which uses ccio-dma in its term uses insn lci (see attached precompile .s=

I'll look at it.  As I recall, there wasn't much information about lha.
If lha and lci are the same, we should be using lci in the disassebly.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)
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