Re: Custom Hardware Acceleration

[Jad Naous <jnaous@stanford.edu>]

Yes, if I do end up doing it on an FPGA, it would be open-source. 
However, I'm also open to suggestions that don't necessarily end up on a 
separate (from the CPU) standalone ASIC/FPGA, but should be integrated 
into the CPU.

For example, are there any processor instructions (extensions) Xen 
developers would like to see in future processors? I'm doing research 
into either including reprogrammable hardware into a CPU (research 
oriented) or on a separate chip that is close to the CPU 
(implementation), which could then be configured according to the 
application running on it.

Returning to the example I mentioned, the instruction could then be 
implemented on the FPGA so that Xen could use it. Any ideas similar to 
this would also be very interesting. Of course, the instruction idea is 
only limited to on-chip reprogrammable logic, but the concept for an 
off-chip FPGA is similar, but limited in communication speed with the CPU.

Btw, sorry if this is not the appropriate place to post this. I'd be 
happy to move it somewhere else if I'm asked to, but I thought that this 
would be of interest to Xen developers.

Thanks,
Jad.

BSD Lazarus wrote:
> Hello Jad,
> 
> Do you plan on an open-source FPGA design?
> 
> -- David
> 
> Jad Naous wrote:
>> Hi all,
>> I am exploring the possibility of designing a custom hardware 
>> acceleration solution using an ASIC or an FPGA to accelerate some part 
>> of Xen. Basically, I am looking for some part of the code that could 
>> be built in hardware to make it faster. Does anybody know where I 
>> could get some statistics on the code, such as the most called 
>> functions, the most parallelizable functions, etc... If you could 
>> think of something that would be useful in HW I would be very 
>> interested to know.
>> Thanks,
>> Jad.
>>
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