Re: Custom Hardware Acceleration

[Jad Naous <jnaous@stanford.edu>]

Jon Mason wrote:
> On Thu, Jan 26, 2006 at 12:52:29AM -0800, Jad Naous wrote:
>> Hi all,
>> I am exploring the possibility of designing a custom hardware 
>> acceleration solution using an ASIC or an FPGA to accelerate some part 
>> of Xen. Basically, I am looking for some part of the code that could be 
>> built in hardware to make it faster. Does anybody know where I could get 
>> some statistics on the code, such as the most called functions, the most 
>> parallelizable functions, etc... If you could think of something that 
>> would be useful in HW I would be very interested to know.
>> Thanks,
>> Jad.
> 
> You could make a custom NIC FPGA that can handle paravirtulized network
> receive.  The NIC can inspect the destination MAC address of the incomming 
> packet, and DMA it to a pre-alloced space in the domU (removing the need
> for the page flip).  It will require modifing the xen network drivers,
> but should be pretty cool.
> 
> Thanks,
> Jon

Just wanted to update that we are going to implement the paravirtualized 
NIC on an FPGA, and see if you guys can suggest where to start. We have 
never done any XEN development.
The implementation should be done by the end of March. Are there any 
suggestions on how to make our FPGA implementation as portable as 
possible to other boards? The problem is we might end up using some IP 
cores for our implementation. If we have time, we'd get rid of those.
Thanks,
Jad.