* [PATCH v2 1/2] powerpc/perf: Cleanup cache_sel bits comment @ 2017-10-09 14:12 Madhavan Srinivasan 2017-10-09 14:12 ` [PATCH v2 2/2] powerpc/perf: Fix unit_sel/cache_sel checks Madhavan Srinivasan 2018-12-22 9:54 ` [v2,1/2] powerpc/perf: Cleanup cache_sel bits comment Michael Ellerman 0 siblings, 2 replies; 4+ messages in thread From: Madhavan Srinivasan @ 2017-10-09 14:12 UTC (permalink / raw) To: mpe; +Cc: linuxppc-dev, Madhavan Srinivasan Update the raw event code comment in power9-pmu.c with respect to "cache" bits, since power9 MMCRC does not support these. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> --- Changelog v1: - No change arch/powerpc/perf/power9-pmu.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c index 24b5b5b7a206..88b0a78eff4d 100644 --- a/arch/powerpc/perf/power9-pmu.c +++ b/arch/powerpc/perf/power9-pmu.c @@ -63,16 +63,8 @@ * MMCRA[9:11] = thresh_cmp[0:2] * MMCRA[12:18] = thresh_cmp[3:9] * - * if unit == 6 or unit == 7 - * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) - * else if unit == 8 or unit == 9: - * if cache_sel[0] == 0: # L3 bank - * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) - * else if cache_sel[0] == 1: - * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) - * else if cache_sel[1]: # L1 event - * MMCR1[16] = cache_sel[2] - * MMCR1[17] = cache_sel[3] + * MMCR1[16] = cache_sel[2] + * MMCR1[17] = cache_sel[3] * * if mark: * MMCRA[63] = 1 (SAMPLE_ENABLE) -- 2.7.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 2/2] powerpc/perf: Fix unit_sel/cache_sel checks 2017-10-09 14:12 [PATCH v2 1/2] powerpc/perf: Cleanup cache_sel bits comment Madhavan Srinivasan @ 2017-10-09 14:12 ` Madhavan Srinivasan 2017-10-10 4:47 ` Michael Ellerman 2018-12-22 9:54 ` [v2,1/2] powerpc/perf: Cleanup cache_sel bits comment Michael Ellerman 1 sibling, 1 reply; 4+ messages in thread From: Madhavan Srinivasan @ 2017-10-09 14:12 UTC (permalink / raw) To: mpe; +Cc: linuxppc-dev, Madhavan Srinivasan Raw event code has couple of fields "unit" and "cache" in it, to capture the "unit" to monitor for a given pmcxsel and cache reload qualifier to program in MMCR1. isa207_get_constraint() refers "unit" field to update the MMCRC (L2/L3) Event bus control fields with "cache" bits of the raw event code. These are power8 specific and not supported by PowerISA v3.0 pmu. So wrap the checks to be power8 specific. Also, "cache" bit field is referred to update MMCR1[16:17] and this check can be power8 specific. Fixes: 7ffd948fae4cd ('powerpc/perf: factor out power8 pmu functions') Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> --- These changes should not have any impact since none of the published events in power9 pmu-event json use the "cache" fields. Changelog v1: - Cleanup previously used macro - Update the constraint check arch/powerpc/perf/isa207-common.c | 25 ++++++++++++++++++------- arch/powerpc/perf/isa207-common.h | 4 ++-- 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c index 2efee3f196f5..9fd2e5c7a063 100644 --- a/arch/powerpc/perf/isa207-common.c +++ b/arch/powerpc/perf/isa207-common.c @@ -150,6 +150,14 @@ static bool is_thresh_cmp_valid(u64 event) return true; } +static unsigned int dc_ic_rld_quad_l1_sel(u64 event) +{ + unsigned int cache; + + cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK; + return cache; +} + static inline u64 isa207_find_source(u64 idx, u32 sub_idx) { u64 ret = PERF_MEM_NA; @@ -285,10 +293,10 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) * have a cache selector of zero. The bank selector (bit 3) is * irrelevant, as long as the rest of the value is 0. */ - if (cache & 0x7) + if (!cpu_has_feature(CPU_FTR_ARCH_300) && (cache & 0x7)) return -1; - } else if (event & EVENT_IS_L1) { + } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) { mask |= CNST_L1_QUAL_MASK; value |= CNST_L1_QUAL_VAL(cache); } @@ -391,11 +399,14 @@ int isa207_compute_mmcr(u64 event[], int n_ev, /* In continuous sampling mode, update SDAR on TLB miss */ mmcra_sdar_mode(event[i], &mmcra); - if (event[i] & EVENT_IS_L1) { - cache = event[i] >> EVENT_CACHE_SEL_SHIFT; - mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT; - cache >>= 1; - mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT; + if (cpu_has_feature(CPU_FTR_ARCH_300)) { + cache = dc_ic_rld_quad_l1_sel(event[i]); + mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; + } else { + if (event[i] & EVENT_IS_L1) { + cache = dc_ic_rld_quad_l1_sel(event[i]); + mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; + } } if (is_event_marked(event[i])) { diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h index 6c737d675792..493e5cc5fa8a 100644 --- a/arch/powerpc/perf/isa207-common.h +++ b/arch/powerpc/perf/isa207-common.h @@ -232,8 +232,8 @@ #define MMCR1_COMBINE_SHIFT(pmc) (35 - ((pmc) - 1)) #define MMCR1_PMCSEL_SHIFT(pmc) (24 - (((pmc) - 1)) * 8) #define MMCR1_FAB_SHIFT 36 -#define MMCR1_DC_QUAL_SHIFT 47 -#define MMCR1_IC_QUAL_SHIFT 46 +#define MMCR1_DC_IC_QUAL_MASK 0x3 +#define MMCR1_DC_IC_QUAL_SHIFT 46 /* MMCR1 Combine bits macro for power9 */ #define p9_MMCR1_COMBINE_SHIFT(pmc) (38 - ((pmc - 1) * 2)) -- 2.7.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/2] powerpc/perf: Fix unit_sel/cache_sel checks 2017-10-09 14:12 ` [PATCH v2 2/2] powerpc/perf: Fix unit_sel/cache_sel checks Madhavan Srinivasan @ 2017-10-10 4:47 ` Michael Ellerman 0 siblings, 0 replies; 4+ messages in thread From: Michael Ellerman @ 2017-10-10 4:47 UTC (permalink / raw) To: Madhavan Srinivasan; +Cc: linuxppc-dev, Madhavan Srinivasan Madhavan Srinivasan <maddy@linux.vnet.ibm.com> writes: > diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c > index 2efee3f196f5..9fd2e5c7a063 100644 > --- a/arch/powerpc/perf/isa207-common.c > +++ b/arch/powerpc/perf/isa207-common.c > @@ -285,10 +293,10 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) > * have a cache selector of zero. The bank selector (bit 3) is > * irrelevant, as long as the rest of the value is 0. > */ > - if (cache & 0x7) > + if (!cpu_has_feature(CPU_FTR_ARCH_300) && (cache & 0x7)) > return -1; > > - } else if (event & EVENT_IS_L1) { > + } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) { > mask |= CNST_L1_QUAL_MASK; > value |= CNST_L1_QUAL_VAL(cache); I don't understand this. You're saying all non L2/L3 events are L1 events on Power9. That seems wrong. > } > @@ -391,11 +399,14 @@ int isa207_compute_mmcr(u64 event[], int n_ev, > /* In continuous sampling mode, update SDAR on TLB miss */ > mmcra_sdar_mode(event[i], &mmcra); > > - if (event[i] & EVENT_IS_L1) { > - cache = event[i] >> EVENT_CACHE_SEL_SHIFT; > - mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT; > - cache >>= 1; > - mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT; > + if (cpu_has_feature(CPU_FTR_ARCH_300)) { > + cache = dc_ic_rld_quad_l1_sel(event[i]); > + mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; > + } else { > + if (event[i] & EVENT_IS_L1) { > + cache = dc_ic_rld_quad_l1_sel(event[i]); > + mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; > + } > } I also don't understand this. Both legs of the if have the exact same code, so at the very least it's factored badly. But why are we doing it for all events on Power9? cheers ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [v2,1/2] powerpc/perf: Cleanup cache_sel bits comment 2017-10-09 14:12 [PATCH v2 1/2] powerpc/perf: Cleanup cache_sel bits comment Madhavan Srinivasan 2017-10-09 14:12 ` [PATCH v2 2/2] powerpc/perf: Fix unit_sel/cache_sel checks Madhavan Srinivasan @ 2018-12-22 9:54 ` Michael Ellerman 1 sibling, 0 replies; 4+ messages in thread From: Michael Ellerman @ 2018-12-22 9:54 UTC (permalink / raw) To: Madhavan Srinivasan; +Cc: Madhavan Srinivasan, linuxppc-dev On Mon, 2017-10-09 at 14:12:39 UTC, Madhavan Srinivasan wrote: > Update the raw event code comment in power9-pmu.c with respect to > "cache" bits, since power9 MMCRC does not support these. > > Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Series applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/8c31459d6138b07537346d976e7c30 cheers ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-12-22 10:47 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-10-09 14:12 [PATCH v2 1/2] powerpc/perf: Cleanup cache_sel bits comment Madhavan Srinivasan 2017-10-09 14:12 ` [PATCH v2 2/2] powerpc/perf: Fix unit_sel/cache_sel checks Madhavan Srinivasan 2017-10-10 4:47 ` Michael Ellerman 2018-12-22 9:54 ` [v2,1/2] powerpc/perf: Cleanup cache_sel bits comment Michael Ellerman
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