Re: [XEN PATCH 3/6] xen/delay: address MISRA C:2012 Rule 5.3.

[Nicola Vetrini <nicola.vetrini@bugseng.com>]

On 07/08/2023 11:15, Jan Beulich wrote:
> On 07.08.2023 11:01, Julien Grall wrote:
>> On 07/08/2023 09:14, Jan Beulich wrote:
>>> On 04.08.2023 17:27, Nicola Vetrini wrote:
>>>> --- a/xen/include/xen/delay.h
>>>> +++ b/xen/include/xen/delay.h
>>>> @@ -5,6 +5,6 @@
>>>> 
>>>>   #include <asm/delay.h>
>>>>   #define mdelay(n) (\
>>>> -	{unsigned long msec=(n); while (msec--) udelay(1000);})
>>>> +	{unsigned long msec_=(n); while (msec_--) udelay(1000);})
>>> 
>>> As elsewhere, please also adjust style while touching the line, at
>>> least as far as the obviously wrong case goes:
>>> 
>>> #define mdelay(n) (\
>>> 	{unsigned long msec_ = (n); while (msec_--) udelay(1000);})
>>> 
>>> Even better would be
>>> 
>>> #define mdelay(n) ({ \
>>> 	unsigned long msec_ = (n); while (msec_--) udelay(1000); \
>>> })
>> 
>> If you are touching the style, about converting to a staging inline 
>> and
>> also splitting the line in multiple one?
> 
> I'd be happy about this being done, but I wouldn't want to go as far 
> with
> on-commit adjustments. Nicola, are you up to doing so in v2?
> 
> Jan

I'm afraid I don't understand what "staging inline" refers to. Other 
than that, sure thing.

-- 
Nicola Vetrini, BSc
Software Engineer, BUGSENG srl (https://bugseng.com)