From: Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
Cc: "U-Boot-Users@lists.sourceforge.net"
<U-Boot-Users@lists.sourceforge.net>,
"linuxppc-embedded@ozlabs.org" <linuxppc-embedded@ozlabs.org>
Subject: Re: [U-Boot-Users] Re: Failure of 2 BAT schemes to enable D-cache
Date: Fri, 12 May 2006 08:26:15 -0400 [thread overview]
Message-ID: <44647EE7.2020205@smiths-aerospace.com> (raw)
In-Reply-To: <20060511223814.2195C352B0C@atlas.denx.de>
Wolfgang Denk wrote:
> In message <20060511201329.23866.qmail@web37105.mail.mud.yahoo.com> you wrote:
>> Please post comments and suggestions of how I can
>> initialized MMU for d-cache performance. I am new
>> to this.
>
> We have been through this before, several times. Many times actually.
> I have explained it to you, and so did others.
>
> It is perfectly fine with me if you ignore my advice. But then please
> stop posting the same question again and again here.
>
> You will not receive any new answers.
>
> Again, and definitely for the last time:
>
> It makes no sense to try to enable the data cache on a MPC82xx system
> in U-Boot; the time you could save if you succeeded is marginal to
> your application startup time.
>
> And in Linux the D-Cache is enabled, so no changes are needed.
>
>
> Best regards,
> Wolfgang Denk
Furthermore, manipulating processor control registers interactively with
a debugger (e.g. attempting to enable dcache) is somewhere between
nearly impossible and totally impossible. Read and understand the
processor manual on the sequences required for changing control
registers and enabling/disabling cache. You cannot guarantee that the
sequences will be done properly because the debugger has LOTS of unknown
code running to implement what to you "looks like" a simple register
write command.
Signing off on this thread,
gvb
WARNING: multiple messages have this Message-ID (diff)
From: Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] Re: Failure of 2 BAT schemes to enable D-cache
Date: Fri, 12 May 2006 08:26:15 -0400 [thread overview]
Message-ID: <44647EE7.2020205@smiths-aerospace.com> (raw)
In-Reply-To: <20060511223814.2195C352B0C@atlas.denx.de>
Wolfgang Denk wrote:
> In message <20060511201329.23866.qmail@web37105.mail.mud.yahoo.com> you wrote:
>> Please post comments and suggestions of how I can
>> initialized MMU for d-cache performance. I am new
>> to this.
>
> We have been through this before, several times. Many times actually.
> I have explained it to you, and so did others.
>
> It is perfectly fine with me if you ignore my advice. But then please
> stop posting the same question again and again here.
>
> You will not receive any new answers.
>
> Again, and definitely for the last time:
>
> It makes no sense to try to enable the data cache on a MPC82xx system
> in U-Boot; the time you could save if you succeeded is marginal to
> your application startup time.
>
> And in Linux the D-Cache is enabled, so no changes are needed.
>
>
> Best regards,
> Wolfgang Denk
Furthermore, manipulating processor control registers interactively with
a debugger (e.g. attempting to enable dcache) is somewhere between
nearly impossible and totally impossible. Read and understand the
processor manual on the sequences required for changing control
registers and enabling/disabling cache. You cannot guarantee that the
sequences will be done properly because the debugger has LOTS of unknown
code running to implement what to you "looks like" a simple register
write command.
Signing off on this thread,
gvb
next prev parent reply other threads:[~2006-05-12 12:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-05-11 20:13 Failure of 2 BAT schemes to enable D-cache Om Vadlapatla
2006-05-11 20:13 ` [U-Boot-Users] " Om Vadlapatla
2006-05-11 22:38 ` Wolfgang Denk
2006-05-11 22:38 ` [U-Boot-Users] " Wolfgang Denk
2006-05-12 12:26 ` Jerry Van Baren [this message]
2006-05-12 12:26 ` Jerry Van Baren
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