[Qemu-devel] [PATCH] Restructure MIPS r4k code

[Qemu-devel] [PATCH] Restructure MIPS r4k code

[Dirk Behme]

[-- Attachment #1: Type: text/plain, Size: 721 bytes --]


This patch restructures the mips_r4k.c code. Goal is to make
it easier to add additional machines in the future. Taking
ARM as example, two additional files mips_timer.c and
mips_pic.c are introduced. The corresponding code from
mips_r4k.c is moved to these files. With this, code reuse is
possible for other machines as well and unnecessary code
duplication can be avoided.

Additionally, machine is renamed from mips_machine to
mips_r4k_machine. Again, this makes it easier to add
addional mips_xxx_machines in future.

This patch has no functional changes. Only exitsting code is
moved, machine name changes and empty function
cpu_mips_irqctrl_init() is removed.

Signed-off-by: Dirk Behme <dirk.behme_at_gmail.com>


[-- Attachment #2: mips_r4k_restructure_patch.txt --]
[-- Type: text/plain, Size: 7463 bytes --]

--- ./hw/mips_timer.c_orig	2006-05-24 19:31:37.000000000 +0200
+++ ./hw/mips_timer.c	2006-05-24 19:36:49.000000000 +0200
@@ -0,0 +1,75 @@
+/*
+ *  MIPS timer for qemu.
+ *
+ */
+
+#include "vl.h"
+
+/* MIPS R4K timer */
+uint32_t cpu_mips_get_count (CPUState *env)
+{
+    return env->CP0_Count +
+        (uint32_t)muldiv64(qemu_get_clock(vm_clock),
+                           100 * 1000 * 1000, ticks_per_sec);
+}
+
+static void cpu_mips_update_count (CPUState *env, uint32_t count,
+                                   uint32_t compare)
+{
+    uint64_t now, next;
+    uint32_t tmp;
+    
+    tmp = count;
+    if (count == compare)
+        tmp++;
+    now = qemu_get_clock(vm_clock);
+    next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
+    if (next == now)
+	next++;
+#if 0
+    if (logfile) {
+        fprintf(logfile, "%s: 0x%08llx %08x %08x => 0x%08llx\n",
+                __func__, now, count, compare, next - now);
+    }
+#endif
+    /* Store new count and compare registers */
+    env->CP0_Compare = compare;
+    env->CP0_Count =
+        count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
+    /* Adjust timer */
+    qemu_mod_timer(env->timer, next);
+}
+
+void cpu_mips_store_count (CPUState *env, uint32_t value)
+{
+    cpu_mips_update_count(env, value, env->CP0_Compare);
+}
+
+void cpu_mips_store_compare (CPUState *env, uint32_t value)
+{
+    cpu_mips_update_count(env, cpu_mips_get_count(env), value);
+    env->CP0_Cause &= ~0x00008000;
+    cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+}
+
+static void mips_timer_cb (void *opaque)
+{
+    CPUState *env;
+
+    env = opaque;
+#if 0
+    if (logfile) {
+        fprintf(logfile, "%s\n", __func__);
+    }
+#endif
+    cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
+    env->CP0_Cause |= 0x00008000;
+    cpu_interrupt(env, CPU_INTERRUPT_HARD);
+}
+
+void cpu_mips_clock_init (CPUState *env)
+{
+    env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
+    env->CP0_Compare = 0;
+    cpu_mips_update_count(env, 1, 0);
+}
--- ./hw/mips_r4k.c_orig	2006-05-24 19:30:34.000000000 +0200
+++ ./hw/mips_r4k.c	2006-05-24 19:40:01.000000000 +0200
@@ -12,103 +12,9 @@
 
 extern FILE *logfile;
 
-static PITState *pit;
-
-static void pic_irq_request(void *opaque, int level)
-{
-    CPUState *env = first_cpu;
-    if (level) {
-        env->CP0_Cause |= 0x00000400;
-        cpu_interrupt(env, CPU_INTERRUPT_HARD);
-    } else {
-	env->CP0_Cause &= ~0x00000400;
-        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
-    }
-}
-
-void cpu_mips_irqctrl_init (void)
-{
-}
-
-/* XXX: do not use a global */
-uint32_t cpu_mips_get_random (CPUState *env)
-{
-    static uint32_t seed = 0;
-    uint32_t idx;
-    seed = seed * 314159 + 1;
-    idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
-    return idx;
-}
-
-/* MIPS R4K timer */
-uint32_t cpu_mips_get_count (CPUState *env)
-{
-    return env->CP0_Count +
-        (uint32_t)muldiv64(qemu_get_clock(vm_clock),
-                           100 * 1000 * 1000, ticks_per_sec);
-}
-
-static void cpu_mips_update_count (CPUState *env, uint32_t count,
-                                   uint32_t compare)
-{
-    uint64_t now, next;
-    uint32_t tmp;
-    
-    tmp = count;
-    if (count == compare)
-        tmp++;
-    now = qemu_get_clock(vm_clock);
-    next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
-    if (next == now)
-	next++;
-#if 0
-    if (logfile) {
-        fprintf(logfile, "%s: 0x%08llx %08x %08x => 0x%08llx\n",
-                __func__, now, count, compare, next - now);
-    }
-#endif
-    /* Store new count and compare registers */
-    env->CP0_Compare = compare;
-    env->CP0_Count =
-        count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
-    /* Adjust timer */
-    qemu_mod_timer(env->timer, next);
-}
-
-void cpu_mips_store_count (CPUState *env, uint32_t value)
-{
-    cpu_mips_update_count(env, value, env->CP0_Compare);
-}
-
-void cpu_mips_store_compare (CPUState *env, uint32_t value)
-{
-    cpu_mips_update_count(env, cpu_mips_get_count(env), value);
-    env->CP0_Cause &= ~0x00008000;
-    cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
-}
-
-static void mips_timer_cb (void *opaque)
-{
-    CPUState *env;
-
-    env = opaque;
-#if 0
-    if (logfile) {
-        fprintf(logfile, "%s\n", __func__);
-    }
-#endif
-    cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
-    env->CP0_Cause |= 0x00008000;
-    cpu_interrupt(env, CPU_INTERRUPT_HARD);
-}
-
-void cpu_mips_clock_init (CPUState *env)
-{
-    env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
-    env->CP0_Compare = 0;
-    cpu_mips_update_count(env, 1, 0);
-}
+extern void pic_irq_request(void *opaque, int level);
 
+static PITState *pit;
 
 static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 {
@@ -269,7 +175,6 @@ void mips_r4k_init (int ram_size, int vg
 
     /* Init internal devices */
     cpu_mips_clock_init(env);
-    cpu_mips_irqctrl_init();
 
     cpu_register_physical_memory(0x0f00e000, 0x00001000, io_memory); // GPIO
     isa_mem_base = 0x10000000;
@@ -290,8 +195,8 @@ void mips_r4k_init (int ram_size, int vg
     }
 }
 
-QEMUMachine mips_machine = {
-    "mips",
+QEMUMachine mips_r4k_machine = {
+    "r4k",
     "mips r4k platform",
     mips_r4k_init,
 };
--- ./hw/mips_pic.c_orig	2006-05-24 19:31:09.000000000 +0200
+++ ./hw/mips_pic.c	2006-05-24 19:39:11.000000000 +0200
@@ -0,0 +1,28 @@
+/*
+ *  MIPS pic and random generator for qemu.
+ *
+ */
+
+#include "vl.h"
+
+void pic_irq_request(void *opaque, int level)
+{
+    CPUState *env = first_cpu;
+    if (level) {
+        env->CP0_Cause |= 0x00000400;
+        cpu_interrupt(env, CPU_INTERRUPT_HARD);
+    } else {
+	env->CP0_Cause &= ~0x00000400;
+        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+    }
+}
+
+/* XXX: do not use a global */
+uint32_t cpu_mips_get_random (CPUState *env)
+{
+    static uint32_t seed = 0;
+    uint32_t idx;
+    seed = seed * 314159 + 1;
+    idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
+    return idx;
+}
--- ./vl.h_orig	2006-05-24 19:30:48.000000000 +0200
+++ ./vl.h	2006-05-24 19:35:34.000000000 +0200
@@ -890,7 +890,7 @@ extern QEMUMachine core99_machine;
 extern QEMUMachine heathrow_machine;
 
 /* mips_r4k.c */
-extern QEMUMachine mips_machine;
+extern QEMUMachine mips_r4k_machine;
 
 /* shix.c */
 extern QEMUMachine shix_machine;
--- ./Makefile.target_orig	2006-05-24 19:32:34.000000000 +0200
+++ ./Makefile.target	2006-05-24 19:38:09.000000000 +0200
@@ -328,7 +328,8 @@ VL_OBJS+= grackle_pci.o prep_pci.o unin_
 DEFINES += -DHAS_AUDIO
 endif
 ifeq ($(TARGET_ARCH), mips)
-VL_OBJS+= mips_r4k.o dma.o vga.o serial.o i8254.o i8259.o smc91c111.o
+VL_OBJS+= mips_timer.o mips_pic.o mips_r4k.o 
+VL_OBJS+= dma.o vga.o serial.o i8254.o i8259.o smc91c111.o
 #VL_OBJS+= #ide.o pckbd.o fdc.o m48t59.o
 endif
 ifeq ($(TARGET_BASE_ARCH), sparc)
--- ./vl.c_orig	2006-05-24 19:30:42.000000000 +0200
+++ ./vl.c	2006-05-24 19:35:13.000000000 +0200
@@ -4938,7 +4938,7 @@ void register_machines(void)
     qemu_register_machine(&core99_machine);
     qemu_register_machine(&prep_machine);
 #elif defined(TARGET_MIPS)
-    qemu_register_machine(&mips_machine);
+    qemu_register_machine(&mips_r4k_machine);
 #elif defined(TARGET_SPARC)
 #ifdef TARGET_SPARC64
     qemu_register_machine(&sun4u_machine);