From: Peter Ryser <peter.ryser@xilinx.com>
To: Grant Likely <grant.likely@secretlab.ca>
Cc: Anantharaman Chetan-W16155 <Chetan.S.Anantharaman@motorola.com>,
linuxppc-embedded@ozlabs.org
Subject: Re: Linux 2.4 Kernel on Xilinx Virtex4 FX100's PPC
Date: Thu, 01 Jun 2006 11:03:58 -0700 [thread overview]
Message-ID: <447F2C0E.1000306@xilinx.com> (raw)
In-Reply-To: <528646bc0606011008o35096b43p42cc6aa9c0002f8c@mail.gmail.com>
It's a little bit more complicated than that but your statement is
basically correct.
- Peter
Grant Likely wrote:
> On 6/1/06, Peter Ryser <peter.ryser@xilinx.com> wrote:
>
>> There are some silicon issues on the PPC405 in V4 with PVR 0x20011430
>> which are documented in Xilinx solution record 20658. All these issues
>> are fixed in silicon where the PPC405 has a PVR of 0x20011470.
>>
>> Said that it's not true that the caches cannot be used in silicon with
>> PVR 0x20011430. The problem is a corner case which does not show in
>> typical designs.
>
>
> If I understand correctly, the cache issue only shows up with RAM
> attached to the OPB (instead of PLB). Is that correct?
>
> Cheers,
> g.
>
>
next prev parent reply other threads:[~2006-06-01 18:04 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-05-31 19:02 Linux 2.4 Kernel on Xilinx Virtex4 FX100's PPC Anantharaman Chetan-W16155
2006-05-31 19:35 ` Grant Likely
2006-05-31 21:47 ` Anantharaman Chetan-W16155
2006-05-31 22:33 ` Grant Likely
2006-06-01 16:59 ` Peter Ryser
2006-05-31 23:14 ` Anantharaman Chetan-W16155
2006-05-31 22:22 ` Aidan Williams
2006-06-01 17:05 ` Peter Ryser
2006-06-01 17:08 ` Grant Likely
2006-06-01 18:03 ` Peter Ryser [this message]
2006-06-12 16:57 ` Stephen Telfer
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