[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

Mpc7448hpc2 board flash driver support.

Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
Signed-off-by: Roy Zang	<tie-fei.zang@freescale.com>

---
 board/mpc7448hpc2/cfi_flash.c | 1273
+++++++++++++++++++++++++++++++++++++++++
 1 files changed, 1273 insertions(+), 0 deletions(-)

diff --git a/board/mpc7448hpc2/cfi_flash.c
b/board/mpc7448hpc2/cfi_flash.c
new file mode 100644
index 0000000..c901abf
--- /dev/null
+++ b/board/mpc7448hpc2/cfi_flash.c
@@ -0,0 +1,1273 @@
+/*
+ * (C) Copyright 2002-2004
+ * Brad Kemp, Seranoa Networks, Brad.Kemp at seranoa.com
+ *
+ * Copyright (C) 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Modified to work with AMD flashes
+ *
+ * Copyright (C) 2004
+ * Ed Okerson
+ * Modified to work with little-endian systems.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * History
+ * 01/20/2004 - combined variants of original driver.
+ * 01/22/2004 - Write performance enhancements for parallel chips
(Tolunay)
+ * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
+ * 01/27/2004 - Little endian support Ed Okerson
+ *
+ * Tested Architectures
+ * Port Width  Chip Width    # of banks	   Flash Chip  Board
+ * 32	       16	     1		   28F128J3    seranoa/eagle
+ * 64	       16	     1		   28F128J3    seranoa/falcon
+ *
+ */
+
+/* The DEBUG define must be before common to enable debugging */
+/* #define DEBUG	*/
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/byteorder.h>
+#include <linux/byteorder/swab.h>
+#ifdef	CFG_HPC2_FLASH_CFI_DRIVER
+
+/*
+ * This file implements a Common Flash Interface (CFI) driver for
U-Boot.
+ * The width of the port and the width of the chips are determined at
initialization.
+ * These widths are used to calculate the address for access CFI data
structures.
+ * It has been tested on an Intel Strataflash implementation and AMD
29F016D.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command
Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ *
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
+ * Table (ALT) to determine if protection is available
+ *
+ * Add support for other command sets Use the PRI and ALT to determine
command set
+ * Verify erase and program timeouts.
+ */
+
+#ifndef CFG_FLASH_BANKS_LIST
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#endif
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER	0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM	0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define AMD_CMD_RESET			0xF0
+#define AMD_CMD_WRITE			0xA0
+#define AMD_CMD_ERASE_START		0x80
+#define AMD_CMD_ERASE_SECTOR		0x30
+#define AMD_CMD_UNLOCK_START		0xAA
+#define AMD_CMD_UNLOCK_ACK		0x55
+
+#define AMD_STATUS_TOGGLE		0x40
+#define AMD_STATUS_ERROR		0x20
+#define AMD_ADDR_ERASE_START		0x555
+#define AMD_ADDR_START			0x555
+#define AMD_ADDR_ACK			0x2AA
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_PRIMARY_VENDOR	0x13
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT		0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT		0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT		0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT		0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE		0x28
+#define FLASH_OFFSET_BUFFER_SIZE	0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION	0x85
+#define FLASH_OFFSET_INTEL_PROTECTION	0x81
+
+#define FLASH_MAN_CFI			0x01000000
+
+#define CFI_CMDSET_NONE		    0
+#define CFI_CMDSET_INTEL_EXTENDED   1
+#define CFI_CMDSET_AMD_STANDARD	    2
+#define CFI_CMDSET_INTEL_STANDARD   3
+#define CFI_CMDSET_AMD_EXTENDED	    4
+#define CFI_CMDSET_MITSU_STANDARD   256
+#define CFI_CMDSET_MITSU_EXTENDED   257
+#define CFI_CMDSET_SST		    258
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+	unsigned long long ll;
+} cfiword_t;
+
+typedef union {
+	volatile unsigned char *cp;
+	volatile unsigned short *wp;
+	volatile unsigned long *lp;
+	volatile unsigned long long *llp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips
*/
+
+/*---------------------------------------------------------------------
--
+ * Functions
+ */
+
+typedef unsigned long flash_sect_t;
+
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword,
uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void
*cmdbuf);
+static void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
uint offset,
+			    uchar cmd);
+static void flash_unlock_seq(flash_info_t * info, flash_sect_t sect);
+static int flash_isequal(flash_info_t * info, flash_sect_t sect, uint
offset,
+			 uchar cmd);
+static int flash_isset(flash_info_t * info, flash_sect_t sect, uint
offset,
+		       uchar cmd);
+static int flash_toggle(flash_info_t * info, flash_sect_t sect, uint
offset,
+			uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size(ulong base, int banknum);
+static int flash_write_cfiword(flash_info_t * info, ulong dest,
+			       cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, flash_sect_t
sector,
+				   ulong tout, char *prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar
* cp,
+				 int len);
+#endif
+
+/*---------------------------------------------------------------------
--
+ * create an address based on the offset and the port width
+ */
+inline uchar *flash_make_addr(flash_info_t * info, flash_sect_t sect,
+			      uint offset)
+{
+	return ((uchar *) (info->start[sect] + (offset *
info->portwidth)));
+}
+
+#ifdef DEBUG
+/*---------------------------------------------------------------------
--
+ * Debug support
+ */
+void print_longlong(char *str, unsigned long long data)
+{
+	int i;
+	char *cp;
+
+	cp = (unsigned char *)&data;
+	for (i = 0; i < 8; i++)
+		sprintf(&str[i * 2], "%2.2x", *cp++);
+}
+static void flash_printqry(flash_info_t * info, flash_sect_t sect)
+{
+	cfiptr_t cptr;
+	int x, y;
+
+	for (x = 0; x < 0x40; x += 16 / info->portwidth) {
+		cptr.cp =
+		    flash_make_addr(info, sect, x +
FLASH_OFFSET_CFI_RESP);
+		debug("%p : ", cptr.cp);
+		for (y = 0; y < 16; y++) {
+			debug("%2.2x ", cptr.cp[y]);
+		}
+		debug(" ");
+		for (y = 0; y < 16; y++) {
+			if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
+				debug("%c", cptr.cp[y]);
+			} else {
+				debug(".");
+			}
+		}
+		debug("\n");
+	}
+}
+#endif
+
+/*---------------------------------------------------------------------
--
+ * read a character@a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uint offset)
+{
+	uchar *cp;
+
+	cp = flash_make_addr(info, 0, offset);
+#if defined(__LITTLE_ENDIAN) || defined(CONFIG_MPC7448HPC2)
+	return (cp[0]);
+#else
+	return (cp[info->portwidth - 1]);
+#endif
+}
+
+/*---------------------------------------------------------------------
--
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, flash_sect_t sect, uint
offset)
+{
+	uchar *addr;
+	ushort retval;
+
+#ifdef DEBUG
+	int x;
+#endif
+	addr = flash_make_addr(info, sect, offset);
+
+#ifdef DEBUG
+	debug("ushort addr is at %p info->portwidth = %d\n", addr,
+	      info->portwidth);
+	for (x = 0; x < 2 * info->portwidth; x++) {
+		debug("addr[%x] = 0x%x\n", x, addr[x]);
+	}
+#endif
+#if defined(__LITTLE_ENDIAN) || defined(CONFIG_MPC7448HPC2)
+	retval = ((addr[(info->portwidth)] << 8) | addr[0]);
+#else
+	retval = ((addr[(2 * info->portwidth) - 1] << 8) |
+		  addr[info->portwidth - 1]);
+#endif
+
+	debug("retval = 0x%x\n", retval);
+	return retval;
+}
+
+/*---------------------------------------------------------------------
--
+ * read a long word by picking the least significant byte of each
maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, flash_sect_t sect, uint
offset)
+{
+	uchar *addr;
+	ulong retval;
+
+#ifdef DEBUG
+	int x;
+#endif
+	addr = flash_make_addr(info, sect, offset);
+
+#ifdef DEBUG
+	debug("long addr is at %p info->portwidth = %d\n", addr,
+	      info->portwidth);
+	for (x = 0; x < 4 * info->portwidth; x++) {
+		debug("addr[%x] = 0x%x\n", x, addr[x]);
+	}
+#endif
+#if defined(__LITTLE_ENDIAN) || defined(CONFIG_MPC7448HPC2)
+	retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
+	    (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)]
<< 8);
+#else
+	retval = (addr[(2 * info->portwidth) - 1] << 24) |
+	    (addr[(info->portwidth) - 1] << 16) |
+	    (addr[(4 * info->portwidth) - 1] << 8) |
+	    addr[(3 * info->portwidth) - 1];
+#endif
+	return retval;
+}
+
+/*---------------------------------------------------------------------
--
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size =
flash_get_size(bank_base[i], i);
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			debug
+			    ("## Unknown FLASH on Bank %d - Size =
0x%08lx = %ld MB\n",
+			     i, flash_info[i].size, flash_info[i].size
<< 20);
+		}
+	}
+
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
&flash_info[0]);
+#endif
+
+	return (size);
+}
+
+/*---------------------------------------------------------------------
--
+ */
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	flash_sect_t sect;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		puts("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		puts("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be
erased!\n",
+		       prot);
+	} else {
+		putc('\n');
+	}
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			switch (info->vendor) {
+			case CFI_CMDSET_INTEL_STANDARD:
+			case CFI_CMDSET_INTEL_EXTENDED:
+				flash_write_cmd(info, sect, 0,
+						FLASH_CMD_CLEAR_STATUS);
+				flash_write_cmd(info, sect, 0,
+						FLASH_CMD_BLOCK_ERASE);
+				flash_write_cmd(info, sect, 0,
+
FLASH_CMD_ERASE_CONFIRM);
+				break;
+			case CFI_CMDSET_AMD_STANDARD:
+			case CFI_CMDSET_AMD_EXTENDED:
+				flash_unlock_seq(info, sect);
+				flash_write_cmd(info, sect,
+						AMD_ADDR_ERASE_START,
+						AMD_CMD_ERASE_START);
+				flash_unlock_seq(info, sect);
+				flash_write_cmd(info, sect, 0,
+						AMD_CMD_ERASE_SECTOR);
+				break;
+			default:
+				debug("Unkown flash vendor %d\n",
info->vendor);
+				break;
+			}
+
+			if (flash_full_status_check
+			    (info, sect, info->erase_blk_tout, "erase"))
{
+				rcode = 1;
+			} else
+				putc('.');
+		}
+	}
+	puts(" done\n");
+	return rcode;
+}
+
+/*---------------------------------------------------------------------
--
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		puts("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth << 3), (info->chipwidth << 3));
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	printf
+	    (" Erase timeout %ld ms, write timeout %ld ms, buffer write
timeout %ld ms, buffer size %d\n",
+	     info->erase_blk_tout, info->write_tout,
info->buffer_write_tout,
+	     info->buffer_size);
+
+	puts("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		int k;
+		int size;
+		int erased;
+		volatile unsigned long *flash;
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size -
info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword
access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n");
+		/* print empty and read-only info */
+		printf(" %08lX%s%s",
+		       info->start[i],
+		       erased ? " E" : "  ", info->protect[i] ? "RO " :
"   ");
+#else
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "
");
+#endif
+	}
+	putc('\n');
+	return;
+}
+
+/*---------------------------------------------------------------------
--
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	int buffered_size;
+#endif
+	/* get lower aligned address */
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if ((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for (i = 0; i < aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *) cp));
+
+		for (; (i < info->portwidth) && (cnt > 0); i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *) cp));
+		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+	/* handle the aligned part */
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	buffered_size = (info->portwidth / info->chipwidth);
+	buffered_size *= info->buffer_size;
+	while (cnt >= info->portwidth) {
+		i = buffered_size > cnt ? cnt : buffered_size;
+		if ((rc = flash_write_cfibuffer(info, wp, src, i)) !=
ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -= i;
+	}
+#else
+	while (cnt >= info->portwidth) {
+		cword.l = 0;
+		for (i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif				/* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i,
++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i < info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, &cword, (*(uchar *) cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*---------------------------------------------------------------------
--
+ */
+#ifdef CFG_FLASH_PROTECTION
+
+int flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if (prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0,
FLASH_CMD_PROTECT_CLEAR);
+
+	if ((retcode =
+	     flash_full_status_check(info, sector, info->erase_blk_tout,
+				     prot ? "protect" : "unprotect")) ==
0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if (prot == 0) {
+			flash_sect_t i;
+
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+	return retcode;
+}
+
+/*---------------------------------------------------------------------
--
+ * flash_read_user_serial - read the OneTimeProgramming cells
+ */
+void flash_read_user_serial(flash_info_t * info, void *buffer, int
offset,
+			    int len)
+{
+	uchar *src;
+	uchar *dst;
+
+	dst = buffer;
+	src = flash_make_addr(info, 0, FLASH_OFFSET_USER_PROTECTION);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
+	memcpy(dst, src + offset, len);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+}
+
+/*
+ * flash_read_factory_serial - read the device Id from the protection
area
+ */
+void flash_read_factory_serial(flash_info_t * info, void *buffer, int
offset,
+			       int len)
+{
+	uchar *src;
+
+	src = flash_make_addr(info, 0, FLASH_OFFSET_INTEL_PROTECTION);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
+	memcpy(buffer, src + offset, len);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+}
+
+#endif				/* CFG_FLASH_PROTECTION */
+
+/*
+ * flash_is_busy - check to see if the flash is busy
+ * This routine checks the status of the chip and returns true if the
chip is busy
+ */
+static int flash_is_busy(flash_info_t * info, flash_sect_t sect)
+{
+	int retval;
+
+	switch (info->vendor) {
+	case CFI_CMDSET_INTEL_STANDARD:
+	case CFI_CMDSET_INTEL_EXTENDED:
+		retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE);
+		break;
+	case CFI_CMDSET_AMD_STANDARD:
+	case CFI_CMDSET_AMD_EXTENDED:
+		retval = flash_toggle(info, sect, 0, AMD_STATUS_TOGGLE);
+		break;
+	default:
+		retval = 0;
+	}
+	debug("flash_is_busy: %d\n", retval);
+	return retval;
+}
+
+/*---------------------------------------------------------------------
--
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, flash_sect_t sector,
+			      ulong tout, char *prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer(0);
+	while (flash_is_busy(info, sector)) {
+		if (get_timer(start) > info->erase_blk_tout * CFG_HZ) {
+			printf("Flash %s timeout at address %lx data
%lx\n",
+			       prompt, info->start[sector],
+			       flash_read_long(info, sector, 0));
+			flash_write_cmd(info, sector, 0,
info->cmd_reset);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+
+/*---------------------------------------------------------------------
--
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise
do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, flash_sect_t
sector,
+				   ulong tout, char *prompt)
+{
+	int retcode;
+
+	retcode = flash_status_check(info, sector, tout, prompt);
+	switch (info->vendor) {
+	case CFI_CMDSET_INTEL_EXTENDED:
+	case CFI_CMDSET_INTEL_STANDARD:
+		if ((retcode != ERR_OK)
+		    && !flash_isequal(info, sector, 0,
FLASH_STATUS_DONE)) {
+			retcode = ERR_INVAL;
+			printf("Flash %s error at address %lx\n",
prompt,
+			       info->start[sector]);
+			if (flash_isset
+			    (info, sector, 0,
+			     FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
+				puts("Command Sequence Error.\n");
+			} else
+			    if (flash_isset
+				(info, sector, 0, FLASH_STATUS_ECLBS)) {
+				puts("Block Erase Error.\n");
+				retcode = ERR_NOT_ERASED;
+			} else
+			    if (flash_isset
+				(info, sector, 0, FLASH_STATUS_PSLBS)) {
+				puts("Locking Error\n");
+			}
+			if (flash_isset(info, sector, 0,
FLASH_STATUS_DPS)) {
+				puts("Block locked.\n");
+				retcode = ERR_PROTECTED;
+			}
+			if (flash_isset(info, sector, 0,
FLASH_STATUS_VPENS))
+				puts("Vpp Low Error.\n");
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+		break;
+	default:
+		break;
+	}
+	return retcode;
+}
+
+/*---------------------------------------------------------------------
--
+ */
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword,
uchar c)
+{
+#if defined(__LITTLE_ENDIAN)
+	unsigned short w;
+	unsigned int l;
+	unsigned long long ll;
+#endif
+
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+#if defined(__LITTLE_ENDIAN)
+		w = c;
+		w <<= 8;
+		cword->w = (cword->w >> 8) | w;
+#else
+		cword->w = (cword->w << 8) | c;
+#endif
+		break;
+	case FLASH_CFI_32BIT:
+#if defined(__LITTLE_ENDIAN)
+		l = c;
+		l <<= 24;
+		cword->l = (cword->l >> 8) | l;
+#else
+		cword->l = (cword->l << 8) | c;
+#endif
+		break;
+	case FLASH_CFI_64BIT:
+#if defined(__LITTLE_ENDIAN)
+		ll = c;
+		ll <<= 56;
+		cword->ll = (cword->ll >> 8) | ll;
+#else
+		cword->ll = (cword->ll << 8) | c;
+#endif
+		break;
+	}
+}
+
+/*---------------------------------------------------------------------
--
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void
*cmdbuf)
+{
+	int i;
+
+#if defined(__LITTLE_ENDIAN) || defined(CONFIG_MPC7448HPC2)
+	ushort stmpw;
+	uint stmpi;
+	uint stmpi2;
+#endif
+	uchar *cp = (uchar *) cmdbuf;
+
+	for (i = 0; i < info->portwidth; i++)
+		*cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
+#if defined(__LITTLE_ENDIAN) || defined(CONFIG_MPC7448HPC2)
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		break;
+	case FLASH_CFI_16BIT:
+		stmpw = *(ushort *) cmdbuf;
+		*(ushort *) cmdbuf = __swab16(stmpw);
+		break;
+	case FLASH_CFI_32BIT:
+		stmpi = *(uint *) cmdbuf;
+		*(uint *) cmdbuf = __swab32(stmpi);
+		break;
+	case FLASH_CFI_64BIT:
+		cp = (uchar *) cmdbuf;
+		stmpi = *(uint *) cp;
+		cp += 4;
+		stmpi2 = *(uint *) cp;
+		cp -= 4;
+		*(uint *) cp = __swab32(stmpi2);
+		cp += 4;
+		*(uint *) cp = __swab32(stmpi);
+		break;
+	default:
+		puts("WARNING: flash_make_cmd: unsuppported LittleEndian
mode\n");
+		break;
+	}
+#endif
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
uint offset,
+			    uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		debug("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp,
cmd,
+		      cword.c, info->chipwidth <<
CFI_FLASH_SHIFT_WIDTH);
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n",
addr.wp,
+		      cmd, cword.w, info->chipwidth <<
CFI_FLASH_SHIFT_WIDTH);
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		debug("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n",
addr.lp,
+		      cmd, cword.l, info->chipwidth <<
CFI_FLASH_SHIFT_WIDTH);
+		*addr.lp = cword.l;
+		break;
+	case FLASH_CFI_64BIT:
+#ifdef DEBUG
+		{
+			char str[20];
+
+			print_longlong(str, cword.ll);
+
+			debug("fwrite addr %p cmd %x %s 64 bit x %d
bit\n",
+			      addr.llp, cmd, str,
+			      info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+		}
+#endif
+		*addr.llp = cword.ll;
+		break;
+	}
+}
+
+static void flash_unlock_seq(flash_info_t * info, flash_sect_t sect)
+{
+	flash_write_cmd(info, sect, AMD_ADDR_START,
AMD_CMD_UNLOCK_START);
+	flash_write_cmd(info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
+}
+
+/*---------------------------------------------------------------------
--
+ */
+static int flash_isequal(flash_info_t * info, flash_sect_t sect, uint
offset,
+			 uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+
+	debug("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		debug("is= %x %x\n", cptr.cp[0], cword.c);
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		debug("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		debug("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	case FLASH_CFI_64BIT:
+#ifdef DEBUG
+		{
+			char str1[20];
+			char str2[20];
+
+			print_longlong(str1, cptr.llp[0]);
+			print_longlong(str2, cword.ll);
+			debug("is= %s %s\n", str1, str2);
+		}
+#endif
+		retval = (cptr.llp[0] == cword.ll);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*---------------------------------------------------------------------
--
+ */
+static int flash_isset(flash_info_t * info, flash_sect_t sect, uint
offset,
+		       uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	case FLASH_CFI_64BIT:
+		retval = ((cptr.llp[0] & cword.ll) == cword.ll);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*---------------------------------------------------------------------
--
+ */
+static int flash_toggle(flash_info_t * info, flash_sect_t sect, uint
offset,
+			uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] &
cword.c));
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] &
cword.w));
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] &
cword.l));
+		break;
+	case FLASH_CFI_64BIT:
+		retval = ((cptr.llp[0] & cword.ll) != (cptr.llp[0] &
cword.ll));
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*---------------------------------------------------------------------
--
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+	debug("flash detect cfi\n");
+
+	for (info->portwidth = FLASH_CFI_8BIT;
+	     info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1)
{
+		for (info->chipwidth = FLASH_CFI_BY8;
+		     info->chipwidth <= info->portwidth;
+		     info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
+					FLASH_CMD_CFI);
+			if (flash_isequal(info, 0,
FLASH_OFFSET_CFI_RESP, 'Q')
+			    && flash_isequal(info, 0,
FLASH_OFFSET_CFI_RESP + 1,
+					     'R')
+			    && flash_isequal(info, 0,
FLASH_OFFSET_CFI_RESP + 2,
+					     'Y')) {
+				info->interface =
+				    flash_read_ushort(info, 0,
+
FLASH_OFFSET_INTERFACE);
+				debug("device interface is %d\n",
+				      info->interface);
+				debug("found port %d chip %d ",
info->portwidth,
+				      info->chipwidth);
+				debug("port %d bits chip %d bits\n",
+				      info->portwidth <<
CFI_FLASH_SHIFT_WIDTH,
+				      info->chipwidth <<
CFI_FLASH_SHIFT_WIDTH);
+				return 1;
+			}
+		}
+	}
+	debug("not found\n");
+	return 0;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size(ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	int i, j;
+	flash_sect_t sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int erase_region_size;
+	int erase_region_count;
+
+	info->start[0] = base;
+
+	if (flash_detect_cfi(info)) {
+		info->vendor =
+		    flash_read_ushort(info, 0,
FLASH_OFFSET_PRIMARY_VENDOR);
+#ifdef DEBUG
+		flash_printqry(info, 0);
+#endif
+		switch (info->vendor) {
+		case CFI_CMDSET_INTEL_STANDARD:
+		case CFI_CMDSET_INTEL_EXTENDED:
+		default:
+			info->cmd_reset = FLASH_CMD_RESET;
+			break;
+		case CFI_CMDSET_AMD_STANDARD:
+		case CFI_CMDSET_AMD_EXTENDED:
+			info->cmd_reset = AMD_CMD_RESET;
+			break;
+		}
+
+		debug("manufacturer is %d\n", info->vendor);
+		size_ratio = info->portwidth / info->chipwidth;
+		/* if the chip is x8/x16 reduce the ratio by half */
+		if ((info->interface == FLASH_CFI_X8X16)
+		    && (info->chipwidth == FLASH_CFI_BY8)) {
+			size_ratio >>= 1;
+		}
+		num_erase_regions =
+		    flash_read_uchar(info,
FLASH_OFFSET_NUM_ERASE_REGIONS);
+		debug("size_ratio %d port %d bits chip %d bits\n",
size_ratio,
+		      info->portwidth << CFI_FLASH_SHIFT_WIDTH,
+		      info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+		debug("found %d erase regions\n", num_erase_regions);
+		sect_cnt = 0;
+		sector = base;
+		for (i = 0; i < num_erase_regions; i++) {
+			if (i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d
used\n",
+				       num_erase_regions,
NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0,
+					      FLASH_OFFSET_ERASE_REGIONS
+
+					      i * 4);
+			erase_region_size =
+			    (tmp & 0xffff) ? ((tmp & 0xffff) * 256) :
128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) + 1;
+			debug
+			    ("erase_region_count = %d erase_region_size
= %d\n",
+			     erase_region_count, erase_region_size);
+			for (j = 0; j < erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size *
size_ratio);
+				info->protect[sect_cnt] =
+				    flash_isset(info, sect_cnt,
+						FLASH_OFFSET_PROTECT,
+						FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size =
+		    (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
+		    size_ratio;
+		info->buffer_size =
+		    (1 << flash_read_ushort(info, 0,
FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info,
FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info,
FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info,
FLASH_OFFSET_WMAX_TOUT))) /
+		    1000;
+		info->flash_id = FLASH_MAN_CFI;
+		if ((info->interface == FLASH_CFI_X8X16)
+		    && (info->chipwidth == FLASH_CFI_BY8)) {
+			info->portwidth >>= 1;	/* XXX - Need to test on
x8/x16 in parallel. */
+		}
+		flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	}
+
+	return (info->size);
+}
+
+/*---------------------------------------------------------------------
--
+ */
+static int flash_write_cfiword(flash_info_t * info, ulong dest,
cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *) dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	case FLASH_CFI_64BIT:
+		flag = ((cptr.lp[0] & cword.ll) == cword.ll);
+		break;
+	default:
+		return 2;
+	}
+	if (!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	switch (info->vendor) {
+	case CFI_CMDSET_INTEL_EXTENDED:
+	case CFI_CMDSET_INTEL_STANDARD:
+		flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+		flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+		break;
+	case CFI_CMDSET_AMD_EXTENDED:
+	case CFI_CMDSET_AMD_STANDARD:
+		flash_unlock_seq(info, 0);
+		flash_write_cmd(info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
+		break;
+	}
+
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	case FLASH_CFI_64BIT:
+		cptr.llp[0] = cword.ll;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout,
"write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static flash_sect_t find_sector(flash_info_t * info, ulong addr)
+{
+	flash_sect_t sector;
+
+	for (sector = info->sector_count - 1; sector >= 0; sector--) {
+		if (addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar
* cp,
+				 int len)
+{
+	flash_sect_t sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+	/* buffered writes in the AMD chip set is not supported yet */
+	if ((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
+	    (info->vendor == CFI_CMDSET_AMD_EXTENDED))
+		return ERR_INVAL;
+
+	src.cp = cp;
+	dst.cp = (uchar *) dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if ((retcode =
+	     flash_status_check(info, sector, info->buffer_write_tout,
+				"write to buffer")) == ERR_OK) {
+		/* reduce the number of loops by the width of the port
*/
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		case FLASH_CFI_64BIT:
+			cnt = len >> 3;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
+		while (cnt-- > 0) {
+			switch (info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			case FLASH_CFI_64BIT:
+				*dst.llp++ = *src.llp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0,
+				FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode =
+		    flash_full_status_check(info, sector,
+					    info->buffer_write_tout,
+					    "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif				/* CFG_USE_FLASH_BUFFER_WRITE */
+#endif				/* CFG_FLASH_CFI */
-- 
1.4.0

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Sam Song]

Zang Roy-r61911 <tie-fei.zang@freescale.com> wrote:
> diff --git a/board/mpc7448hpc2/cfi_flash.c
> b/board/mpc7448hpc2/cfi_flash.c
> new file mode 100644
> index 0000000..c901abf
> --- /dev/null
> +++ b/board/mpc7448hpc2/cfi_flash.c

Any reason why to use another CFI Flash driver
but not the one in the box?

Thanks,

Sam

__________________________________________________
???????????????
http://cn.mail.yahoo.com

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

> Zang Roy-r61911 <tie-fei.zang@freescale.com> wrote:
> > diff --git a/board/mpc7448hpc2/cfi_flash.c 
> > b/board/mpc7448hpc2/cfi_flash.c new file mode 100644 index 
> > 0000000..c901abf
> > --- /dev/null
> > +++ b/board/mpc7448hpc2/cfi_flash.c
> 
> Any reason why to use another CFI Flash driver but not the 
> one in the box?

The reason is due to some byte swap issue. I will move it into the
general flash 
driver in the further.
Thanks.
Roy

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Wolfgang Denk]

In message <7EA18FDD2DC2154AA3BD6D2F22A62A0E0D2CC7@zch01exm23.fsl.freescale.net> you wrote:
>
> The reason is due to some byte swap issue. I will move it into the
> general flash 
> driver in the further.

No. Please clean up first, and then submit.

I will not accept such code duplication.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Don't hit a man when he's down - kick him; it's easier.

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

> > The reason is due to some byte swap issue. I will move it into the 
> > general flash driver in the further.
> 
> No. Please clean up first, and then submit.
> 
> I will not accept such code duplication.
> 
> Best regards,
> 
> Wolfgang Denk

There are some differences. Another reason I keep the driver in my board
directory 
is that I do not want to affect other board behavior. At lease, I am not
sure.

Is it right that I add some "ifdef BOARD_BYPE" in the general driver
code?
What's your comment?

Should I move the tsi108 feature to the general directory or just keep
it in my board 
directory?
Thanks.
Roy

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Wolfgang Denk]

In message <7EA18FDD2DC2154AA3BD6D2F22A62A0E0D2CDE@zch01exm23.fsl.freescale.net> you wrote:
>
> > I will not accept such code duplication.
> 
> There are some differences. Another reason I keep the driver in my board

Differences are  small  compared  to  the  toal  size  of  the  file.
Duplication  is always bad, as it will cause a maintenance nightmare.
It may slip though occasionally, but when I get aware of  it  I  will
not accept such duplicated code.

> directory 
> is that I do not want to affect other board behavior. At lease, I am not
> sure.

Submit a patch on the list for testing?

> Is it right that I add some "ifdef BOARD_BYPE" in the general driver
> code?

There must be no board dependent code in the CFI driver. If you  want
to  add  support for a special feature, use some CFG_HAVE_FEATURE_FOO
or the like, but only when *really* necessary.

Normally, the need for such  a  feature  in  the  CFI  driver  is  an
indication of some design error on your side.

> Should I move the tsi108 feature to the general directory or just keep
> it in my board 
> directory?

Please move to the drivers directory.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The day-to-day travails of the IBM programmer are so amusing to  most
of us who are fortunate enough never to have been one - like watching
Charlie Chaplin trying to cook a shoe.

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

> > > I will not accept such code duplication.
> > 
> > There are some differences. Another reason I keep the driver in my 
> > board
> 
> Differences are  small  compared  to  the  toal  size  of  the  file.
> Duplication  is always bad, as it will cause a maintenance nightmare.
> It may slip though occasionally, but when I get aware of  it  
> I  will not accept such duplicated code.
> 

I will erase the duplication. I never intend to slip though.

> > directory
> > is that I do not want to affect other board behavior. At 
> lease, I am 
> > not sure.
> 
> Submit a patch on the list for testing?

No, They are not for testing. I have tested them thousands of times :).
My original intend is 
to keep the code in my board directory..
 

> > Is it right that I add some "ifdef BOARD_BYPE" in the 
> general driver 
> > code?
> 
> There must be no board dependent code in the CFI driver. If 
> you  want to  add  support for a special feature, use some 
> CFG_HAVE_FEATURE_FOO or the like, but only when *really* necessary.
> 
> Normally, the need for such  a  feature  in  the  CFI  driver 
>  is  an indication of some design error on your side.

The difference is caused by ENDIAN issue.  Anyway, I will consider it
carefully. 

> 
> > Should I move the tsi108 feature to the general directory 
> or just keep 
> > it in my board directory?
> 
> Please move to the drivers directory.

OK, I will collect the feedback and refine my code.
Thanks.
Roy

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Wolfgang Denk]

In message <7EA18FDD2DC2154AA3BD6D2F22A62A0E0D2DCB@zch01exm23.fsl.freescale.net> you wrote:
>
> > > is that I do not want to affect other board behavior. At 
> > lease, I am 
> > > not sure.
> > 
> > Submit a patch on the list for testing?
> 
> No, They are not for testing. I have tested them thousands of times :).
> My original intend is 
> to keep the code in my board directory..

You wrote: "not want to affect other board behavior".
Sounds as if your code needs testing on these other boards ?

> The difference is caused by ENDIAN issue.  Anyway, I will consider it
> carefully. 

Oops? Can you program your flash for exanmple with a BDI200?


Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Pardon me for breathing, which I never do anyway so I don't know why
I bother to say it, oh God, I'm so depressed. Here's another of those
self-satisfied doors. Life! Don't talk to me about life."
                                        - Marvin the Paranoid Android

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

> >
> > > > is that I do not want to affect other board behavior. At
> > > lease, I am
> > > > not sure.
> > > 
> > > Submit a patch on the list for testing?
> > 
> > No, They are not for testing. I have tested them thousands 
> of times :).
> > My original intend is
> > to keep the code in my board directory..
> 
> You wrote: "not want to affect other board behavior".
> Sounds as if your code needs testing on these other boards ?
No, I suppose it should not. 
While, before submit, I tested the code on other
boards in my hand: mpc8540ads, mpc8560ads, mpc8555cds. They worked.

> 
> > The difference is caused by ENDIAN issue.  Anyway, I will 
> consider it 
> > carefully.
> 
> Oops? Can you program your flash for exanmple with a BDI200?
Hardware issue. I can program it with BDI2000,  PowerTAP and UsbTAP
under CodeWarrior.
Any suggestion?
Thanks.
Roy

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Wolfgang Denk]

In message <7EA18FDD2DC2154AA3BD6D2F22A62A0E0D2E89@zch01exm23.fsl.freescale.net> you wrote:
>
> > > The difference is caused by ENDIAN issue.  Anyway, I will 
> > consider it 
> > > carefully.
> > 
> > Oops? Can you program your flash for exanmple with a BDI200?
> Hardware issue. I can program it with BDI2000,  PowerTAP and UsbTAP
> under CodeWarrior.
> Any suggestion?

Please explain. When the BDI can program the flash,  the  CFI  driver
should be able to do the same. What exactly is the problem?

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
My play was a complete success.  The audience was a failure.

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

> > > > The difference is caused by ENDIAN issue.  Anyway, I will
> > > consider it
> > > > carefully.
> > > 
> > > Oops? Can you program your flash for exanmple with a BDI200?
> > Hardware issue. I can program it with BDI2000,  PowerTAP and UsbTAP 
> > under CodeWarrior.
> > Any suggestion?
> 
> Please explain. When the BDI can program the flash,  the  CFI 
>  driver should be able to do the same. What exactly is the problem?
> 

mpc7448 processor is BIG ENDIAN, while the tsi108 bridge connects the
flash chip  
by little ENDIA mode.  When I set __LITTLE_ENDIA in the cfi_flash
driver, everything seems
OK, but  the written bytes are swapped (see the following log). 
Now, It seems that if I define CFG_FLASH_USE_BUFFER_WRITE in my config
file, this issue 
can be solved. I will do more test on my board.
While, how can I set __LITTLE_ENDIA mode for cfi_driver file in a BIG
ENDIA system?
Thanks.

////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////
Please see the following log with general cfi_driver. 
The log shows my problem .
////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////
U-Boot 1.1.4-ge4f3fb8b-dirty (Aug  2 2006 - 10:01:47) Freescale MPC7448
HPC II

CPU:   MPC7448 v2.0 @ 1336 MHz
BOARD: MPC7448 HPC II
DRAM:  512 MB
FLASH: ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB
16 MB
In:    serial
Out:   serial
Err:   serial
BUS:   167 MHz
MEM:   200 MHz
CACHE: L1 Instruction cache - 32KB 8-way ENABLED
       L1 Data cache - 32KB 8-way ENABLED
       Unified L2 cache - 1MB 8-way DISABLED
Net:   TSI108_eth0, TSI108_eth1
Hit any key to stop autoboot:  0
=> fli

Bank # 1: CFI conformant FLASH (32 x 16)  Size: 16 MB in 128 Sectors
 Erase timeout 16384 ms, write timeout 1 ms, buffer write timeout 5 ms,
buffer s
ize 32
  Sector Start Addresses:
    FF000000      FF020000      FF040000      FF060000      FF080000
    FF0A0000      FF0C0000      FF0E0000      FF100000      FF120000
    FF140000      FF160000      FF180000      FF1A0000      FF1C0000
    FF1E0000      FF200000      FF220000      FF240000      FF260000
    FF280000      FF2A0000      FF2C0000      FF2E0000      FF300000
    FF320000      FF340000      FF360000      FF380000      FF3A0000
    FF3C0000      FF3E0000      FF400000      FF420000      FF440000
    FF460000      FF480000      FF4A0000      FF4C0000      FF4E0000
    FF500000      FF520000      FF540000      FF560000      FF580000
    FF5A0000      FF5C0000      FF5E0000      FF600000      FF620000
    FF640000      FF660000      FF680000      FF6A0000      FF6C0000
    FF6E0000      FF700000      FF720000      FF740000      FF760000
    FF780000      FF7A0000      FF7C0000      FF7E0000      FF800000
    FF820000      FF840000      FF860000      FF880000      FF8A0000
    FF8C0000      FF8E0000      FF900000      FF920000      FF940000
    FF960000      FF980000      FF9A0000      FF9C0000      FF9E0000
    FFA00000      FFA20000      FFA40000      FFA60000      FFA80000
    FFAA0000      FFAC0000      FFAE0000      FFB00000      FFB20000
    FFB40000      FFB60000      FFB80000      FFBA0000      FFBC0000
    FFBE0000      FFC00000      FFC20000      FFC40000      FFC60000
    FFC80000      FFCA0000      FFCC0000      FFCE0000      FFD00000
    FFD20000      FFD40000      FFD60000      FFD80000      FFDA0000
    FFDC0000      FFDE0000      FFE00000      FFE20000      FFE40000
    FFE60000      FFE80000      FFEA0000      FFEC0000      FFEE0000
    FFF00000      FFF20000      FFF40000      FFF60000      FFF80000
    FFFA0000      FFFC0000      FFFE0000

Bank # 2: missing or unknown FLASH type
=> md ff000000
ff000000: 27051956 552d426f 6f742031 2e312e34    '..VU-Boot 1.1.4
ff000010: 2d673230 38653063 38312d64 69727479    -g208e0c81-dirty
ff000020: 20284a75 6c203131 20323030 36202d20     (Jul 11 2006 -
ff000030: 31313a34 343a3333 29204672 65657363    11:44:33) Freesc
ff000040: 616c6520 4d504337 34343820 48504320    ale MPC7448 HPC
ff000050: 49490000 00000000 00000000 00000000    II..............
ff000060: 00000000 00000000 00000000 00000000    ................
ff000070: 00000000 00000000 00000000 00000000    ................
ff000080: 00000000 00000000 00000000 00000000    ................
ff000090: 00000000 00000000 00000000 00000000    ................
ff0000a0: 00000000 00000000 00000000 00000000    ................
ff0000b0: 00000000 00000000 00000000 00000000    ................
ff0000c0: 00000000 00000000 00000000 00000000    ................
ff0000d0: 00000000 00000000 00000000 00000000    ................
ff0000e0: 00000000 00000000 00000000 00000000    ................
ff0000f0: 00000000 00000000 00000000 00000000    ................
=> erase fff80000 fff9ffff

. done
Erased 1 sectors
=> cp.b ff000000 fff80000 20000
Copy to Flash... done
=> md fff80000
fff80000: 56190527 6f422d55 3120746f 342e312e    V..'oB-U1 to4.1.
fff80010: 3032672d 63306538 642d3138 79747269    02g-c0e8d-18ytri
fff80020: 754a2820 3131206c 30303220 202d2036    uJ( 11 l002  - 6
fff80030: 343a3131 33333a34 72462029 63736565    4:1133:4rF )csee
fff80040: 20656c61 3743504d 20383434 20435048     ela7CPM 844 CPH
fff80050: 00004949 00000000 00000000 00000000    ..II............
fff80060: 00000000 00000000 00000000 00000000    ................
fff80070: 00000000 00000000 00000000 00000000    ................
fff80080: 00000000 00000000 00000000 00000000    ................
fff80090: 00000000 00000000 00000000 00000000    ................
fff800a0: 00000000 00000000 00000000 00000000    ................
fff800b0: 00000000 00000000 00000000 00000000    ................
fff800c0: 00000000 00000000 00000000 00000000    ................
fff800d0: 00000000 00000000 00000000 00000000    ................
fff800e0: 00000000 00000000 00000000 00000000    ................
fff800f0: 00000000 00000000 00000000 00000000    ................
=>

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Wolfgang Denk]

In message <7EA18FDD2DC2154AA3BD6D2F22A62A0E0D2F42@zch01exm23.fsl.freescale.net> you wrote:
> 
> mpc7448 processor is BIG ENDIAN, while the tsi108 bridge connects the
> flash chip  
> by little ENDIA mode.  When I set __LITTLE_ENDIA in the cfi_flash
> driver, everything seems
> OK, but  the written bytes are swapped (see the following log). 
> Now, It seems that if I define CFG_FLASH_USE_BUFFER_WRITE in my config
> file, this issue 
> can be solved. I will do more test on my board.
> While, how can I set __LITTLE_ENDIA mode for cfi_driver file in a BIG
> ENDIA system?

Please check your keyboard; the 'N' key seems to fail quite often.

> FLASH: ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB
> 16 MB
...
> => fli
> 
> Bank # 1: CFI conformant FLASH (32 x 16)  Size: 16 MB in 128 Sectors
>  Erase timeout 16384 ms, write timeout 1 ms, buffer write timeout 5 ms,
> buffer size 32

Stop. What's this. First we see a report of "Unknown  FLASH  on  Bank
1",  and  that  the size has been set to 0, and here we get different
information?

>   Sector Start Addresses:
>     FF000000      FF020000      FF040000      FF060000      FF080000
...
>     FFFA0000      FFFC0000      FFFE0000
> 
> Bank # 2: missing or unknown FLASH type

And what's this about Bank # 2???

This seems to be a bug. Please fix this first.


> => md ff000000
> ff000000: 27051956 552d426f 6f742031 2e312e34    '..VU-Boot 1.1.4
> ff000010: 2d673230 38653063 38312d64 69727479    -g208e0c81-dirty
...
> => cp.b ff000000 fff80000 20000
> Copy to Flash... done

So you are copying some area within the *same*  memory  device  (your
flash memory)...

> => md fff80000
> fff80000: 56190527 6f422d55 3120746f 342e312e    V..'oB-U1 to4.1.
> fff80010: 3032672d 63306538 642d3138 79747269    02g-c0e8d-18ytri

You read from memory, write to the same memory device, and  read  the
written  data  back from the same memory device, and find the data to
be swapped?

That would mean that reading and writing memory  use  different  byte
order. If this is true, then you're screwed.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Mandrell: "You know what I think?"
Doctor:   "Ah, ah that's a catch question. With a brain your size you
          don't think, right?"
                - Dr. Who

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Andreas Engel]

Wolfgang Denk wrote:
> In message <7EA18FDD2DC2154AA3BD6D2F22A62A0E0D2F42@zch01exm23.fsl.freescale.net> you wrote:
>> FLASH: ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB
>> 16 MB
> ...
>> => fli
>>
>> Bank # 1: CFI conformant FLASH (32 x 16)  Size: 16 MB in 128 Sectors
>>  Erase timeout 16384 ms, write timeout 1 ms, buffer write timeout 5 ms,
>> buffer size 32
> 
> Stop. What's this. First we see a report of "Unknown  FLASH  on  Bank
> 1",  and  that  the size has been set to 0, and here we get different
> information?
> 
>>   Sector Start Addresses:
>>     FF000000      FF020000      FF040000      FF060000      FF080000
> ...
>>     FFFA0000      FFFC0000      FFFE0000
>>
>> Bank # 2: missing or unknown FLASH type
> 
> And what's this about Bank # 2???
> 
> This seems to be a bug. Please fix this first.

This is a bug in u-boot I already reported in May. Maybe it has been
ignored because of the missing changelog and signed-off-by?

Regards,
  Andreas Engel
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[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

> > 
> > mpc7448 processor is BIG ENDIAN, while the tsi108 bridge 
> connects the 
> > flash chip by little ENDIAN mode.  When I set __LITTLE_ENDIAN in the

> > cfi_flash driver, everything seems OK, but  the written bytes are 
> > swapped (see the following log).
> > Now, It seems that if I define CFG_FLASH_USE_BUFFER_WRITE 
> in my config 
> > file, this issue can be solved. I will do more test on my board.
> > While, how can I set __LITTLE_ENDIAN mode for cfi_driver 
> file in a BIG 
> > ENDIAN system?
> 
> Please check your keyboard; the 'N' key seems to fail quite often.

Sorry, I have changed my keyboard:).

> 
> > FLASH: ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB
> > 16 MB
> ...
> > => fli
> > 
> > Bank # 1: CFI conformant FLASH (32 x 16)  Size: 16 MB in 
> 128 Sectors  
> > Erase timeout 16384 ms, write timeout 1 ms, buffer write 
> timeout 5 ms, 
> > buffer size 32
> 
> Stop. What's this. First we see a report of "Unknown  FLASH  
> on  Bank 1",  and  that  the size has been set to 0, and here 
> we get different information?

That first "Bank1 " is not this "Bank #1".  this "BANK #1"  should refer
the Bank index 0. 
It might be a bug in u-boot. Please compare the following code in
u-boot.

in file cfi_flash.c :
unsigned long flash_init (void)
{
...
	/* Init: no FLASHes known */
	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
		flash_info[i].flash_id = FLASH_UNKNOWN;
		size += flash_info[i].size = flash_get_size
(bank_base[i], i);
		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
#ifndef CFG_FLASH_QUIET_TEST
			printf ("## Unknown FLASH on Bank %d - Size =
0x%08lx = %ld MB\n",
				i, flash_info[i].size,
flash_info[i].size << 20);
#endif /* CFG_FLASH_QUIET_TEST */
 ...
The index start from 0.

in file cmd_flash.c
int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
...
	if (argc == 1) {	/* print info for all FLASH banks */
		for (bank=0; bank <CFG_MAX_FLASH_BANKS; ++bank) {
			printf ("\nBank # %ld: ", bank+1);

			flash_print_info (&flash_info[bank]);
		}
		return 0;
	}
...
the print information start from bank+1.

Should they be unified?

> 
> >   Sector Start Addresses:
> >     FF000000      FF020000      FF040000      FF060000      FF080000
> ...
> >     FFFA0000      FFFC0000      FFFE0000
> > 
> > Bank # 2: missing or unknown FLASH type
> 
> And what's this about Bank # 2???
> 
> This seems to be a bug. Please fix this first.

It is not a bug. This "Bank #2 " refer to the previous "## Unknown FLASH
on Bank 1". 
This device is a flash emulator (PromJet) on my board. If you are
unhappy with this 
information, I can remove it by setting my CFG_MAX_FLASH_BANKS to 1.

> 
> 
> > => md ff000000
> > ff000000: 27051956 552d426f 6f742031 2e312e34    '..VU-Boot 1.1.4
> > ff000010: 2d673230 38653063 38312d64 69727479    -g208e0c81-dirty
> ...
> > => cp.b ff000000 fff80000 20000
> > Copy to Flash... done
> 
> So you are copying some area within the *same*  memory  
> device  (your flash memory)...
> 
> > => md fff80000
> > fff80000: 56190527 6f422d55 3120746f 342e312e    V..'oB-U1 to4.1.
> > fff80010: 3032672d 63306538 642d3138 79747269    02g-c0e8d-18ytri
> 
> You read from memory, write to the same memory device, and  
> read  the written  data  back from the same memory device, 
> and find the data to be swapped?

Sure!

> 
> That would mean that reading and writing memory  use  
> different  byte order. If this is true, then you're screwed.
> 

Sorry. I do not touch alcohol  these days :). it is the same phenomena
copying 
data from  DDR ram to flash. 
The only modification I do is introducing a define 
__LITTLE_ENDIAN in file cfi_flash.c. Just as I said, If I 
define CFG_FLASH_USE_BUFFER_WRITE , it will
be OK.  I will explore this. Any comment?

Roy

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

> > 
> > > FLASH: ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB
> > > 16 MB
> > ...
> > > => fli
> > > 
> > > Bank # 1: CFI conformant FLASH (32 x 16)  Size: 16 MB in 
> > 128 Sectors  
> > > Erase timeout 16384 ms, write timeout 1 ms, buffer write 
> > timeout 5 ms, 
> > > buffer size 32
> > 
> > Stop. What's this. First we see a report of "Unknown  FLASH  
> > on  Bank 1",  and  that  the size has been set to 0, and here 
> > we get different information?
> 
> That first "Bank1 " is not this "Bank #1".  this "BANK #1"  
> should refer
> the Bank index 0. 
> It might be a bug in u-boot. Please compare the following code in
> u-boot.
> 
> in file cfi_flash.c :
> unsigned long flash_init (void)
> {
> ...
> 	/* Init: no FLASHes known */
> 	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
> 		flash_info[i].flash_id = FLASH_UNKNOWN;
> 		size += flash_info[i].size = flash_get_size
> (bank_base[i], i);
> 		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
> #ifndef CFG_FLASH_QUIET_TEST
> 			printf ("## Unknown FLASH on Bank %d - Size =
> 0x%08lx = %ld MB\n",
> 				i, flash_info[i].size,
> flash_info[i].size << 20);
> #endif /* CFG_FLASH_QUIET_TEST */
>  ...
> The index start from 0.
> 
> in file cmd_flash.c
> int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
> {
> ...
> 	if (argc == 1) {	/* print info for all FLASH banks */
> 		for (bank=0; bank <CFG_MAX_FLASH_BANKS; ++bank) {
> 			printf ("\nBank # %ld: ", bank+1);
> 
> 			flash_print_info (&flash_info[bank]);
> 		}
> 		return 0;
> 	}
> ...
> the print information start from bank+1.
> 
> Should they be unified?

How about this?

> 
> > 
> > >   Sector Start Addresses:
> > >     FF000000      FF020000      FF040000      FF060000    
>   FF080000
> > ...
> > >     FFFA0000      FFFC0000      FFFE0000
> > > 
> > > Bank # 2: missing or unknown FLASH type
> > 
> > And what's this about Bank # 2???
> > 
> > This seems to be a bug. Please fix this first.
> 
> It is not a bug. This "Bank #2 " refer to the previous "## 
> Unknown FLASH
> on Bank 1". 
> This device is a flash emulator (PromJet) on my board. If you are
> unhappy with this 
> information, I can remove it by setting my CFG_MAX_FLASH_BANKS to 1.
> 
> > 
> > 
> > > => md ff000000
> > > ff000000: 27051956 552d426f 6f742031 2e312e34    '..VU-Boot 1.1.4
> > > ff000010: 2d673230 38653063 38312d64 69727479    -g208e0c81-dirty
> > ...
> > > => cp.b ff000000 fff80000 20000
> > > Copy to Flash... done
> > 
> > So you are copying some area within the *same*  memory  
> > device  (your flash memory)...
> > 
> > > => md fff80000
> > > fff80000: 56190527 6f422d55 3120746f 342e312e    V..'oB-U1 to4.1.
> > > fff80010: 3032672d 63306538 642d3138 79747269    02g-c0e8d-18ytri
> > 
> > You read from memory, write to the same memory device, and  
> > read  the written  data  back from the same memory device, 
> > and find the data to be swapped?
> 
> Sure!
> 
> > 
> > That would mean that reading and writing memory  use  
> > different  byte order. If this is true, then you're screwed.
> > 
> 
> Sorry. I do not touch alcohol  these days :). it is the same phenomena
> copying 
> data from  DDR ram to flash. 
> The only modification I do is introducing a define 
> __LITTLE_ENDIAN in file cfi_flash.c. Just as I said, If I 
> define CFG_FLASH_USE_BUFFER_WRITE , it will
> be OK.  I will explore this. Any comment?
> 

The issue should locate at function write_buff() for my board.
if define __LITTLE_ENDIAN, the function flash_add_byte() will swap the
bytes.
define CFG_FLASH_USE_BUFFER_WRITE can not solve all the problems.
For handling unaligned head and tail bytes, the byte swap issue also
exists.
For example
=> cp.b 400002 fff80002 12 (from ram to flash).
To solve the issue of general cfi_flash driver for my board. I introduce
a flag
CFG_FLASH_TSI_SWAP (tsi108/108 swap issue) and add the following patch.
Is there any comment?
Thanks.
Roy


diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index fd0a186..0d92a99 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -268,7 +268,7 @@ inline uchar flash_read_uchar (flash_inf
 	uchar *cp;
 
 	cp = flash_make_addr (info, 0, offset);
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_FLASH_TSI_SWAP)
 	return (cp[0]);
 #else
 	return (cp[info->portwidth - 1]);
@@ -295,7 +295,7 @@ #ifdef DEBUG
 		debug ("addr[%x] = 0x%x\n", x, addr[x]);
 	}
 #endif
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_FLASH_TSI_SWAP)
 	retval = ((addr[(info->portwidth)] << 8) | addr[0]);
 #else
 	retval = ((addr[(2 * info->portwidth) - 1] << 8) |
@@ -327,7 +327,7 @@ #ifdef DEBUG
 		debug ("addr[%x] = 0x%x\n", x, addr[x]);
 	}
 #endif
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_FLASH_TSI_SWAP)
 	retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
 		(addr[(2 * info->portwidth)]) | (addr[(3 *
info->portwidth)] << 8);
 #else
@@ -596,7 +596,6 @@ #ifdef CFG_FLASH_USE_BUFFER_WRITE
 	int buffered_size;
 #endif
 	/* get lower aligned address */
-	/* get lower aligned address */
 	wp = (addr & ~(info->portwidth - 1));
 
 	/* handle unaligned start */
@@ -892,7 +891,7 @@ static void flash_make_cmd (flash_info_t
 	int i;
 	uchar *cp = (uchar *) cmdbuf;
 
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_FLASH_TSI_SWAP)
 	for (i = info->portwidth; i > 0; i--)
 #else
 	for (i = 1; i <= info->portwidth; i++)

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Wolfgang Denk]

In message <7EA18FDD2DC2154AA3BD6D2F22A62A0E0D319B@zch01exm23.fsl.freescale.net> you wrote:
>
> > Should they be unified?
> 
> How about this?

I will check in Andreas Engel's patch ASAP - as time permits.

> -#if defined(__LITTLE_ENDIAN)
> +#if defined(__LITTLE_ENDIAN) || defined(CFG_FLASH_TSI_SWAP)

As mentioned before, I will not accept board specific  code  in  this
file.  Please chose a generic name for the #define which desribes the
problem, not your board.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Systems programmers are the high priests of a low cult.
                                                       -- R.S. Barton

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

> 
> In message 
> <7EA18FDD2DC2154AA3BD6D2F22A62A0E0D319B@zch01exm23.fsl.freesca
> le.net> you wrote:
> >
> > > Should they be unified?
> > 
> > How about this?
> 
> I will check in Andreas Engel's patch ASAP - as time permits.
> 
> > -#if defined(__LITTLE_ENDIAN)
> > +#if defined(__LITTLE_ENDIAN) || defined(CFG_FLASH_TSI_SWAP)
> 
> As mentioned before, I will not accept board specific  code  
> in  this file.  Please chose a generic name for the #define 
> which desribes the problem, not your board.

I always remember your word:). 
CFG_FLASH_TSI_SWAP is not my board specific code. My board 
name is MPC7448HPC2:).  This flag deals with such type of 
systems:
(1) 74xx + tsi108/9
(2) The flash data line is connected with tsi108 data line by little
Endian mode.
I will consider a more reasonable name.
Thanks.
Roy

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Wolfgang Denk]

In message <7EA18FDD2DC2154AA3BD6D2F22A62A0E0D31AE@zch01exm23.fsl.freescale.net> you wrote:
> 
> I always remember your word:). 

Excellent to know. So I finally know whom to ask when I can't
remember :-)

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Little known fact about Middle Earth:   The Hobbits had a very sophi-
sticated computer network!   It was a Tolkien Ring...

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

> > 
> > I always remember your word:). 
> 
> Excellent to know. So I finally know whom to ask when I can't 
> remember :-)
> 
That is OK! 

In file cfi_flash.c, why there are two same comments?
 	
int buffered_size;
 #endif
 	/* get lower aligned address */
-	/* get lower aligned address */
 	wp = (addr & ~(info->portwidth - 1));
 
 	/* handle unaligned start */

it seems strange. 
Roy

[U-Boot-Users] [PATCH 05/08]: mpc7448hpc2 board flash support

[Zang Roy-r61911]

> Wolfgang Denk wrote:
> > In message 
> <7EA18FDD2DC2154AA3BD6D2F22A62A0E0D2F42@zch01exm23.fsl.freesca
> le.net> you wrote:
> >> FLASH: ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB
> >> 16 MB
> > ...
> >> => fli
> >>
> >> Bank # 1: CFI conformant FLASH (32 x 16)  Size: 16 MB in 
> 128 Sectors  
> >> Erase timeout 16384 ms, write timeout 1 ms, buffer write timeout 5 
> >> ms, buffer size 32
> > 
> > Stop. What's this. First we see a report of "Unknown  FLASH 
>  on  Bank 
> > 1",  and  that  the size has been set to 0, and here we get 
> different 
> > information?
> > 
> >>   Sector Start Addresses:
> >>     FF000000      FF020000      FF040000      FF060000     
>  FF080000
> > ...
> >>     FFFA0000      FFFC0000      FFFE0000
> >>
> >> Bank # 2: missing or unknown FLASH type
> > 
> > And what's this about Bank # 2???
> > 
> > This seems to be a bug. Please fix this first.
> 
> This is a bug in u-boot I already reported in May. Maybe it 
> has been ignored because of the missing changelog and signed-off-by?
> 
It should be fixed in u-boot.
Roy