* aplay skipping first periods
@ 2006-08-12 3:05 Julien Bramary
2006-08-12 3:44 ` Julien Bramary
0 siblings, 1 reply; 2+ messages in thread
From: Julien Bramary @ 2006-08-12 3:05 UTC (permalink / raw)
To: alsa-devel
When testing my driver at low sampling rates like 8k,
I noticed that aplay was skipping the very first samples.
This skipping process might also happen at 44.1k but is then too short
to be noticeable.
Is this a know issue with aplay or a bug with my driver?
I really don't see how my code could be causing this.
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^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: aplay skipping first periods
2006-08-12 3:05 aplay skipping first periods Julien Bramary
@ 2006-08-12 3:44 ` Julien Bramary
0 siblings, 0 replies; 2+ messages in thread
From: Julien Bramary @ 2006-08-12 3:44 UTC (permalink / raw)
To: Julien Bramary; +Cc: alsa-devel
Julien Bramary wrote:
> When testing my driver at low sampling rates like 8k,
> I noticed that aplay was skipping the very first samples.
>
> This skipping process might also happen at 44.1k but is then too short
> to be noticeable.
>
> Is this a know issue with aplay or a bug with my driver?
> I really don't see how my code could be causing this.
>
No it was my code breaking the stuff.
Some obscure transfer request that I was enabling too soon.
I needed to add that in the trigger callback instead of the open callback.
Here is my new trigger, do you think it is short enough? (atomicity in
mind):
static int snd_card_mdac3560c_pcm_trigger(struct snd_pcm_substream
*substream, int cmd)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_mdac3560c_pcm *dpcm = runtime->private_data;
int err = 0;
spin_lock(&dpcm->lock);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
unlock_mdac_irq(); /* enable hardware IRQ */
at91_ssc_write(AT91_PDC_PTCR, AT91_PDC_TXTEN); /* enable PDC
transfer requests */
at91_ssc_write(AT91_SSC_CR, AT91_SSC_TXEN); /* enable SSC
(I2S) data Tx */
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
at91_ssc_write(AT91_SSC_CR, AT91_SSC_TXDIS); /* disable SSC
(I2S) data Tx */
at91_ssc_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS); /* disable
PDC transfer requests */
lock_mdac_irq(); /* disable hardware IRQ /*
break;
default:
err = -EINVAL;
break;
}
spin_unlock(&dpcm->lock);
return 0;
}
Cheers then,
Julien
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^ permalink raw reply [flat|nested] 2+ messages in thread
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