[PATCH] TX49 has write buffer

[PATCH] TX49 has write buffer

[Sergei Shtylyov]

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TX49 CPUs have a write buffer, so we need to select CPU_HAS_WB -- otherwise 
all Toshiba RBTX49xx kernels fail to build.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>


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Index: linux-mips/arch/mips/Kconfig
===================================================================
--- linux-mips.orig/arch/mips/Kconfig
+++ linux-mips/arch/mips/Kconfig
@@ -1225,6 +1225,7 @@ config CPU_TX49XX
 	bool "R49XX"
 	depends on SYS_HAS_CPU_TX49XX
 	select CPU_HAS_LLSC
+	select CPU_HAS_WB
 	select CPU_HAS_PREFETCH
 	select CPU_SUPPORTS_32BIT_KERNEL
 	select CPU_SUPPORTS_64BIT_KERNEL

Re: [PATCH] TX49 has write buffer

[Atsushi Nemoto]

On Sat, 19 Aug 2006 03:00:23 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> TX49 CPUs have a write buffer, so we need to select CPU_HAS_WB -- otherwise 
> all Toshiba RBTX49xx kernels fail to build.

TX49 CPUs also have a SYNC instruction which flushes a write buffer.
I think it is enough and wbflush() have been abused in
arch/mips/tx4927/ and arch/mips/tx4938/ codes.

There is old thread about this issue:

http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=Pine.GSO.3.96.1030415161611.13254H-100000%40delta.ds2.pg.gda.pl

---
Atsushi Nemoto

Re: [PATCH] TX49 has write buffer

[Sergei Shtylyov]

Hello.

Atsushi Nemoto wrote:

>>TX49 CPUs have a write buffer, so we need to select CPU_HAS_WB -- otherwise 
>>all Toshiba RBTX49xx kernels fail to build.

> TX49 CPUs also have a SYNC instruction which flushes a write buffer.
> I think it is enough and wbflush() have been abused in
> arch/mips/tx4927/ and arch/mips/tx4938/ codes.

    How about a patch? I needed the kernel up and running, so I came up with 
the obvious patch. I don't have no time to fix this assumed abuse.
    I should also note, that this patch wasn't enough to bring RBTX4938 kernel 
back to life since rbhma4500_defconfig is broken somewhere so the kernel 
doesn't output anything on the colsole). If I have some more time, I'll try to 
investigate what exactly was causing this (I have a working .config)...

WBR, Sergei

Re: [PATCH] TX49 has write buffer

[Sergei Shtylyov]

Hello.

Sergei Shtylyov wrote:

> TX49 CPUs have a write buffer, so we need to select CPU_HAS_WB -- 
> otherwise all Toshiba RBTX49xx kernels fail to build.

    The uptimate reason is I think that <asm/system.h> doesn't include 
<asm/wbflush.h> if CONFIG_CPU_HAS_WB is undefined -- although, <asm/wbflush.h> 
handles this situation itself. Well, <asm/system.h> doesn't need the wbflush() 
macro in that case, so it's in his own right to not include that header...

WBR, Sergei

Re: [PATCH] TX49 has write buffer

[Atsushi Nemoto]

On Sat, 19 Aug 2006 20:36:13 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
>     The uptimate reason is I think that <asm/system.h> doesn't
> include <asm/wbflush.h> if CONFIG_CPU_HAS_WB is undefined --
> although, <asm/wbflush.h> handles this situation itself. Well,
> <asm/system.h> doesn't need the wbflush() macro in that case, so
> it's in his own right to not include that header...

Yes, so I think we should include <asm/wbflush.h> if we used
wbflush().  Here is my proposal patch.


Subject: Fix build errors related to wbflush.h on tx4927/tx4938.

TX49 CPUs have a SYNC instruction so that CONFIG_CPU_HAS_WB is no
longer needed.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>

diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index 3ace403..4658b2a 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -53,19 +53,9 @@ void __init tx4927_time_init(void);
 void dump_cp0(char *key);
 
 
-void (*__wbflush) (void);
-
-static void tx4927_write_buffer_flush(void)
-{
-	__asm__ __volatile__
-	    ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
-}
-
-
 void __init plat_mem_setup(void)
 {
 	board_time_init = tx4927_time_init;
-	__wbflush = tx4927_write_buffer_flush;
 
 #ifdef CONFIG_TOSHIBA_RBTX4927
 	{
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index b0f021f..1b7cde1 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -130,6 +130,7 @@ #include <asm/processor.h>
 #include <asm/ptrace.h>
 #include <asm/reboot.h>
 #include <asm/time.h>
+#include <asm/wbflush.h>
 #include <linux/bootmem.h>
 #include <linux/blkdev.h>
 #ifdef CONFIG_RTC_DS1742
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index dc30d66..f2be0ea 100644
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -30,6 +30,7 @@ #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
+#include <asm/wbflush.h>
 #include <asm/tx4938/rbtx4938.h>
 
 /**********************************************************************************/
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
index 71859c4..f415a1f 100644
--- a/arch/mips/tx4938/common/setup.c
+++ b/arch/mips/tx4938/common/setup.c
@@ -41,29 +41,10 @@ void __init tx4938_setup(void);
 void __init tx4938_time_init(void);
 void dump_cp0(char *key);
 
-void (*__wbflush) (void);
-
-static void
-tx4938_write_buffer_flush(void)
-{
-	mmiowb();
-
-	__asm__ __volatile__(
-		".set	push\n\t"
-		".set	noreorder\n\t"
-		"lw	$0,%0\n\t"
-		"nop\n\t"
-		".set	pop"
-		: /* no output */
-		: "m" (*(int *)KSEG1)
-		: "memory");
-}
-
 void __init
 plat_mem_setup(void)
 {
 	board_time_init = tx4938_time_init;
-	__wbflush = tx4938_write_buffer_flush;
 	toshiba_rbtx4938_setup();
 }
 
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 83f2750..8ef8c4e 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -84,6 +84,7 @@ #include <asm/processor.h>
 #include <asm/ptrace.h>
 #include <asm/reboot.h>
 #include <asm/time.h>
+#include <asm/wbflush.h>
 #include <linux/bootmem.h>
 #include <asm/tx4938/rbtx4938.h>