[U-Boot-Users] Cache issue on MPC8xx

[U-Boot-Users] Cache issue on MPC8xx

[Qichen Huang]

Hi,
I want to apply some simple tests on MPC855T and need to turn on both
instruction- and data-cache. I have used the codes in cpu/mpc8xx/start.S(as
follows), but it crashes while trying to write IDC_ENABLE to DC_CST. Do I
have to enable the MMU first? If so,
how? I have tried the code in
linuxppc_2_4_devel/arch/ppc/kernel/head_8xx.S, it also crashes while
trying to write MSR_DR|MSR_IR to msr.

Any ideas? Thanks!

Qichen


/* ************** dcache_enable in start.S ************ */
.globl dcache_enable
dcache_enable:
#if 0
SYNC
#endif
#if 1
lis r3, 0x0400 /* Set cache mode with MMU off */
mtspr MD_CTR, r3
#endif

lis r3, IDC_INVALL at h
mtspr DC_CST, r3
#if 0
lis r3, DC_SFWT at h
mtspr DC_CST, r3
#endif
lis r3, IDC_ENABLE at h
mtspr DC_CST, r3
blr

/* ************ turn_on_mmu in head_8xx.S *********** */
bl initial_mmu

/* We now have the lower 8 Meg mapped into TLB entries, and the caches
* ready to work.
*/

turn_on_mmu:
mfmsr r0
ori r0,r0,MSR_DR|MSR_IR
mtspr SRR1,r0
blr

initial_mmu:
tlbia /* Invalidate all TLB entries */
#ifdef CONFIG_PIN_TLB
lis r8, MI_RSV4I at h
ori r8, r8, 0x1c00
#else
li r8, 0
#endif
mtspr MI_CTR, r8 /* Set instruction MMU control */

#ifdef CONFIG_PIN_TLB
lis r10, (MD_RSV4I | MD_RESETVAL)@h
ori r10, r10, 0x1c00
mr r8, r10
#else
lis r10, MD_RESETVAL at h
#endif
#ifndef CONFIG_8xx_COPYBACK
oris r10, r10, MD_WTDEF at h
#endif
mtspr MD_CTR, r10 /* Set data TLB control */

/* Now map the lower 8 Meg into the TLBs. For this quick hack,
* we can load the instruction and data TLB registers with the
* same values.
*/
lis r8, KERNELBASE at h /* Create vaddr for TLB */
ori r8, r8, MI_EVALID /* Mark it valid */
mtspr MI_EPN, r8
mtspr MD_EPN, r8
li r8, MI_PS8MEG /* Set 8M byte page */
ori r8, r8, MI_SVALID /* Make it valid */
mtspr MI_TWC, r8
mtspr MD_TWC, r8
li r8, MI_BOOTINIT /* Create RPN for address 0 */
mtspr MI_RPN, r8 /* Store TLB entry */
mtspr MD_RPN, r8
lis r8, MI_Kp at h /* Set the protection mode */
mtspr MI_AP, r8
mtspr MD_AP, r8

/* Map another 8 MByte at the IMMR to get the processor
* internal registers (among other things).
*/
#ifdef CONFIG_PIN_TLB
addi r10, r10, 0x0100
mtspr MD_CTR, r10
#endif
mfspr r9, 638 /* Get current IMMR */
andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */

mr r8, r9 /* Create vaddr for TLB */
ori r8, r8, MD_EVALID /* Mark it valid */
mtspr MD_EPN, r8
li r8, MD_PS8MEG /* Set 8M byte page */
ori r8, r8, MD_SVALID /* Make it valid */
mtspr MD_TWC, r8
mr r8, r9 /* Create paddr for TLB */
ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
mtspr MD_RPN, r8

#ifdef CONFIG_PIN_TLB
/* Map two more 8M kernel data pages.
*/
addi r10, r10, 0x0100
mtspr MD_CTR, r10

lis r8, KERNELBASE at h /* Create vaddr for TLB */
addis r8, r8, 0x0080 /* Add 8M */
ori r8, r8, MI_EVALID /* Mark it valid */
mtspr MD_EPN, r8
li r9, MI_PS8MEG /* Set 8M byte page */
ori r9, r9, MI_SVALID /* Make it valid */
mtspr MD_TWC, r9
li r11, MI_BOOTINIT /* Create RPN for address 0 */
addis r11, r11, 0x0080 /* Add 8M */
mtspr MD_RPN, r8

addis r8, r8, 0x0080 /* Add 8M */
mtspr MD_EPN, r8
mtspr MD_TWC, r9
addis r11, r11, 0x0080 /* Add 8M */
mtspr MD_RPN, r8
#endif

/* Since the cache is enabled according to the information we
* just loaded into the TLB, invalidate and enable the caches here.
* We should probably check/set other modes....later.
*/
lis r8, IDC_INVALL at h
mtspr IC_CST, r8
mtspr DC_CST, r8
lis r8, IDC_ENABLE at h
mtspr IC_CST, r8
#ifdef CONFIG_8xx_COPYBACK
mtspr DC_CST, r8
#else
/* For a debug option, I left this here to easily enable
* the write through cache mode
*/
lis r8, DC_SFWT at h
mtspr DC_CST, r8
lis r8, IDC_ENABLE at h
mtspr DC_CST, r8
#endif
blr
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[U-Boot-Users] Cache issue on MPC8xx

[Wolfgang Denk]

In message <b4ebaa9d0608240455p26c28d4ey2ebf3768f986c8c2@mail.gmail.com> you wrote:
> 
> I want to apply some simple tests on MPC855T and need to turn on both
> instruction- and data-cache. I have used the codes in cpu/mpc8xx/start.S(as

Please read the README to understand why this is not so easy.

> follows), but it crashes while trying to write IDC_ENABLE to DC_CST. Do I
> have to enable the MMU first? If so,

This is one option, but it may require lots of changes everywhere  in
the  8xx  drivers.  Another  option is to make sure you run your code
without using any  U-Boot  services  (and  interrupts  disabled)  and
disable DC before returning.

> how? I have tried the code in
> linuxppc_2_4_devel/arch/ppc/kernel/head_8xx.S, it also crashes while
> trying to write MSR_DR|MSR_IR to msr.

U-Boot is not Linux, so no big surprise...

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There are certain things men must do to remain men.
	-- Kirk, "The Ultimate Computer", stardate 4929.4

[U-Boot-Users] Cache issue on MPC8xx

[Qichen Huang]

hi,
-- Another  option is to make sure you run your codewithout using
any  U-Boot  services  (and  interrupts  disabled)  and disable DC before
returning.

I did so, but still couldn't get D-Cache enabled.


On 8/24/06, Wolfgang Denk <wd@denx.de> wrote:
>
> In message <b4ebaa9d0608240455p26c28d4ey2ebf3768f986c8c2@mail.gmail.com>
> you wrote:
> >
> > I want to apply some simple tests on MPC855T and need to turn on both
> > instruction- and data-cache. I have used the codes in
> cpu/mpc8xx/start.S(as
>
> Please read the README to understand why this is not so easy.
>
> > follows), but it crashes while trying to write IDC_ENABLE to DC_CST. Do
> I
> > have to enable the MMU first? If so,
>
> This is one option, but it may require lots of changes everywhere  in
> the  8xx  drivers.  Another  option is to make sure you run your code
> without using any  U-Boot  services  (and  interrupts  disabled)  and
> disable DC before returning.
>
> > how? I have tried the code in
> > linuxppc_2_4_devel/arch/ppc/kernel/head_8xx.S, it also crashes while
> > trying to write MSR_DR|MSR_IR to msr.
>
> U-Boot is not Linux, so no big surprise...
>
> Best regards,
>
> Wolfgang Denk
>
> --
> Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> There are certain things men must do to remain men.
>         -- Kirk, "The Ultimate Computer", stardate 4929.4
>
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[U-Boot-Users] Cache issue on MPC8xx

[Qichen Huang]

On 8/24/06, Wolfgang Denk <wd@denx.de> wrote:
> In message <b4ebaa9d0608240832i212b01aey4f?e1362002756833@mail.gmail.com> you wrote:
> >
> > I did so, but still couldn't get D-Cache enabled.
>
> Then you did something wrong.
I have been trapped in this problem for a long time. Could you tell me
some more details. Thanks.

What I did is:
 - set msr to 0.
 - disable D-cache
 - enable D-cache  <-- and it crashes here.

What is the correct way?

Qichen

>
> > ------=_Part_166562_33295880.1?156433560418
> > Content-Type: text/html; charset=ISO-8859-1
>
> DO NOT POST HTML ON THIS LIST!!!

Sorry, I didn't realize that.

>
>
> Wolfgang Denk
>
> --
> Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> Our way is peace.
>         -- Septimus, the Son Worshiper, "Bread and Circuses",
>            stardate 4040.7.
>

[U-Boot-Users] Cache issue on MPC8xx

[Jerry Van Baren]

Qichen Huang wrote:
> On 8/24/06, Wolfgang Denk <wd@denx.de> wrote:
>> In message <b4ebaa9d0608240832i212b01aey4f?e1362002756833@mail.gmail.com> you wrote:
>>> I did so, but still couldn't get D-Cache enabled.
>> Then you did something wrong.
> I have been trapped in this problem for a long time. Could you tell me
> some more details. Thanks.
> 
> What I did is:
>  - set msr to 0.
>  - disable D-cache
>  - enable D-cache  <-- and it crashes here.

This is impossibly vague.  There are many reasons for "it crashes here." 
including that it quite likely doesn't crash there.

* Are you running with instruction cache enabled?  If so, your memory 
controller is probably configured OK.  If not, it is very possible that 
your memory controller isn't handling bursts properly.

* How do you know it crashes there?  When you turn on data cache, all of 
your peripherals, including blinkin' LEDs and your UART, get cached so 
you won't see anything unless you have set up BAT registers or the MMU 
to control the data cache such that your peripherals are NOT cached.

* If you have set up the BAT and/or the MMU, did you do it correctly?

* Did you FOLLOW THE INSTRUCTIONS in the user's guide on the proper 
sequence when messing with the MSR register?  Really weird things happen 
if you don't (or so they tell me ;-).

> What is the correct way?

That is the nutshell correct way.  There are a lot of details that have 
to be done right before it works, however.  There is a devil hiding in 
each and every detail.

> Qichen

HTH,
gvb

[U-Boot-Users] Cache issue on MPC8xx

[Qichen Huang]

On 8/24/06, Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com> wrote:
> Qichen Huang wrote:
> > On 8/24/06, Wolfgang Denk <wd@denx.de> wrote:
> >> In message <b4ebaa9d0608240832i212b01aey4f?e1362002756833@mail.gmail.com> you wrote:
> >>> I did so, but still couldn't get D-Cache enabled.
> >> Then you did something wrong.
> > I have been trapped in this problem for a long time. Could you tell me
> > some more details. Thanks.
> >
> > What I did is:
> >  - set msr to 0.
> >  - disable D-cache
> >  - enable D-cache  <-- and it crashes here.
>
> This is impossibly vague.  There are many reasons for "it crashes here."
> including that it quite likely doesn't crash there.
>
> * Are you running with instruction cache enabled?  If so, your memory
> controller is probably configured OK.  If not, it is very possible that
> your memory controller isn't handling bursts properly.

I-Cache is enabled.

>
> * How do you know it crashes there?  When you turn on data cache, all of
> your peripherals, including blinkin' LEDs and your UART, get cached so
> you won't see anything unless you have set up BAT registers or the MMU
> to control the data cache such that your peripherals are NOT cached.
>

The IBAT and DBAT registers are not supported by MPC860. So, I have to
set up MMU first? It seems really complicated. :-(

> * If you have set up the BAT and/or the MMU, did you do it correctly?
>

no...

> * Did you FOLLOW THE INSTRUCTIONS in the user's guide on the proper
> sequence when messing with the MSR register?  Really weird things happen
> if you don't (or so they tell me ;-).
>
> > What is the correct way?
>
> That is the nutshell correct way.  There are a lot of details that have
> to be done right before it works, however.  There is a devil hiding in
> each and every detail.
>
> > Qichen
>
> HTH,
> gvb
>
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