* PAE and PSE ?? @ 2006-10-22 6:29 Sandeep Kumar 2006-10-22 10:15 ` Rafael J. Wysocki 0 siblings, 1 reply; 6+ messages in thread From: Sandeep Kumar @ 2006-10-22 6:29 UTC (permalink / raw) To: linux-kernel Hi all, I have read in UTLK by bovet that the linux kernel does not uses the PSE bit on an x86 machine. Then how come we have the hugetlbfs, which provides support for 4MB pages ? -- Regards, Sandeep Winners expect to win in advance. Life is a self-fulfilling prophecy. ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: PAE and PSE ?? 2006-10-22 6:29 PAE and PSE ?? Sandeep Kumar @ 2006-10-22 10:15 ` Rafael J. Wysocki 2006-10-22 23:37 ` H. Peter Anvin 0 siblings, 1 reply; 6+ messages in thread From: Rafael J. Wysocki @ 2006-10-22 10:15 UTC (permalink / raw) To: Sandeep Kumar; +Cc: linux-kernel Hi, On Sunday, 22 October 2006 08:29, Sandeep Kumar wrote: > Hi all, > I have read in UTLK by bovet that the linux kernel does not uses the > PSE bit on an x86 > machine. Then how come we have the hugetlbfs, which provides support > for 4MB pages ? AFAIK, PSE is only used when PAE is not set and then it enables the 4 MB pages. If PAE is set, the 4 MB pages are impossible because there are only 512 entries per page table, but 2 MB pages can be used instead (and you don't need to set PSE to use them). Greetings, Rafael -- You never change things by fighting the existing reality. R. Buckminster Fuller ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: PAE and PSE ?? 2006-10-22 10:15 ` Rafael J. Wysocki @ 2006-10-22 23:37 ` H. Peter Anvin 2006-10-23 10:13 ` Rafael J. Wysocki 0 siblings, 1 reply; 6+ messages in thread From: H. Peter Anvin @ 2006-10-22 23:37 UTC (permalink / raw) To: Rafael J. Wysocki; +Cc: Sandeep Kumar, linux-kernel Rafael J. Wysocki wrote: > Hi, > > On Sunday, 22 October 2006 08:29, Sandeep Kumar wrote: >> Hi all, >> I have read in UTLK by bovet that the linux kernel does not uses the >> PSE bit on an x86 >> machine. Then how come we have the hugetlbfs, which provides support >> for 4MB pages ? > > AFAIK, PSE is only used when PAE is not set and then it enables the 4 MB > pages. If PAE is set, the 4 MB pages are impossible because there are only > 512 entries per page table, but 2 MB pages can be used instead (and you don't > need to set PSE to use them). > You're wrong. PSE refers to 4 MB pages when PAE is not used, and 2 MB pages when PAE is used. In theory, you could have PAE without PSE, which would only support 4K pages. Linux uses PSE; it may or may not use PAE depending on the configuration. -hpa ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: PAE and PSE ?? 2006-10-22 23:37 ` H. Peter Anvin @ 2006-10-23 10:13 ` Rafael J. Wysocki 2006-10-23 14:10 ` H. Peter Anvin 0 siblings, 1 reply; 6+ messages in thread From: Rafael J. Wysocki @ 2006-10-23 10:13 UTC (permalink / raw) To: H. Peter Anvin; +Cc: Sandeep Kumar, linux-kernel On Monday, 23 October 2006 01:37, H. Peter Anvin wrote: > Rafael J. Wysocki wrote: > > Hi, > > > > On Sunday, 22 October 2006 08:29, Sandeep Kumar wrote: > >> Hi all, > >> I have read in UTLK by bovet that the linux kernel does not uses the > >> PSE bit on an x86 > >> machine. Then how come we have the hugetlbfs, which provides support > >> for 4MB pages ? > > > > AFAIK, PSE is only used when PAE is not set and then it enables the 4 MB > > pages. If PAE is set, the 4 MB pages are impossible because there are only > > 512 entries per page table, but 2 MB pages can be used instead (and you don't > > need to set PSE to use them). > > > > You're wrong. > > PSE refers to 4 MB pages when PAE is not used, and 2 MB pages when PAE > is used. > > In theory, you could have PAE without PSE, which would only support 4K > pages. Well, "AMD64 Architecture Programmer’s Manual" says the following: The choice of 2 Mbyte or 4 Mbyte as the large physical-page size depends on the value of CR4.PSE and CR4.PAE, as follows: - If physical-address extensions are enabled (CR4.PAE=1), the large physical-page size is 2 Mbytes, regardless of the value of CR4.PSE. - If physical-address extensions are disabled (CR4.PAE=0) and CR4.PSE=1, the large physical-page size is 4 Mbytes. - If both CR4.PAE=0 and CR4.PSE=0, the only available page size is 4 Kbytes. Greetings, Rafael -- You never change things by fighting the existing reality. R. Buckminster Fuller ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: PAE and PSE ?? 2006-10-23 10:13 ` Rafael J. Wysocki @ 2006-10-23 14:10 ` H. Peter Anvin 2006-10-23 14:14 ` Rafael J. Wysocki 0 siblings, 1 reply; 6+ messages in thread From: H. Peter Anvin @ 2006-10-23 14:10 UTC (permalink / raw) To: Rafael J. Wysocki; +Cc: Sandeep Kumar, linux-kernel Rafael J. Wysocki wrote: > > Well, "AMD64 Architecture Programmer’s Manual" says the following: > > The choice of 2 Mbyte or 4 Mbyte as the large physical-page size > depends on the value of CR4.PSE and CR4.PAE, as follows: > - If physical-address extensions are enabled (CR4.PAE=1), the > large physical-page size is 2 Mbytes, regardless of the value > of CR4.PSE. > - If physical-address extensions are disabled (CR4.PAE=0) > and CR4.PSE=1, the large physical-page size is 4 Mbytes. > - If both CR4.PAE=0 and CR4.PSE=0, the only available page > size is 4 Kbytes. > That would be a retroactive redef on the part of AMD; it probably makes sense for x86-64 if someone thinks that is may drop support for 4 MB pages at some point in the distant future. Still, I'm not sure Intel would agree with the definition as stated, although I haven't looked in the docs. This is all extremely theoretical, since there has never been a chip with PAE=1 and PSE=0, and I wouldn't expect one to appear any time soon. -hpa ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: PAE and PSE ?? 2006-10-23 14:10 ` H. Peter Anvin @ 2006-10-23 14:14 ` Rafael J. Wysocki 0 siblings, 0 replies; 6+ messages in thread From: Rafael J. Wysocki @ 2006-10-23 14:14 UTC (permalink / raw) To: H. Peter Anvin; +Cc: Sandeep Kumar, linux-kernel On Monday, 23 October 2006 16:10, H. Peter Anvin wrote: > Rafael J. Wysocki wrote: > > > > Well, "AMD64 Architecture Programmer’s Manual" says the following: > > > > The choice of 2 Mbyte or 4 Mbyte as the large physical-page size > > depends on the value of CR4.PSE and CR4.PAE, as follows: > > - If physical-address extensions are enabled (CR4.PAE=1), the > > large physical-page size is 2 Mbytes, regardless of the value > > of CR4.PSE. > > - If physical-address extensions are disabled (CR4.PAE=0) > > and CR4.PSE=1, the large physical-page size is 4 Mbytes. > > - If both CR4.PAE=0 and CR4.PSE=0, the only available page > > size is 4 Kbytes. > > > > That would be a retroactive redef on the part of AMD; it probably makes > sense for x86-64 if someone thinks that is may drop support for 4 MB > pages at some point in the distant future. Still, I'm not sure Intel > would agree with the definition as stated, although I haven't looked in > the docs. > > This is all extremely theoretical, since there has never been a chip > with PAE=1 and PSE=0, and I wouldn't expect one to appear any time soon. Agreed. Rafael -- You never change things by fighting the existing reality. R. Buckminster Fuller ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2006-10-23 14:14 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2006-10-22 6:29 PAE and PSE ?? Sandeep Kumar 2006-10-22 10:15 ` Rafael J. Wysocki 2006-10-22 23:37 ` H. Peter Anvin 2006-10-23 10:13 ` Rafael J. Wysocki 2006-10-23 14:10 ` H. Peter Anvin 2006-10-23 14:14 ` Rafael J. Wysocki
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