From: Chris Wilson <chris@chris-wilson.co.uk>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH] drm/i915: optimize ilk/snb irq handler
Date: Fri, 30 Nov 2012 11:00:12 +0000 [thread overview]
Message-ID: <453bf0$6m9dtt@azsmga001.ch.intel.com> (raw)
In-Reply-To: <1354271090-27192-1-git-send-email-daniel.vetter@ffwll.ch>
On Fri, 30 Nov 2012 11:24:50 +0100, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> We only need to read/write the south interrupt register if the
> corresponding bit is set in the north master interrupt register.
> Noticed while reading our interrupt handling code.
>
> Same optimization has already been applied on ivb in
>
> commit 0e43406bcc1868a316eea6012a0a09d992c53521
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date: Wed May 9 21:45:44 2012 +0100
>
> drm/i915: Simplify interrupt processing for IvyBridge
>
> We can take advantage that the PCH_IIR is a subordinate register to
> reduce one of the required IIR reads, and that we only need to clear
> interrupts handled to reduce the writes. And by simply tidying the code
> we can reduce the line count and hopefully make it more readable.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-11-30 11:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-30 10:24 [PATCH] drm/i915: optimize ilk/snb irq handler Daniel Vetter
2012-11-30 11:00 ` Chris Wilson [this message]
2012-12-05 11:01 ` Daniel Vetter
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