Re: [PATCH 2/5] mips: PMC MSP71xx mips common

[Marc St-Jean <Marc_St-Jean@pmc-sierra.com>]

Ralf Baechle wrote:
> On Wed, Feb 28, 2007 at 01:35:32PM -0800, Marc St-Jean wrote:
> 
>  > Ralf Baechle wrote:
>  > > On Tue, Feb 27, 2007 at 05:38:41PM +0000, Thiemo Seufer wrote:
>  > >
>  > >  > Something like
>  > >  >
>  > >  > #if LOADADDR == 0xffffffff80000000
>  > >  >       .fill   0x400
>  > >  > #endif
>  > >  >
>  > >  > but by defining an appropriate name in arch/mips/Makefile 
> instead of
>  > >  > externalizing the load-y/LOADADDR there.
>  > >
>  > > Basically a good idea but it will fail for 64-bit kernels so the test
>  > > would need to be extended to cover XKPHYS as well.  Also R2 processors
>  > > which have the c0_ebase registers do no need to reserve space for
>  > > exception handlers as they can easily move them elsewhere.
>  > >
>  > >   Ralf
>  >
>  > Hi Ralf,
>  >
>  >  From your description it sounds like not all R2 CPUs have c0_ebase 
> registers?
>  >
>  > I don't know how to check for c0_ebase from the pre-processor, the 
> test below
>  > assumes they all do.
> 
> Sorry for being ambigous.  All R2 processors have ebase.  However Linux
> happens to support older processors as well, that was my point.
> 
>  > How about something like:
>  >
>  > #if (defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) && \
>  >                  VMLINUX_LOAD_ADDRESS == CKSEG0) || \
>  >          ((defined(CONFIG_SYS_HAS_CPU_MIPS64_R1) || 
> defined(CONFIG_SYS_HAS_CPU_MIPS64_R2)) && \
>  >                  VMLINUX_LOAD_ADDRESS == XKPHYS)
>  >       .fill 0x400
>  > #endif
> 
> There are several potencial addresses in XKPHYS, so if anything:
> 
> #if !defined(CONFIG_CPU_MIPSR2) && \
>     ((VMLINUX_LOAD_ADDRESS == CKSEG0) || \
>      (VMLINUX_LOAD_ADDRESS & 0xc7ffffffffffffffUL) == XKPHYS)
> 
> However even where ebase actually exists there might be reasons not to use
> it.  So a config option might be the safe thing to do.
> 
>   Ralf

OK, I'll introduce a CONFIG_NO_EXCEPT_FILL as proposed earlier and select
it in our platform configuration section.

Marc