[Xenomai-core] [BUG] target width of shifts on 64 bits

[Jan Kiszka <jan.kiszka@domain.hid>]

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Hi Philippe,

here is an explanation of the scalable scheduler issue I face on x86_64
under different gcc compilers:

        unsigned long x = 0;
        int n = 32;

        x |= 1 << n;

The last instruction translates to:

	mov    0xfffffffffffffffc(%rbp),%ecx
	mov    $0x1,%eax
	shl    %cl,%eax
	cltq
	or     %rax,0xfffffffffffffff0(%rbp)

That means we only shift with 32-bit precision although the target type
is 64 bit. We find such code for setting the queue usage bits in
addmlq(), but probably elsewhere too. This variant lets gcc generate the
desired code:

	x |= (unsigned long)1 << n;

Compiler issue, x86_64-specific oddity, or generic 64-bit problem we may
have across the ipipe and Xenomai code (ppc64, ia64?)?

After patching nucleus/queue.h appropriately, my oopses disappear, but
RT threads still do not run (no CSW to the threads latency creates).

Jan


PS: If you are interested, I could post a modified qemu patch that
enables gdb kernel debugging under x86_64.


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