From: Jeff Garzik <jeff@garzik.org>
To: Fajun Chen <fajunchen@gmail.com>
Cc: "linux-ide@vger.kernel.org" <linux-ide@vger.kernel.org>,
Alan <alan@lxorguk.ukuu.org.uk>
Subject: Re: Question about PATA Sil680 Bus Reset Code
Date: Mon, 09 Jul 2007 12:58:20 -0400 [thread overview]
Message-ID: <4692692C.2070908@garzik.org> (raw)
In-Reply-To: <8202f4270707090946q6ae5347ascd93a2bff6c2f281@mail.gmail.com>
Fajun Chen wrote:
> Hi,
>
> Could someone help me interpret the code snippet below:
> static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes)
> {
> struct pci_dev *pdev = to_pci_dev(ap->host->dev);
> unsigned long addr = sil680_selreg(ap, 0);
> u8 reset;
>
> pci_read_config_byte(pdev, addr, &reset);
> pci_write_config_byte(pdev, addr, reset | 0x03); // ?
> udelay(25);
> pci_write_config_byte(pdev, addr, reset);
> return ata_std_softreset(ap, classes);
> }
>
> Based on Sil680 data sheet, channel reset bit is bit 2, why the reset
> code above is not "pci_write_config_byte(pdev, addr, reset | 0x04);"?
Definitely looks like a bug to me.
Channel reset is bit 2 in SiI 311x SATA family as well.
Jeff
next prev parent reply other threads:[~2007-07-09 16:58 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-07-09 16:46 Question about PATA Sil680 Bus Reset Code Fajun Chen
2007-07-09 16:58 ` Jeff Garzik [this message]
2007-07-09 18:37 ` Sergei Shtylyov
2007-07-09 18:46 ` Jeff Garzik
2007-07-09 18:51 ` Sergei Shtylyov
2007-07-09 22:09 ` Alan Cox
2007-07-10 12:58 ` Sergei Shtylyov
2007-07-10 22:00 ` Bartlomiej Zolnierkiewicz
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