[U-Boot-Users] MPC8540, UPM Writeburst generating also read bursts

[U-Boot-Users] MPC8540, UPM Writeburst generating also read bursts

[Gerrit Van de Velde]

Hello all,

I'm having a couple of troubles on the MPC8540 on our board. It's
derived from the MPC8540ADS board but we added a Spartan 3 FPGA with
DDR memory on the local plus bus (with two chip selects for different
memory windows in the fpga memory mapped driver) and we implemented a
UPM (A) for 8 burst writes and reads on the bus. We're using U-Boot
1.2 and Linux 2.6.20.3. In debug, we can use Chipscope to view the
local plus bus signals.

The problem is that every write burst that we issue generates an awful
lot of read accesses to the same chip select / address range. We're
clueless on what exactly is generating this. We've been thinking about
caching issues, TLB setup, UPM misconfiguration, fishy driver code
(memory mapped), or a fishy user application. Nothing of those seems
wrong to us.

I was trying to get a write burst going to the FPGA from U-Boot but it
seems that it only issues single word accesses on the bus. Is it
actually possible to trigger the UPM burst sequencing at all from
U-Boot?

If anyone had the same issues or something similar, I would like to
know how you fixed it or how to debug it. I could give many more
information or code snippets but I'll save that for later when someone
has a good idea about what to check out.

To give a comparison about the bus access speeds to the local plus bus
and the interface: our FPGA interface can give about 500Mpbs from FPGA
DDR memory into the CPU's gigabit ethernet, but writing to the same
memory is below 10Mbps due to the excessive reads.

I don't know if this list is actually the best option to get advice
(maybe off topic), but I just don't know any better place to go.

Any help in this case is appreciated,

Regards,
Gerrit Van de Velde

[U-Boot-Users] MPC8540, UPM Writeburst generating also read bursts

[Clemens Koller]

Hello, Gerrit!

Please don't top-post and please don't remove the list. (use reply-to-all)
(and please move this thread over to linuxppc-embedded, as we are OT here)

Gerrit Van de Velde schrieb:
> Your input is appreciated. But .. I have verified the ECC, it's turned off.
> Nowadays it's configurable with CONFIG_DDR_ECC or something and I've
> used your if statement in the code to check if it was enabled but it
> was going to the else.

Fine.

> But I was just wondering, is DMA really needed to have decent
> througput? Without doing anything with DMA, we attain 500Mbit/s via
> our Gbit link from FPGA DDR memory up to a client PC. The FPGA is
> using a UPM with write/read bursts only.

You don't have single read and write instructions in your UPM?
Please post your UPM table.

> Only the other way is too
> slow at this time (upload from pc to embedded system).

Do you access the DDR memory aligned in 32byte cacheline sizes?
The UPM propably cannot burst unaligned chunks properly.
(I'm not sure about that, comments are welcome).
500MBit/s should be easy to handle with the UPM, if done right.

> I'm asking this because
> 1* I'm not a DMA expert
> 2* I must be sure that the slowness is not caused by not using DMA

1) It makes sense to use the DMA to offload the CPU for copying bulk
data if the CPU can be used for other stuff.

2) Can you first make sure that your Gbit link is working fine by copying
data from/to the CPU's memory without using the UPM?

I guess you will need to post more information about your
system (schematics, code, UPM)...

Regards,
-- 
Clemens Koller
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Re: [U-Boot-Users] MPC8540, UPM Writeburst generating also read bursts

[Gerrit Van de Velde]

Hello again,

> Please don't top-post and please don't remove the list. (use reply-to-all)
> (and please move this thread over to linuxppc-embedded, as we are OT here)

Ok, I'll never do that again. And the topic has been moved.

> You don't have single read and write instructions in your UPM?
> Please post your UPM table.

I do have single reads and writes. The UPM is as follows (taken from
the upmtool output)

/* MxMR Configuration Code */
unsigned long MAMR = 0x40000;
unsigned long MBMR = 0x40000;
unsigned long MCMR = 0x40000;

/* UPM Table Configuration Code */
static unsigned long UPMATable[] =
{
	0x0faffc00,  0x0faffc00,  0x0fafdc04,  0x3fbffc01, //Words 0 to 3
	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 4 to 7
	0x0ffffc00,  0x0ffffc00,  0x0ffffc0c,  0x0ffffc0c, //Words 8 to 11
	0x0ffffc0c,  0x0ffffc0c,  0x0ffffc0c,  0x0ffffc0c, //Words 12 to 15
	0x0ffffc0c,  0x0ffffc04,  0x3ffffc01,  0xfffffc00, //Words 16 to 19
	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 20 to 23
	0x0fa3fc00,  0x0fa3fc00,  0x0fa3fc04,  0x3fb7fc01, //Words 24 to 27
	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 28 to 31
	0x0ff3fc00,  0x0ff3fc00,  0x0ff3fc0c,  0x0ff3fc0c, //Words 32 to 35
	0x0ff3fc0c,  0x0ff3fc0c,  0x0ff3fc0c,  0x0ff3fc0c, //Words 36 to 39
	0x0ff3fc0c,  0x0ff3fc04,  0x3ff7fc00,  0xfffffc01, //Words 40 to 43
	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 44 to 47
	0xfffffc00,  0xfffffc01,  0xfffffc00,  0xfffffc00, //Words 48 to 51
	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 52 to 55
	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 56 to 59
	0xfffffc00,  0xfffffc01,  0xfffffc00,  0xfffffc01  //Words 60 to 63
};

> Do you access the DDR memory aligned in 32byte cacheline sizes?
> The UPM propably cannot burst unaligned chunks properly.
> (I'm not sure about that, comments are welcome).
> 500MBit/s should be easy to handle with the UPM, if done right.

Yes target addresses are aligned to 32 byte words. I 'm not sure what
you mean with cachelines.

> 1) It makes sense to use the DMA to offload the CPU for copying bulk
> data if the CPU can be used for other stuff.

Ok, but currently our MPC8540 is a bit overkill, maybe later in the
life of our board it will be come necessary but at least not now.

> 2) Can you first make sure that your Gbit link is working fine by copying
> data from/to the CPU's memory without using the UPM?

That's something I should try first indeed, I'll update you/the list
if I know about the results

> I guess you will need to post more information about your
> system (schematics, code, UPM)...

I'll do that when UPM-less writes are much faster and you don't see
anything strange in the UPM table.

Regards,
Gerrit Van de Velde