[U-Boot-Users] DP83848 PHY for AT91RM9200 board

[U-Boot-Users] DP83848 PHY for AT91RM9200 board

[Marco Cavallini]

Hi,
I'm using u-boot-1.1.4 (quite old but I must use it)
with my AT91RM9200 based board.
I replaced DM9161 with a new DP83848 PHY ethernet physical layer 
transceiver.

So I'm backporting Sergey Kubushyn's driver
National Semiconductor DP83848 PHY Driver for TI DaVinci (TMS320DM644x) 
adapting it for my AT91RM9200 based board.

I left eth_init() like it was for DM9161 because connections are the same.
The problem I'm facing to is that PHY is not detected when I call 
dp83848_is_phy_connected (see below).

I wonder if anybody used DP83848 PHY before and maybe could give me a hint.

int dp83848_is_phy_connected(AT91PS_EMAC phy_addr)
{
	u_int16_t	id1, id2;

	printf ("*** dp83848_is_phy_connected\n");

	at91rm9200_EmacEnableMDIO (phy_addr);
	at91rm9200_EmacReadPhy(phy_addr, DP83848_PHYID1_REG, &id1) ;
	at91rm9200_EmacReadPhy(phy_addr, DP83848_PHYID2_REG, &id2) ;
	at91rm9200_EmacDisableMDIO (phy_addr);

	printf ("phy_addr=%X - id1=%X - id2=%X\n", phy_addr, id1, id2);
	// here I always get 0xFFFBC000 0xFFFF 0xFFFF

	if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
		return(1);

	return(0);
}

TIA
-- 
Marco Cavallini
Koan s.a.s. - Bergamo - Italia
Embedded and Real-Time Software Engineering
http://www.KoanSoftware.com  -  http://www.KaeilOS.com

[U-Boot-Users] DP83848 PHY for AT91RM9200 board

[ksi at koi8.net]

On Mon, 1 Oct 2007, Marco Cavallini wrote:

Here is DP83848 driver code for AT91RM9200 for u-boot-1.1.4 :) Just from my
archives...

Something might be missing but the driver source and the header files are
there...

> Hi,
> I'm using u-boot-1.1.4 (quite old but I must use it)
> with my AT91RM9200 based board.
> I replaced DM9161 with a new DP83848 PHY ethernet physical layer
> transceiver.
>
> So I'm backporting Sergey Kubushyn's driver
> National Semiconductor DP83848 PHY Driver for TI DaVinci (TMS320DM644x)
> adapting it for my AT91RM9200 based board.
>
> I left eth_init() like it was for DM9161 because connections are the
> same.
> The problem I'm facing to is that PHY is not detected when I call
> dp83848_is_phy_connected (see below).
>
> I wonder if anybody used DP83848 PHY before and maybe could give me a
> hint.
>
> int dp83848_is_phy_connected(AT91PS_EMAC phy_addr)
> {
> 	u_int16_t	id1, id2;
>
> 	printf ("*** dp83848_is_phy_connected\n");
>
> 	at91rm9200_EmacEnableMDIO (phy_addr);
> 	at91rm9200_EmacReadPhy(phy_addr, DP83848_PHYID1_REG, &id1) ;
> 	at91rm9200_EmacReadPhy(phy_addr, DP83848_PHYID2_REG, &id2) ;
> 	at91rm9200_EmacDisableMDIO (phy_addr);
>
> 	printf ("phy_addr=%X - id1=%X - id2=%X\n", phy_addr, id1, id2);
> 	// here I always get 0xFFFBC000 0xFFFF 0xFFFF
>
> 	if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
> 		return(1);
>
> 	return(0);
> }
>
> TIA
> -- 
> Marco Cavallini
> Koan s.a.s. - Bergamo - Italia
> Embedded and Real-Time Software Engineering
> http://www.KoanSoftware.com  -  http://www.KaeilOS.com
>
> ------------------------------------------------------------------------
> -
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---
******************************************************************
*  KSI at home    KOI8 Net  < >  The impossible we do immediately.  *
*  Las Vegas   NV, USA   < >  Miracles require 24-hour notice.   *
******************************************************************
-------------- next part --------------
diff -urN --show-c-function u-boot-1.1.4.orig/board/vadatech/dp83848.c u-boot-1.1.4/board/vadatech/dp83848.c
--- u-boot-1.1.4.orig/board/vadatech/dp83848.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-1.1.4/board/vadatech/dp83848.c	2006-02-16 15:34:56.000000000 -0800
@@ -0,0 +1,279 @@
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Sergey Kubushin <ksi@koi8.net>: Changed for DP83848 PHY 08/31/2005
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <dp83848.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ *	dp84848_IsPhyConnected
+ * Description:
+ *	Reads the 2 PHY ID registers
+ * Arguments:
+ *	p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ *	TRUE - if id read successfully
+ *	FALSE- if error
+ */
+static unsigned int dp83848_IsPhyConnected( AT91PS_EMAC p_mac )
+{
+    unsigned short Id1, Id2;
+
+    at91rm9200_EmacEnableMDIO( p_mac );
+    at91rm9200_EmacReadPhy( p_mac, DP83848_PHYID1_REG, &Id1 );
+    at91rm9200_EmacReadPhy( p_mac, DP83848_PHYID2_REG, &Id2 );
+    at91rm9200_EmacDisableMDIO (p_mac);
+
+    if( (Id1 == DP83848_PHYID1_OUI) && (Id2 == DP83848_PHYID2_OUI) )
+    {
+	return TRUE;
+    }
+
+    return FALSE;
+}
+
+/*
+ * Name:
+ *	dp83848_GetLinkSpeed
+ * Description:
+ *	Link parallel detection status of MAC is checked and set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to MAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dp83848_GetLinkSpeed( AT91PS_EMAC p_mac )
+{
+    unsigned short stat1, stat2;
+
+    if( !at91rm9200_EmacReadPhy( p_mac, DP83848_STAT_REG, &stat1 ) )
+    {
+	return FALSE;
+    }
+
+    if( !(stat1 & DP83848_LINK_STATUS) )	/* link status up? */
+    {
+	return FALSE;
+    }
+
+    if( !at91rm9200_EmacReadPhy( p_mac, DP83848_PHY_STAT_REG, &stat2 ) )
+    {
+	return FALSE;
+    }
+
+    if ( !(stat2 & DP83848_SPEED) && (stat2 & DP83848_DUPLEX) ) 
+    {
+	/*set Emac for 100BaseTX and Full Duplex  */
+	p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+	return TRUE;
+    }
+
+    if ( (stat2 & DP83848_SPEED) && (stat2 & DP83848_DUPLEX) )
+    {
+	/*set MII for 10BaseT and Full Duplex  */
+	p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+			  ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) |
+			  AT91C_EMAC_FD;
+	return TRUE;
+    }
+
+    if ( !(stat2 & DP83848_SPEED) && !(stat2 & DP83848_DUPLEX) )
+    {
+	/*set MII for 100BaseTX and Half Duplex  */
+	p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+			  ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) |
+			  AT91C_EMAC_SPD;
+	return TRUE;
+    }
+
+     if ( (stat2 & DP83848_SPEED) && !(stat2 & DP83848_DUPLEX) )
+    {
+	/*set MII for 10BaseT and Half Duplex  */
+	p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+	return TRUE;
+    }
+
+    return FALSE;
+}
+
+
+/*
+ * Name:
+ *	dp83848_InitPhy
+ * Description:
+ *	MAC starts checking its link by using parallel detection and
+ *	Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dp83848_InitPhy( AT91PS_EMAC p_mac )
+{
+    UCHAR ret = TRUE;
+    unsigned short IntValue = 0;
+
+    at91rm9200_EmacEnableMDIO( p_mac );
+
+    if( !dp83848_GetLinkSpeed( p_mac ) ) 
+    {
+	/* Wait and try once more  */
+	udelay(100000);
+        ret = dp83848_GetLinkSpeed(p_mac);
+    }
+
+    /* Disable PHY Interrupts */
+    at91rm9200_EmacWritePhy (p_mac, DP83848_PHY_INTR_CTRL_REG, &IntValue);
+
+    at91rm9200_EmacDisableMDIO( p_mac );
+
+    return( ret );
+}
+
+
+/*
+ * Name:
+ *	dp83848_AutoNegotiate
+ * Description:
+ *	MAC Autonegotiates with the partner status of same is set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	dev - pointer to struct net_device
+ * Return value:
+ *	TRUE - if link status set successfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dp83848_AutoNegotiate( AT91PS_EMAC p_mac, int *status )
+{
+    unsigned short value;
+    unsigned short PhyAnar;
+    unsigned short PhyAnalpar;
+
+    /* Set dp83848 control register */
+    if( !at91rm9200_EmacReadPhy( p_mac, DP83848_CTL_REG, &value ) )
+    {
+	return FALSE;
+    }
+
+    value &= ~DP83848_AUTONEG;	/* remove autonegotiation enable */
+    value |= DP83848_ISOLATE;	/* Electrically isolate PHY */
+    if( !at91rm9200_EmacWritePhy( p_mac, DP83848_CTL_REG, &value ) )
+    {
+	return FALSE;
+    }
+
+    /* Set the Auto_negotiation Advertisement Register 
+     * MII advertising for Next page, 100BaseTxFD and HD, 
+     * 10BaseTFD and HD, IEEE 802.3 
+     */
+    PhyAnar = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
+	      DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
+    if( !at91rm9200_EmacWritePhy( p_mac, DP83848_ANA_REG, &PhyAnar ) )
+    {
+	return FALSE;
+    }
+
+    /* Read the Control Register     */
+    if( !at91rm9200_EmacReadPhy( p_mac, DP83848_CTL_REG, &value ) )
+    {
+	return FALSE;
+    }
+
+    value |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
+    if( !at91rm9200_EmacWritePhy( p_mac, DP83848_CTL_REG, &value ) )
+    {
+	return FALSE;
+    }
+
+    /* Restart Auto_negotiation  */
+    value |= DP83848_RESTART_AUTONEG;
+    if( !at91rm9200_EmacWritePhy( p_mac, DP83848_CTL_REG, &value ) )
+    {
+	return FALSE;
+    }
+
+    /*check AutoNegotiate complete */
+    udelay( 10000 );
+    at91rm9200_EmacReadPhy( p_mac, DP83848_STAT_REG, &value );
+    if( !(value & DP83848_AUTONEG_COMP) )
+    {
+	return FALSE;
+    }
+
+    /* Get the AutoNeg Link partner base page */
+    if( !at91rm9200_EmacReadPhy( p_mac, DP83848_ANLPA_REG, &PhyAnalpar ) )
+    {
+	return FALSE;
+    }
+
+    if( (PhyAnar & DP83848_TX_FDX) && (PhyAnalpar & DP83848_TX_FDX) ) 
+    {
+	/*set MII for 100BaseTX and Full Duplex  */
+	p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+	return TRUE;
+    }
+
+    if( (PhyAnar & DP83848_10_FDX) && (PhyAnalpar & DP83848_10_FDX) ) 
+    {
+	/*set MII for 10BaseT and Full Duplex  */
+	p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+			  ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) |
+			  AT91C_EMAC_FD;
+	return TRUE;
+    }
+
+    return FALSE;
+}
+
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface( AT91PS_PhyOps p_phyops )
+{
+    p_phyops->Init           = dp83848_InitPhy;
+    p_phyops->IsPhyConnected = dp83848_IsPhyConnected;
+    p_phyops->GetLinkSpeed   = dp83848_GetLinkSpeed;
+    p_phyops->AutoNegotiate  = dp83848_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+
+#endif	/* CONFIG_DRIVER_ETHER */
-------------- next part --------------
diff -urN --show-c-function u-boot-1.1.4.orig/include/dp83848.h u-boot-1.1.4/include/dp83848.h
--- u-boot-1.1.4.orig/include/dp83848.h	1969-12-31 16:00:00.000000000 -0800
+++ u-boot-1.1.4/include/dp83848.h	2006-02-16 15:34:56.000000000 -0800
@@ -0,0 +1,96 @@
+/*
+ * NOTE:	DP83848 ethernet Physical layer
+ *
+ * Version:	1.0.0	08/31/2005
+ *
+ * Authors:	Sergey Kubushin
+ *
+ *
+ *		This program is free software; you can redistribute it and/or
+ *		modify it under the terms of the GNU General Public License
+ *		as published by the Free Software Foundation; either version
+ *		2 of the License, or (at your option) any later version.
+ */
+
+
+/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
+
+#define	DP83848_CTL_REG         0x0  /* Basic Mode Control Reg */
+#define DP83848_STAT_REG        0x1  /* Basic Mode Status Reg */
+#define DP83848_PHYID1_REG      0x2  /* PHY Idendifier Reg 1 */
+#define DP83848_PHYID2_REG      0x3  /* PHY Idendifier Reg 2 */
+#define DP83848_ANA_REG	        0x4  /* Auto_Neg Advt Reg  */
+#define DP83848_ANLPA_REG       0x5  /* Auto_neg Link Partner Ability Reg */
+#define DP83848_ANE_REG	        0x6  /* Auto-neg Expansion Reg  */
+#define DP83848_PHY_STAT_REG    0x10 /* PHY Status Register  */
+#define DP83848_PHY_INTR_CTRL_REG 0x11	/* PHY Interrupt Control Register */
+#define DP83848_PHY_CTRL_REG    0x19 /* PHY Status Register  */
+
+/*--Bit definitions: DP83848_CTL_REG */
+#define DP83848_RESET   	 (1 << 15)  /* 1= S/W Reset */
+#define DP83848_LOOPBACK	 (1 << 14)  /* 1=loopback Enabled */
+#define DP83848_SPEED_SELECT	 (1 << 13) 
+#define DP83848_AUTONEG          (1 << 12)
+#define DP83848_POWER_DOWN       (1 << 11)
+#define DP83848_ISOLATE          (1 << 10)
+#define DP83848_RESTART_AUTONEG  (1 << 9)
+#define DP83848_DUPLEX_MODE      (1 << 8)
+#define DP83848_COLLISION_TEST   (1 << 7)
+
+/*--Bit definitions: DP83848_STAT_REG */
+#define DP83848_100BASE_T4        (1 << 15)
+#define DP83848_100BASE_TX_FD     (1 << 14)
+#define DP83848_100BASE_TX_HD     (1 << 13)
+#define DP83848_10BASE_T_FD       (1 << 12)
+#define DP83848_10BASE_T_HD       (1 << 11)
+#define DP83848_MF_PREAMB_SUPPR   (1 << 6)
+#define DP83848_AUTONEG_COMP      (1 << 5)
+#define DP83848_RMT_FAULT         (1 << 4)
+#define DP83848_AUTONEG_ABILITY   (1 << 3)
+#define DP83848_LINK_STATUS       (1 << 2)
+#define DP83848_JABBER_DETECT     (1 << 1)
+#define DP83848_EXTEND_CAPAB      (1 << 0)
+
+/*--definitions: DP83848_PHYID1 */
+#define DP83848_PHYID1_OUI	 0x2000
+#define DP83848_PHYID2_OUI	 0x5c90
+
+/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
+#define DP83848_NP               (1 << 15)
+#define DP83848_ACK              (1 << 14)
+#define DP83848_RF               (1 << 13)
+#define DP83848_PAUSE            (1 << 10)
+#define DP83848_T4               (1 << 9)
+#define DP83848_TX_FDX           (1 << 8)
+#define DP83848_TX_HDX           (1 << 7)
+#define DP83848_10_FDX           (1 << 6)
+#define DP83848_10_HDX           (1 << 5)
+#define DP83848_AN_IEEE_802_3	  0x0001
+
+/*--Bit definitions: DP83848_ANER */
+#define DP83848_PDF              (1 << 4)
+#define DP83848_LP_NP_ABLE       (1 << 3)
+#define DP83848_NP_ABLE          (1 << 2)
+#define DP83848_PAGE_RX          (1 << 1)
+#define DP83848_LP_AN_ABLE       (1 << 0)
+
+/*--Bit definitions: DP83848_PHY_STAT */
+#define DP83848_RX_ERR_LATCH     (1 << 13)
+#define DP83848_POLARITY_STAT    (1 << 12)
+#define DP83848_FALSE_CAR_SENSE  (1 << 11)
+#define DP83848_SIG_DETECT       (1 << 10)
+#define DP83848_DESCRAM_LOCK     (1 << 9)
+#define DP83848_PAGE_RCV         (1 << 8)
+#define DP83848_PHY_RMT_FAULT    (1 << 6)
+#define DP83848_JABBER           (1 << 5)
+#define DP83848_AUTONEG_COMPLETE (1 << 4)
+#define DP83848_LOOPBACK_STAT    (1 << 3)
+#define DP83848_DUPLEX           (1 << 2)
+#define DP83848_SPEED            (1 << 1)
+#define DP83848_LINK             (1 << 0)
+
+/******************  function prototypes **********************/
+static unsigned int  dp83848_IsPhyConnected(AT91PS_EMAC p_mac);
+static unsigned char dp83848_GetLinkSpeed(AT91PS_EMAC p_mac);
+static unsigned char dp83848_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
+static unsigned char dp83848_InitPhy(AT91PS_EMAC p_mac);

[U-Boot-Users] DP83848 PHY for AT91RM9200 board

[Marco Cavallini]

ksi at koi8.net ha scritto:
> On Mon, 1 Oct 2007, Marco Cavallini wrote:
> 
> Here is DP83848 driver code for AT91RM9200 for u-boot-1.1.4 :) Just from my
> archives...
> 
> Something might be missing but the driver source and the header files are
> there...
> 
>> Hi,
>> I'm using u-boot-1.1.4 (quite old but I must use it)
>> with my AT91RM9200 based board.
>> I replaced DM9161 with a new DP83848 PHY ethernet physical layer
>> transceiver.
>>
>> So I'm backporting Sergey Kubushyn's driver
>> National Semiconductor DP83848 PHY Driver for TI DaVinci (TMS320DM644x)
>> adapting it for my AT91RM9200 based board.
>>
>> I left eth_init() like it was for DM9161 because connections are the
>> same.
>> The problem I'm facing to is that PHY is not detected when I call
>> dp83848_is_phy_connected (see below).
>>
>> I wonder if anybody used DP83848 PHY before and maybe could give me a
>> hint.
>>
>> int dp83848_is_phy_connected(AT91PS_EMAC phy_addr)
>> {
>>     u_int16_t    id1, id2;
>>
>>     printf ("*** dp83848_is_phy_connected\n");
>>
>>     at91rm9200_EmacEnableMDIO (phy_addr);
>>     at91rm9200_EmacReadPhy(phy_addr, DP83848_PHYID1_REG, &id1) ;
>>     at91rm9200_EmacReadPhy(phy_addr, DP83848_PHYID2_REG, &id2) ;
>>     at91rm9200_EmacDisableMDIO (phy_addr);
>>
>>     printf ("phy_addr=%X - id1=%X - id2=%X\n", phy_addr, id1, id2);
>>     // here I always get 0xFFFBC000 0xFFFF 0xFFFF
>>
>>     if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
>>         return(1);
>>
>>     return(0);
>> }
>>
>> TIA
>> -- 
>> Marco Cavallini



Hi Sergey,
thank you for answering.
we have just discovered an hardware mistake on PFBOUT-PFBIN2 pins
now I can detect the PHY using your code

Thank you very much

Best regards
-- 
Marco Cavallini
Koan s.a.s. - Bergamo - Italia
Embedded and Real-Time Software Engineering
http://www.KoanSoftware.com  -  http://www.KaeilOS.com

[U-Boot-Users] DP83848 PHY for AT91RM9200 board

[ksi at koi8.net]

On Mon, 1 Oct 2007, Marco Cavallini wrote:

> ksi at koi8.net ha scritto:
>> On Mon, 1 Oct 2007, Marco Cavallini wrote:
>> 
>> Here is DP83848 driver code for AT91RM9200 for u-boot-1.1.4 :) Just
> from my
>> archives...
>> 
>> Something might be missing but the driver source and the header files
> are
>> there...
>> 
>>> Hi,
>>> I'm using u-boot-1.1.4 (quite old but I must use it)
>>> with my AT91RM9200 based board.
>>> I replaced DM9161 with a new DP83848 PHY ethernet physical layer
>>> transceiver.
>>> 
>>> So I'm backporting Sergey Kubushyn's driver
>>> National Semiconductor DP83848 PHY Driver for TI DaVinci
> (TMS320DM644x)
>>> adapting it for my AT91RM9200 based board.
>>> 
>>> I left eth_init() like it was for DM9161 because connections are the
>>> same.
>>> The problem I'm facing to is that PHY is not detected when I call
>>> dp83848_is_phy_connected (see below).
>>> 
>>> I wonder if anybody used DP83848 PHY before and maybe could give me a
>>> hint.
>>> 
>>> int dp83848_is_phy_connected(AT91PS_EMAC phy_addr)
>>> {
>>>     u_int16_t    id1, id2;
>>>
>>>     printf ("*** dp83848_is_phy_connected\n");
>>>
>>>     at91rm9200_EmacEnableMDIO (phy_addr);
>>>     at91rm9200_EmacReadPhy(phy_addr, DP83848_PHYID1_REG, &id1) ;
>>>     at91rm9200_EmacReadPhy(phy_addr, DP83848_PHYID2_REG, &id2) ;
>>>     at91rm9200_EmacDisableMDIO (phy_addr);
>>>
>>>     printf ("phy_addr=%X - id1=%X - id2=%X\n", phy_addr, id1, id2);
>>>     // here I always get 0xFFFBC000 0xFFFF 0xFFFF
>>>
>>>     if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
>>>         return(1);
>>>
>>>     return(0);
>>> }
>>> 
>>> TIA
>>> -- 
>>> Marco Cavallini
>
>
>
> Hi Sergey,
> thank you for answering.
> we have just discovered an hardware mistake on PFBOUT-PFBIN2 pins
> now I can detect the PHY using your code

Please be aware that for AT91RM9200 you should read the negotiated
connection status from the PHY and setup EMAC accordingly. That is in that
old code.

Davinci, on the other hand, doesn't require it (as a matter of fact it
doesn't even have provision for setting those parameters for EMAC,) it's
more automated so PHY code is different. And PHY presence is detected by
reading DaVinci register that monitors PHY presence.

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