[Qemu-devel] [PATCH] sparc32 use stq_* for 64bit stores

[Robert Reif <reif@earthlink.net>]

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Use stq_* for 64 bit stores.

This fixes one bug where T1 was used twice rather than T1 and T2.

Should the address be 64 bit alligned?  i.e. T0 & ~7 rather than T0 & ~3?

Should these unaligned address cause traps?


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Index: target-sparc/op_helper.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.44
diff -p -u -r1.44 op_helper.c
--- target-sparc/op_helper.c	14 Oct 2007 17:07:21 -0000	1.44
+++ target-sparc/op_helper.c	14 Oct 2007 18:28:37 -0000
@@ -515,8 +515,7 @@ void helper_st_asi(int asi, int size)
             stl_user(T0 & ~3, T1);
             break;
         case 8:
-            stl_user(T0 & ~3, T1);
-            stl_user((T0 + 4) & ~3, T2);
+            stq_user(T0 & ~3, ((uint64_t)T1 << 32) | T2);
             break;
         }
         break;
@@ -533,8 +532,7 @@ void helper_st_asi(int asi, int size)
             stl_kernel(T0 & ~3, T1);
             break;
         case 8:
-            stl_kernel(T0 & ~3, T1);
-            stl_kernel((T0 + 4) & ~3, T2);
+            stq_kernel(T0 & ~3, ((uint64_t)T1 << 32) | T2);
             break;
         }
         break;
@@ -591,8 +589,7 @@ void helper_st_asi(int asi, int size)
                 stl_phys(T0 & ~3, T1);
                 break;
             case 8:
-                stl_phys(T0 & ~3, T1);
-                stl_phys((T0 + 4) & ~3, T2);
+                stq_phys(T0 & ~3, ((uint64_t)T1 << 32) | T2);
                 break;
             }
         }
@@ -615,10 +612,8 @@ void helper_st_asi(int asi, int size)
                            | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
                 break;
             case 8:
-                stl_phys((target_phys_addr_t)(T0 & ~3)
-                           | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
-                stl_phys((target_phys_addr_t)((T0 + 4) & ~3)
-                           | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
+                stq_phys((target_phys_addr_t)(T0 & ~3)
+                           | ((target_phys_addr_t)(asi & 0xf) << 32), ((uint64_t)T1 << 32) | T2);
                 break;
             }
         }